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NDS355AN
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description Features
January 1997
SuperSOTTM-3 N-Channel logic level enhancement mode
power field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very high
density process is especially tailored to minimize on-state
resistance. These devices are particularly suited for low voltage
applications in notebook computers, portable phones, PCMCIA
cards, and other battery powered circuits where fast
switching, and low in-line power loss are needed in a very small
outline surface mount package.
1.7A, 30 V, R
R
= 0.125 Ω @ VGS = 4.5 V
DS(ON)
= 0.085 Ω @ VGS = 10 V.
DS(ON)
Industry standard outline SOT-23 surface mount package
using proprietary SuperSOTTM-3 design for superior
thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
Compact industry standard SOT-23 surface mount
package.
_______________________________________________________________________________
D
G
S
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
Symbol Parameter NDS355AN Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 30 V
Gate-Source Voltage - Continuous ±20 V
Maximum Drain Current - Continuous (Note 1a) 1.7 A
- Pulsed 10
P
D
TJ,T
Maximum Power Dissipation (Note 1a) 0.5 W
(Note 1b)
Operating and Storage Temperature Range -55 to 150 °C
STG
0.46
THERMAL CHARACTERISTICS
R
JA
θ
R
JC
θ
© 1997 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Ambient (Note 1a) 250 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W
NDS355AN Rev.C
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Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 30 V
Zero Gate Voltage Drain Current
VDS = 24 V, V
GS
= 0 V
TJ =125°C
1 µA
10 µA
Gate - Body Leakage, Forward VGS = 20 VDS = 0 V 100 nA
Gate - Body Leakage, Reverse
VGS = -20 V, VDS = 0 V
-100 nA
ON CHARACTERISTICS (Note 2)
V
R
I
D(ON)
g
GS(th)
DS(ON)
FS
Gate Threshold Voltage VDS = VGS, ID = 250 µA 1 1.6 2 V
0.5 1.2 1.5
0.105 0.125
0.16 0.23
0.065 0.085
6 A
3.5 S
Static Drain-Source On-Resistance
On-State Drain Current
Forward Transconductance
TJ =125°C
VGS = 4.5 V, ID = 1.7 A
TJ =125°C
VGS = 10 V, ID = 1.9 A
VGS = 4.5 V, VDS = 5 V
VDS = 5 V, ID= 1.7 A
Ω
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 135 pF
VDS = 15 V, VGS = 0 V,
f = 1.0 MHz
Reverse Transfer Capacitance 48 pF
195 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
t
t
t
t
Q
Q
Q
d(on)
r
d(off)
f
d(on)
r
d(off)
f
g
gs
gd
Turn - On Delay Time VDD = 10 V, ID = 1 A,
Turn - On Rise Time 13 25 ns
VGS = 10 V, R
GEN
= 6 Ω
10 20 ns
Turn - Off Delay Time 13 25 ns
Turn - Off Fall Time 4 10 ns
Turn - On Delay Time VDD = 5 V, ID = 1 A,
Turn - On Rise Time 32 60 ns
VGS = 4.5 V, R
GEN
= 6 Ω
10 20 ns
Turn - Off Delay Time 10 20 ns
Turn - Off Fall Time 5 10 ns
Total Gate Charge VDS = 10 V, ID = 1.7 A,
Gate-Source Charge 0.8 nC
VGS = 5 V
3.5 5 nC
Gate-Drain Charge 1.7 nC
NDS355AN Rev.C
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Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
I
SM
V
SD
Notes:
1. R
design while R
P
Typical R
a. 250
Maximum Continuous Drain-Source Diode Forward Current 0.42 A
Maximum Pulsed Drain-Source Diode Forward Current 10 A
Drain-Source Diode Forward Voltage VGS = 0 V, IS =0.42 A (Note 2) 0.8 1.2 V
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
D
is determined by the user's board design.
CA
θ
T
−T
T
J
(t)
=
R
θJ A
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
JA
θ
b. 270oC/W when mounted on a 0.001 in2 pad of 2oz copper.
−T
J
A
(t)
o
A
=
R
θ
J C
C/W when mounted on a 0.02 in2 pad of 2oz copper.
2
= I
(t) × R
DS (ON ) T
D
+R
(t)
θ
CA
J
is guaranteed by
JC
θ
1a
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
1b
NDS355AN Rev.C
Page 4
J
D
Typical Electrical Characteristics
10
V =10V
GS
8
7.0
6.0
5.0
4.5
4.0
6
4
2
D
I , DRAIN-SOURCE CURRENT (A)
0
0 0.5 1 1.5 2 2.5 3
V , DRAIN-SOURCE VOLTAGE (V)
DS
3.5
3.0
Figure 1. On-Region Characteristics.
1.6
ID = 1.6A
VGS= 4.5V
1.4
1.2
1
DS(ON)
R , NORMALIZED
0.8
DRAIN-SOURCE ON-RESISTANCE
0.6
-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)
2
1.8
1.6
V = 3.5V
GS
1.4
1.2
1
DS(on)
R , NORMALIZED
0.8
0.6
DRAIN-SOURCE ON-RESISTANCE
0.4
0 2 4 6 8 10
4.0
4.5
5.0
I , DRAIN CURRENT (A)
6.0
Figure 2. On-Resistance Variation
with Drain Current and Gate Voltage.
2
V = 4.5 V
GS
1.8
1.6
1.4
1.2
1
DS(on)
0.8
R , NORMALIZED
0.6
DRAIN-SOURCE ON-RESISTANCE
0.4
0 1 2 3 4 5
T = 125°C
J
I , DRAIN CURRENT (A)
D
25°C
-55°C
7
10
Figure 3. On-Resistance Variation
with Temperature.
5
V = 5.0V
DS
4
3
2
D
I , DRAIN CURRENT (A)
1
T = -55°C
J
25°C
125°C
0
1 1.5 2 2.5 3 3.5 4
V , GATE TO SOURCE VOLTAGE (V)
GS
Figure 5. Transfer Characteristics.
Figure 4. On-Resistance Variation
with Drain Current and Temperature.
1.2
1.1
1
0.9
th
V , NORMALIZED
0.8
0.7
GATE-SOURCE THRESHOLD VOLTAGE
0.6
-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)
J
V = V
DS GS
I = 250µA
D
Figure 6. Gate Threshold Variation
with Temperature.
NDS355AN Rev.C
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Typical Electrical Characteristics (continued)
DS
1.12
I = 250µA
D
1.08
1.04
1
DSS
BV , NORMALIZED
0.96
DRAIN-SOURCE BREAKDOWN VOLTAGE
0.92
-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)
J
Figure 7. Breakdown Voltage Variation with
Temperature.
500
300
200
100
60
CAPACITANCE (pF)
f = 1 MHz
40
V = 0V
GS
20
0.1 0.2 0.5 1 2 5 10 20 30
V , DRAIN TO SOURCE VOLTAGE (V)
C
C
C
iss
oss
rss
5
V = 0V
GS
1
0.1
0.01
0.001
S
I , REVERSE DRAIN CURRENT (A)
0.0001
0 0.2 0.4 0.6 0.8 1 1.2
V , BODY DIODE FORWARD VOLTAGE (V)
SD
T = 125°C
J
25°C
-55°C
Figure 8. Body Diode Forward Voltage Variation with
Source Current and Temperature.
10
I = 1.6A
D
8
6
4
2
GS
V , GATE-SOURCE VOLTAGE (V)
0
0 2 4 6 8
Q , GATE CHARGE (nC)
V = 5V
DS
10V
15V
g
Figure 9. Capacitance Characteristics.
V
DD
V
IN
R
D
V
GS
R
GEN
G
S
Figure 11. Switching Test Circuit.
L
DUT
V
OUT
Figure 10. Gate Charge Characteristics.
t t
on off
t
d(on)
r
t
d(off)
90%
V
OUT
V
IN
10%
50%
10%
PULSE WIDTH
Figure 12. Switching Waveforms.
50%
10%
90%
tt
90%
INVERTED
NDS355AN Rev.C
f
Page 6
Typical Electrical Characteristics (continued)
7
V = 5.0V
6
5
4
3
2
1
FS
g , TRANSCONDUCTANCE (SIEMENS)
0
DS
0 2 4 6 8 10
I , DRAIN CURRENT (A)
D
T = -55°C
J
25°C
125°C
Figure 13. Transconductance Variation with Drain
Current and Temperature.
1
0.8
0.6
1a
1b
0.4
0.2
STEADY-STATE POWER DISSIPATION (W)
0
0 0.1 0.2 0.3 0.4
2oz COPPER MOUNTING PAD AREA (in )
4.5"x5" FR-4 Board
o
T = 25 C
A
Still Air
2
30
10
5
3
RDS(ON) LIMIT
1
0.3
0.1
D
I , DRAIN CURRENT (A)
0.03
0.01
V = 4.5V
GS
SINGLE PULSE
R =See Note1b
JA
θ
T = 25°C
A
0.1 0.2 0.5 1 2 5 10 20 30 50
V , DRAI N-SOURCE VOLTAGE (V)
DS
1ms
10ms
100ms
1s
DC
Figure 14. Maximum Safe Operating Area.
2
1.8
1.6
1a
1b
1.4
D
I , STEADY-STATE DRAIN CURRENT (A)
1.2
0 0.1 0.2 0.3 0.4
2oz COPPER MOUNTING PAD AREA (in )
4.5"x5" FR-4 Board
o
T = 25 C
A
Still Air
V = 4.5V
GS
2
100us
Figue 15. SuperSOT
TM _
3 Maximum
Steady-State Power Dissipation versus Copper
Figure 16. Maximum Steady-State Drain
Current versus Copper Mounting Pad Area.
Mounting Pad Area.
1
D = 0.5
0.5
R (t) = r(t) * R
JA
0.2
0.2
0.1
0.1
0.05
0.05
0.02
0.02
0.01
0.01
0.005
r(t), NORMALIZED EFFECTIVE
0.002
TRANSIENT THERMAL RESISTANCE
0.001
0.0001 0.001 0.01 0.1 1 10 100 300
Single Pulse
t , TIME (sec)
1
θ
R = See Note 1b
θJA
P(pk)
t
1
t
2
T - T = P * R (t)
J
A
Duty Cycle, D = t /t
JA
θ
θ
JA
1
2
Figure 17. Transient Thermal Response Curve.
Note : Characterization performed using the conditions described in note 1b. Transient thermal response will
change depending on the circuit board design.
NDS355AN Rev.C
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TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
DenseTrench™
DOME™
EcoSPARK™
E2CMOS
EnSigna
TM
TM
FACT™
FACT Quiet Series™
STAR*POWER is used under license
FAST
FASTr™
FRFET™
GlobalOptoisolator™
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ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
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OPTOLOGIC™
OPTOPLANAR™
PACMAN™
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Power247™
PowerTrench
QFET™
QS™
QT Optoelectronics™
Quiet Series™
SILENT SWITCHER
SMART START™
STAR*POWER™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
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UHC™
UltraFET
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DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Formative or
In Design
First Production
Full Production
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H4
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