Datasheet NDC652P Datasheet (Fairchild Semiconductor)

March 1996

NDC652P P-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description Features

These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast high-side switching, and low in-line power loss are needed in a very small outline surface mount package.

____________________________________________________________________________________________

-2.4A, -30V. R R

= 0.18Ω @ VGS = -4.5V

DS(ON)

= 0.11Ω @ VGS = -10V.

DS(ON)

Proprietary SuperSOTTM-6 package design using copper lead frame for superior thermal and electrical capabilities.

High density cell design for extremely low R

DS(ON)

.

Exceptional on-resistance and maximum DC current capability.

4

5

6

3

2

1

Absolute Maximum Ratings T

Symbol Parameter NDC652P Units

V V I

D

P

TJ,T

THERMAL CHARACTERISTICS

R R

Drain-Source Voltage -30 V

DSS

Gate-Source Voltage - Continuous -20 V

GSS

Drain Current - Continuous -2.4 A

- Pulsed -10 Maximum Power Dissipation (Note 1a) 1.6 W

D

STG

JA

θ

JC

θ

(Note 1b)

(Note 1c)

Operating and Storage Temperature Range -55 to 150 °C

Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W Thermal Resistance, Junction-to-Case (Note 1) 30 °C/W

= 25°C unless otherwise noted

A

1

0.8

NDC652P Rev. D1

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS

BV I

DSS

I

GSSF

I

GSSR

DSS

Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -30 V Zero Gate Voltage Drain Current

Gate - Body Leakage, Forward Gate - Body Leakage, Reverse

VDS = -24 V, V

GS

= 0 V

VGS = 20 V, VDS = 0 V VGS = -20 V, VDS= 0 V

TJ = 55oC

1 µA

10 µA

100 nA

-100 nA

ON CHARACTERISTICS (Note 2)

V

R

GS(th)

DS(ON)

Gate Threshold Voltage

VDS = VGS, ID = -250 µA

TJ = 125oC

Static Drain-Source On-Resistance VGS = -4.5 V, ID = -2.4 A 0.16 0.18

TJ = 125oC

-1 -1.5 -3 V

-0.7 -1.2 -2.2

Ω

0.22 0.36

VGS = -10 V, ID = -3.1 A 0.09 0.11 I g

D(on)

On-State Drain Current

FS

Forward Transconductance VDS = -10 V, ID = -2.4 A 3 S

VGS = -4.5 V, VDS = -5 V

-5 A

DYNAMIC CHARACTERISTICS

C

iss

C

oss

C

rss

Input Capacitance Output Capacitance 180 pF

VDS = -15 V, V

f = 1.0 MHz

GS

= 0 V,

Reverse Transfer Capacitance 60 pF

290 pF

SWITCHING CHARACTERISTICS (Note 2)

t t t t Q Q Q

D(on)

r

D(off)

f

Turn - On Delay Time Turn - On Rise Time 26 35 ns

VDD = -15 V, ID = -1 A,

V

= -4.5 V, R

GEN

= 6 Ω

Turn - Off Delay Time 22 30 ns Turn - Off Fall Time 19 30 ns

g

gs

gd

Total Gate Charge Gate-Source Charge 1.5 nC Gate-Drain Charge 3.3 nC

VDS = -15 V,

ID = -2.4 A, VGS = -10 V

13 20 ns

10.5 20 nC

NDC652P Rev. D1

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units DRAIN-SOURCE DIODE CHARACTERISTICS

I

S

V

SD

Notes:

1. R design while R

P

Typical R

Scale 1 : 1 on letter size paper

Continuous Source Diode Current -1.3 A Drain-Source Diode Forward Voltage

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R

JA

θ

D

is determined by the user's board design.

CA

θ

T

(t)

=

R

using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:

JA

θ

a. 78oC/W when mounted on a 1 in2 pad of 2oz cpper. b. 125oC/W when mounted on a 0.01 in2 pad of 2oz cpper. c. 156oC/W when mounted on a 0.003 in2 pad of 2oz cpper.

θJ A

J−TA

T

=

(t)

R

θJ C+RθCA

J−TA

2

= I

(t) × R

DS(ON)T

D

(t)

J

1a

VGS = 0 V, IS = -1.3 A (Note 2)

1b

1c

-0.8 -1.2 V

is guaranteed by

JC

θ

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.

NDC652P Rev. D1

Typical Electrical Characteristics

-10

V = -10V

GS

-8

-6

-4

-2

D

I , DRAIN-SOURCE CURRENT (A)

0

-7.0

V , DRAIN-SOURCE VOLTAGE (V)

DS

-6.0

-5.5

-5.0

-4.5

-4.0

-3.5

-3.0

-2.5

-3-2.5-2-1.5-1-0.50

2.5

V = -3.0V

GS

2

1.5

DS(ON)

1

R , NORMALIZED

DRAIN-SOURCE ON-RESISTANCE

0.5

-3.5

I , DRAIN CURRENT (A)

D

Figure 1. On-Region Characteristics Figure 2. On-Resistance Variation

with Drain Current and Gate Voltage

1.6

I = -2.4A

D

1.4

V = -4.5V

GS

1.2

1

DS(ON)

R , NORMALIZED

0.8

DRAIN-SOURCE ON-RESISTANCE

0.6

-50 -25 0 25 50 75 100 125 150 T , JUNCTION TEMPERATURE (°C)

J

2.5

V = -4.5 V

GS

2

1.5

DS(on)

R , NORMALIZED

1

DRAIN-SOURCE ON-RESISTANCE

0.5

T = 125°C

J

I , DRAIN CURRENT (A)

D

-4.0

25°C

-4.5

-55°C

-5.0

-5.5

-6.0

-7.0

-10

-10-8-6-4-20

Figure 3. On-Resistance Variation

with Temperature

-10

V = - 10V

DS

-8

-6

-4

D

I , DRAIN CURRENT (A)

-2

0

V , GATE TO SOURCE VOLTAGE (V)

GS

T = -55°C

J

Figure 5. Transfer Characteristics

125°C

25°C

Figure 4. On-Resistance Variation

with Drain Current and Temperature

1.2

V = V

GS

1.1

1

0.9

0.8

th

V , NORMALIZED

0.7

GATE-SOURCE THRESHOLD VOLTAGE

-6-5-4-3-2-1

0.6

-50 -25 0 25 50 75 100 125 150 T , JUNCTION TEMPERATURE (°C)

J

DS

I = -250µA

D

Figure 6. Gate Threshold Variation

with Temperature

NDC652P Rev. D1

Typical Electrical Characteristics (continued)

1.1

I = -250µAD

1.08

1.06

1.04

1.02

1

DSS

0.98

BV , NORMALIZED

0.96

DRAIN-SOURCE BREAKDOWN VOLTAGE

0.94

-50 -25 0 25 50 75 100 125 150 T , JUNCTION TEMPERATURE (°C)

J

Figure 7. Breakdown Voltage Variation

with Temperature

1000

500

200

CAPACITANCE (pF)

f = 1 MHz

100

V = 0V

GS

50

0.1 0.2 0.5 1 2 5 10 30

-V , DRAIN TO SOURCE VOLTAGE (V)

DS

C

iss

oss

rss

10

5

V = 0V

GS

T = 125°C

1

0.1

0.01

S

-I , REVERSE DRAIN CURRENT (A)

0.001

0.2 0.4 0.6 0.8 1 1.2

J

-V , BODY DIODE FORWARD VOLTAGE (V)

SD

25°C

-55°C

Figure 8. Body Diode Forward Voltage Variation with

Source Current and Temperature

10

I = -2.4A

D

8

6

4

2

GS

-V , GATE-SOURCE VOLTAGE (V) 0

0 2 4 6 8 10 12

Q , GATE CHARGE (nC)

g

V = -5V

DS

-15V

-10V

Figure 9. Capacitance Characteristics Figure 10. Gate Charge Characteristics

t t

on off

t

r

t

d(off)

90%

10%

50%

PULSE WIDTH

Figure 12. Switching Waveforms

V

IN

V

GS

R

GEN

G

Figure 11. Switching Test Circuit

-V

D

DD

t

V

d(on)

OUT

R

L

V

OUT

DUT

V

S

IN

10%

50%

90%

10%

90%

t

f

INVERTED

NDC652P Rev. D1

Typical Electrical and ThermalCharacteristics (continued)

8

V = -10V

DS

T = -55°C

6

J

25°C

4

2

FS

g , TRANSCONDUCTANCE (SIEMENS)

0

I , DRAIN CURRENT (A)

D

125°C

Figure 13. Transconductance Variation with Drain

Current and Temperature

3

2.5

2

1b

1c

1.5

D

-I , STEADY-STATE DRAIN CURRENT (A) 1

0 0.2 0.4 0.6 0.8 1

2oz COPPER MOUNTING PAD AREA (in )

4.5"x5" FR-4 Board

o

T = 25 C

A

Still Air V = -4.5V

GS

2

-10-8-6-4-20

1a

2

1.5

1b

1

1c

0.5

STEADY-STATE POWER DISSIPATION (W)

0

0 0.2 0.4 0.6 0.8 1

2oz COPPER MOUNTING PAD AREA (in )

4.5"x5" FR-4 Board

o

T = 25 C

A

Still Air

2

Figure 14. SOT-6 Maximum Steady-State Power

Dissipation versus Copper Mounting Pad Area.

30

10

3

RDS(ON) LIMIT

1

0.3

0.1

D

-I , DRAIN CURRENT (A)

0.03

0.01

V = -4.5V

GS

SINGLE PULSE

R = See Note 1c

JA

θ

T = 25°C

A

0.1 0.2 0.5 1 2 5 10 30 50

-V , DRAIN-SOURCE VOLTAGE (V)

DS

DC

100us

1ms

10ms

100ms

1s

1a

Figure 15. Maximum Steady-State Drain Current

Figure 16. Maximum Safe Operating Area

versus Copper Mounting Pad Area.

1

D = 0.5

0.5

R (t) = r(t) * R

JA

0.2

0.1

0.05

0.02

r(t), NORMALIZED EFFECTIVE

0.01

TRANSIENT THERMAL RESISTANCE

0.005

0.2

0.1

0.05

0.02

0.01

Single Pulse

0.00001 0.0001 0.001 0.01 0.1 1 10 100 300

t , TIME (sec)

1

Figure 17. Transient Thermal Response Curve.

Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change

depending on the circuit board design.

θ

R = See Note 1c

JA

θ

P(pk)

t

1

t

2

T - T = P * R (t)

J

A

Duty Cycle, D = t / t

JA

θ

1

JA

θ

2

NDC652P Rev. D1

g

y

g

SuperSOTTM-6 Tape and Reel Data and Package Dimensions

SSOT-6 Packaging Configuration:

Fi

ure 1.0

SSOT-6 Packaging Information

Packaging Option Packaging type

Qty per Reel/Tube/Bag Reel Size Box Dimension (mm) Max qty per Box Weight per unit (gm) Weight per Reel (kg)

Note/Comments

Customize Label

Stan dard

(no fl ow c ode )

3,000 10,000 7" Dia

184x187x47 343x343x64

9,000 30,000

0.0158 0.0158

0.1440 0.4700

TNR

D87Z

TNR

13"

Antistatic Cover Tape

F63TNR Label

Packaging Description:

SSOT-6 parts are shipped in tape. The carrier tape is made from a dissipative (carbon filled) polycarbonate resin. The cover tape is a multilayer film (Heat Activated Adhesive in nature) primarily composed of polyester film, adhesive layer, sealant, and anti-static sprayed agent. These reeled parts in standard option are shipped with 3,000 uni ts p er 7 " or 17 7cm di amet er re el. The reels are dark blue in color and is made of polystyrene plastic (antistatic coated). Other option comes in 10,000 units per 13" or 330cm diam eter reel. T his a nd some othe r opti ons ar e described in the Packaging Information table.

These full reels are individually barcode labeled and placed inside a pizza box (illustrated in f igure 1.0) made of recyclable corrugated brown paper with a Fairchild logo printi ng. One pizza box contain s three r eels maximu m. And these pizza boxes are placed inside a barcode labeled shipping box which comes in different sizes

Embo ssed

Carrier Tape

depending on the number of parts shipped.

631

SSOT-6 Unit Orientation

343mm x 342mm x 64mm

Intermediate box for D87Z Option

631

631631

631

Pin 1

F63TNR Label

184mm x 187mm x 47mm

Pizza Box for Standard Option

SSOT-6 Tape Leader and Trailer Configuration:

Carrier Tape

Cover Tape

1998 Fairchild Semiconductor Corporation

ure 2.0

Fi

Tr ailer Tape 300mm mi nimum or 75 empt

F63TNR Label

pockets

Component s

F63TNR Label sampl e

LOT: CBVK7 41B019

FSID: FDC633N

D/C1: D9842 QTY1: SPEC REV: D/C2: QTY2: CPN:

QTY: 3000

SPEC:

N/F: F (F63TNR)3

Leader Tape 500mm mi nimum or 125 empt

pockets

August 1999, Rev. C

g

SuperSOTTM-6 Tape and Reel Data and Package Dimensions, continued

SSOT-6 Embossed Carrier Tape Configuration:

T

K0

Wc

Fi

B0

ure 3.0

P0

D0

E1

F

W

E2

Tc

A0

P1

D1

User Direction of Feed

Dimensions are in millimeter

Pkg type

SSOT-6

(8mm)

Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481

SSOT-6 Reel Configuration:

A0 B0 W D0 D1 E1 E2 F P1 P0 K0 T Wc Tc

3.23

3.18

8.0

1.55

1.125

1.75

6.25

+/-0.10

+/-0.3

+/-0.05

+/-0.125

+/-0.10

rotational and lateral movement requirements (see sketches A, B, and C).

B0

20 deg maximum component rotation

Sketch A (Side or Front Sectional View)

Component Rotation

Fi

ure 4.0

3.50

min

+/-0.05

20 deg maximum

A0

Sketch B (Top View)

Component Rotation

W1 Measured at Hub

4.0 +/-0.1

Typical component cavity center line

Typical component center line

Dim A

Max

4.0 +/-0.1

1.37

0.255 +/-0.150

5.2 +/-0.3

0.5mm maximum

+/-0.10

0.5mm maximum

Sketch C (Top View)

Component lateral movement

0.06 +/-0.02

Dim A

max

Dim N

Diameter Option

7"

See detail AA

B Min

Dim C

13" Diameter Option

See detail AA

W2 max Measured at Hub

W3

Dim D

min

DETAIL AA

Dimensions are in inches and millimeters

Tape Size

8mm 7" Dia

8mm 13" Dia

Reel

Option

Dim A Dim B Dim C Dim D Dim N Dim W1 Dim W2 Dim W3 (LSL-USL)

7.00

0.059

177.8

13.00 330

1.5

0.059

1.5

512 +0.020/-0.008 13 +0.5/-0.2

0.795

2.165550.331 +0.059/-0.000

20.2

0.795

4.00

20.2

100

8.4 +1.5/0

0.331 +0.059/-0.000

8.4 +1.5/0

0.567

14.4

0.567

14.4

0.311 – 0.429

7.9 – 10.9

0.311 – 0.429

7.9 – 10.9

July 1999, Rev. C

SuperSOTTM-6 Tape and Reel Data and Package Dimensions, continued

SuperSOT -6 (FS PKG Code 31, 33)

1:1

Scale 1:1 on letter size paper

Dimensions shown below are in:

inches [millimeters]

Part Weight per unit (gram): 0.0158

1998 Fairchild Semiconductor Corporation

September 1998, Rev. A

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The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.

ACEx™ CoolFET™ CROSSVOLT™

2

E

CMOS

TM

FACT™ FACT Quiet Series™

®

FAST FASTr™ GTO™ HiSeC™

ISOPLANAR™ MICROWIRE™ POP™ PowerTrench



QFET™ QS™

Quiet Series™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8

SyncFET™ TinyLogic™ UHC™ VCX™

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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICA TION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROV AL OF FAIRCHILD SEMICONDUCTOR CORPORA TION. As used herein:

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2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or

effectiveness.

PRODUCT STA TUS DEFINITIONS Definition of Terms

Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Obsolete

Formative or In Design

First Production

Full Production

Not In Production

This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.

Rev. D