Datasheet NCP561SN15T1, NCP561SN18T1, NCP561SN25T1, NCP561SN27T1, NCP561SN28T1 Datasheet (ON) [ru]

NCP561

150 mA CMOS Low Iq
Low-Dropout Voltage
Regulator

The NCP561 series of fixed output low dropout linear regulators are
designed for handheld communication equipment and portable battery
powered applications which require low quiescent. The NCP561
series features an ultralow quiescent current of 3.0 A. Each device
contains a voltage reference unit, an error amplifier, a PMOS power
transistor, resistors for setting output voltage, current limit, and
temperature limit protection circuits.

The NCP561 has been designed to be used with low cost ceramic
capacitors and requires a minimum output capacitor of 1.0 F. The
device is housed in the micro-miniature TSOP-5 surface mount
package. Standard voltage versions are 1.5 V, 1.8 V, 2.5 V, 2.7 V,

2.8 V, 3.0 V, 3.3 V and 5.0 V.

Features

•Low Quiescent Current of 3.0 A Typical

•Low Dropout Voltage of 170 mV at 150 mA

•Low Output Voltage Option

•Output Voltage Accuracy of 2.0%

•Industrial Temperature Range of -40°C to 85°C

•Pb-Free Packages are Available

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5

1

TSOP-5

SN SUFFIX

CASE 483

PIN CONNECTIONS AND

MARKING DIAGRAM

1

V

GND

Enable

IN

2

3

(Top View)

G

5

XXXAYWG

4

V

OUT

N/C

Typical Applications

•Battery Powered Instruments

•Hand-Held Instruments

•Camcorders and Cameras

V

IN

1

Thermal

Shutdown

Enable

3

ON

OFF

This device contains 28 active transistors

Figure 1. Representative Block Diagram

Driver w/

Current

Limit

GND

XXX = Specific Device Code
A = Assembly Location
Y = Year
W = Work Week
G = Pb-Free Package

(Note: Microdot may be in either location)

V

OUT

5

See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.

2

ORDERING INFORMATION

© Semiconductor Components Industries, LLC, 2007

August, 2007 - Rev. 5

1 Publication Order Number:

NCP561/D

NCP561

PIN FUNCTION DESCRIPTION

Pin No. Pin Name Description

1 V

IN

2 GND Power supply ground.

3 Enable This input is used to place the device into low-power standby. When this input is pulled low, the device is

4 N/C No internal connection.

5 V

OUT

MAXIMUM RATINGS

Input Voltage V

Enable Voltage Enable -0.3 to V

Output Voltage V

Power Dissipation and Thermal Characteristics

Power Dissipation
Thermal Resistance, Junction-to-Ambient

Operating Junction Temperature T

Operating Ambient Temperature T

Storage Temperature T

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.

1. This device series contains ESD protection and exceeds the following tests:

Human Body Model 2000 V per MIL-STD-883, Method 3015
Machine Model Method 200 V

2. Latchup capability (85°C) "100 mA DC with trigger voltage.

Positive power supply input voltage.

disabled. If this function is not used, Enable should be connected to V

.

IN

Regulated output voltage.

Rating Symbol Value Unit

6.0 V

+0.3 V

IN

-0.3 to V

+0.3 V

IN

Internally Limited

250

+150 °C

-40 to +85 °C

-55 to +150 °C

R

IN

OUT

P



A

stg

D

JA

J

W

°C/W

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2

NCP561

ELECTRICAL CHARACTERISTICS (V

IN

= V

OUT(nom)

+ 1.0 V, V

= VIN, CIN = 1.0 F, C

enable

= 1.0 F, TJ = 25°C,

OUT

unless otherwise noted.)

Characteristic

Output Voltage (TA = 25°C, I

= 1.0 mA)

OUT

1.5 V

1.8 V

2.5 V

2.7 V

2.8 V

3.0 V

3.3 V

5.0 V

Line Regulation

1.5 V-4.4 V (V

4.5 V-5.0 V (V

Load Regulation (I

Output Current (V

1.5 V to 3.9 V (V

4.0 V to 5.0 V (V

Dropout Voltage (TA = -40°C to 85°C, I

Measured at V

= V

IN

= 5.5 V to 6.0 V)

IN

OUT

OUT

IN

IN

OUT

+ 1.0 V to 6.0 V)

o(nom)

= 10 mA to 150 mA) Reg

= (V

= V

OUT

o(nom)

at I

= 150 mA) -3.0%)

out

+ 2.0 V)

= 6.0 V)

= 150 mA,

OUT

- 3.0%)

1.5 V - 1.7 V

1.8 V - 2.4 V

2.5 V - 2.7 V

2.8 V - 3.2 V

3.3 V - 4.9 V

5.0 V

Quiescent Current

(Enable Input = 0 V)
(Enable Input = VIN, I

= 1.0 mA to I

OUT

o(nom)

)

Output Short Circuit Current

1.5 V to 3.9 V (V

4.0 V to 5.0 V (V

= V

IN

= 6.0 V)

IN

o(nom)

+ 2.0 V)

Output Voltage Noise

(f = 20 Hz to 100 kHz, V

OUT

= 3.0, V I

OUT

= 1.0 V)

Enable Input Threshold Voltage

(Voltage Increasing, Output Turns On, Logic High)
(Voltage Decreasing, Output Turns Off, Logic Low)

Output Voltage Temperature Coefficient T

Symbol Min Typ Max Unit

V

OUT

Reg

load

I

o(nom)

VIN-V

I

Q

I

OUT(max)

V

n

V

th(en)

C

line

OUT

1.455

1.746

2.425

2.646

2.744

2.940

3.234

4.90

-

-

1.5

1.8

2.5

2.7

2.8

3.0

3.3

5.0

10
10

1.545

1.854

2.575

2.754

2.856

3.060

3.366

5.10

20
20

- 30 60 mV

150
150

-

-

-

-

-

-

-

-

160
160

-

-

330
240
150
140
130
120

0.1

4.0

400
400

-

-

500
360
250
230
200
190

1.0

8.0

800
800

- 60 -

1.3

-

-

-

-

0.2

- "100 - ppm/°C

3. Maximum package power dissipation limits must be observed.

T

J(max)*TA

PD +

R

JA

4. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.

V

mV

mA

mV

A

mA

Vrms

V

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3

NCP561

0

k

TYPICAL CHARACTERISTICS

180

V

= 3.0 V

OUT

160

140

120

150 mA Load

100

80

60

, DROPOUT VOLTAGE (mV)

40

OUT

20

- V

IN

V

0

-50 -25 0 25 50 75 100 125

100 mA Load

50 mA Load

TEMPERATURE (C°)

Figure 2. Dropout Voltage vs. Temperature

4.75

I

= 10 mA

OUT

4.50

V

= 4.0 V

IN

4.25

4.00

3.75

3.50

3.015
I

= 10 mA

3.010

3.005

OUT

VIN = 6.0 V

3.000

VIN = 4.0 V

2.995

2.990

, OUTPUT VOLTAGE (V)

2.985

OUT

V

2.980

2.975

-50 0 50 10

TEMPERATURE (C°)

Figure 3. Output Voltages vs. Temperature

4.5

V

= 3.0 V

4.0

3.5

3.0

2.5

OUT

I

OUT

= 25°C

T

A

= 0 mA

, QUIESCENT CURRENT (A)

3.25

q

I

3.00

-50 0 50

100

2.0

, QUIESCENT CURRENT (A)

q

I

1.5
05

1234 6

TEMPERATURE (C°)

Figure 4. Quiescent Current vs. Temperature

5.0
V

= 3.0 V

OUT

4.5

I

= 50 mA

OUT

= 25°C

T

A

Figure 5. Quiescent Current vs. Input Voltage

4.0

3.5

3.0

4.0

2.5

3.5

3.0

2.5

, GROUND PIN CURRENT (A)

2.0

GND

I

1.5

05

1234 6

2.0

1.5

1.0

0.5

OUTPUT NOISE VOLTAGE (V/ǰHz)

0

10 100 1 k 10 k 100 k 1000

VIN, INPUT VOLTAGE (V)

Figure 6. Ground Current vs. Input Voltage

Figure 7. Output Noise Voltage

TEMPERATURE (C°)

1.0 mA

150 mA

NOISE CHARACTERIZATION

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4

60

0

0

50

, INPUT

IN

40

V

VOLTAGE (mV)

400

200

0

-200

VOLTAGE (mV)

CHANGE IN OUTPUT

-400
0 0.2 0.4 0.8 1.0 1.2 1.4

NCP561

TYPICAL CHARACTERISTICS

I

= 10 mA

OUT

C

= 1.0 F

OUT

0.6 1.6 1.8 2.0
TIME (s)

0

-50

-100

-150

VOLTAGE (mV)

-200

CHANGE IN OUTPUT

-250

150

100

, OUTPUT

50

OUT

0

I

CURRENT (mA)

0 200 400 600 800 1000 120

VIN = 4.0 V
V

= 3.0 V

OUT

C

= 1.0 F

IN

C

= 10 F

OUT

Al. Elec. Surface Mount

TIME (s)

Figure 8. Line Transient Response

0

-50

-100

-150

VOLTAGE (mV)

-200

CHANGE IN OUTPUT

-250

150

100

, OUTPUT

50

OUT

0

I

CURRENT (mA)

0 200 400 600 800 1000

Figure 10. Load Transient Response

TIME (s)

3.5

3.0

2.5

2.0

1.5

VIN = 4.0 V
V

= 3.0 V

OUT

C

= 1.0 F

IN

C

= 10 F

OUT

Tantalum

1200

4

2

ENABLE

0

VOLTAGE (V)

3

2

, OUTPUT

1

OUT

VOLTAGE (V)

V

0

CIN = 1.0 F
C

OUT

= 25°C

T

A

V

ENABLE

Figure 9. Load Transient Response

CIN = 1.0 F
C
I

0 200 400 600 800 1000

TIME (s)

Figure 11. Turn-On Response

= 1.0 F

= V

IN

OUT

OUT

= 1.0 F

= 10 mA

1200

1400 160

1.0

, OUTPUT VOLTAGE (V)

OUT

V

0.5

0

012 3

VIN, INPUT VOLTAGE (V)

Figure 12. Output Voltage vs. Input Voltage

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456

5

NCP561

DEFINITIONS

Load Regulation

The change in output voltage for a change in output

current at a constant temperature.

Dropout Voltage

The input/output differential at which the regulator output
no longer maintains regulation against further reductions in
input voltage. Measured when the output drops 3.0% below
its nominal. The junction temperature, load current, and
minimum input supply requirements affect the dropout level.

Maximum Power Dissipation

The maximum total dissipation for which the regulator
will operate within its specifications.

Quiescent Current

The quiescent current is the current which flows through
the ground when the LDO operates without a load on its
output: internal IC operation, bias, etc. When the LDO
becomes loaded, this term is called the Ground current. It is
actually the difference between the input current (measured
through the LDO input pin) and the output current.

Line Regulation

The change in output voltage for a change in input voltage.
The measurement is made under conditions of low
dissipation or by using pulse technique such that the average
chip temperature is not significantly affected.

Line Transient Response

Typical over and undershoot response when input voltage
is excited with a given slope.

Thermal Protection

Internal thermal shutdown circuitry is provided to protect
the integrated circuit in the event that the maximum junction
temperature is exceeded. When activated at typically 160°C,
the regulator turns off. This feature is provided to prevent
failures from accidental overheating.

Maximum Package Power Dissipation

The maximum power package dissipation is the power
dissipation level at which the junction temperature reaches
its maximum operating value, i.e. 125°C. Depending on the
ambient power dissipation and thus the maximum available
output current.

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6

NCP561

APPLICATIONS INFORMATION

A typical application circuit for the NCP561 series is

shown in Figure 13.

Input Decoupling (C1)

A 1.0 F capacitor either ceramic or tantalum is

recommended and should be connected close to the NCP561
package. Higher values and lower ESR will improve the
overall line transient response.
TDK capacitor: C2012X5R1C105K, or C1608X5R1A105K

Output Decoupling (C2)

The NCP561 is a stable Regulator and does not require
any specific Equivalent Series Resistance (ESR) or a
minimum output current. Capacitors exhibiting ESRs
ranging from a few m up to 3.0  can thus safely be used.
The minimum decoupling value is 1.0 F and can be
augmented to fulfill stringent load transient requirements.
The regulator accepts ceramic chip capacitors as well as
tantalum devices. Larger values improve noise rejection and
load regulation transient response.
TDK capacitor: C2012X5R1C105K, or C1608X5R1A105K,
or C3216X7R1C105K

Enable Operation

The enable pin will turn on the regulator when pulled high
and turn off the regulator when pulled low. These limits of
threshold are covered in the electrical specification section
of this data sheet. If the enable is not used then the pin should
be connected to V

Hints

IN

.

Please be sure the VIN and GND lines are sufficiently
wide. When the impedance of these lines is high, there is a
chance to pick up noise or cause the regulator to
malfunction.

Set external components, especially the output capacitor,
as close as possible to the circuit, and make leads a short as
possible.

Thermal

As power across the NCP561 increases, it might become
necessary to provide some thermal relief. The maximum
power dissipation supported by the device is dependent
upon board design and layout. Mounting pad configuration
on the PCB, the board material and also the ambient
temperature effect the rate of temperature rise for the part.
This is stating that when the NCP561 has good thermal
conductivity through the PCB, the junction temperature will
be relatively low with high power dissipation applications.

The maximum dissipation the package can handle is
given by:

T

PD +

J(max)*TA

R

JA

If junction temperature is not allowed above the
maximum 125°C, then the NCP561 can dissipate up to
400 mW @ 25°C.

The power dissipated by the NCP561 can be calculated
from the following equation:

P

tot

+[Vin*I

gnd

(I

)])[Vin* V

out

out

]

*I

out

or

V

INMAX

+

P

TOT

)

I

GND

V

OUT

) I

*

OUT

I

OUT

If a 150 mA output current is needed then the ground
current from the data sheet is 4.0 A. For an
NCP561SN30T1 (3.0 V), the maximum input voltage will
then be 5.6 V.

Battery or

Unregulated

Voltage

ON

OFF

+

C1

Figure 13. Typical Application Circuit

1

2

3

5

4

V

OUT

+

C2

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7

NCP561

APPLICATION CIRCUITS

Input

R

Q1

Output

1

1.0 F 1.0 F
2

3

5

4

Figure 14. Current Boost Regulator Figure 15. Current Boost Regulator

The NCP561 series can be current boosted with a PNP transist‐
or. Resistor R in conjunction with V
when the pass transistor begins conducting; this circuit is not
short circuit proof. Input/Output differential voltage minimum is
increased by V

of the pass resistor.

BE

Input

1.0 F

Enable

1.0 F 1.0 F

R

C

of the PNP determines

BE

1

2

3

1

2

3

Output

5

1.0 F

4

Output

5

4

Input

R1

Q1

R2

Q2

R3

1

1.0 F 1.0 F
2

3

with Short Circuit Limit

Short circuit current limit is essentially set by the V
R1. I

Input

R

SC

5.6 V

= ((V

- ib * R2) / R1) + I

BEQ2

Q1

1.0 F

O(max) Regulator

1

2

3

5

4

of Q2 and

BE

5

4

Output

Output

1.0 F

Figure 16. Delayed Turn-on Figure 17. Input Voltages Greater than 6.0 V

If a delayed turn-on is needed during power up of several
voltages then the above schematic can be used. Resistor R,
and capacitor C, will delay the turn-on of the bottom regulator.

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A regulated output can be achieved with input voltages that
exceed the 6.0 V maximum rating of the NCP561 series with
the addition of a simple pre-regulator circuit. Care must be
taken to prevent Q1 from overheating when the regulated
output (V

) is shorted to GND.

OUT

8

NCP561

ORDERING INFORMATION

Nominal

Device

NCP561SN15T1 1.5 LDA TSOP-5

NCP561SN15T1G 1.5

NCP561SN18T1 1.8 LEV TSOP-5

NCP561SN18T1G 1.8 LEV TSOP-5

NCP561SN25T1 2.5 LDC TSOP-5

NCP561SN25T1G 2.5 LDC TSOP-5

NCP561SN27T1 2.7 LEX TSOP-5

NCP561SN27T1G 2.7 LEX TSOP-5

NCP561SN28T1 2.8 LDD TSOP-5

NCP561SN28T1G 2.8 LDD TSOP-5

NCP561SN30T1 3.0 LDE TSOP-5

NCP561SN30T1G 3.0 LDE TSOP-5

NCP561SN33T1 3.3 LDF TSOP-5

NCP561SN33T1G 3.3 LDF TSOP-5

NCP561SN50T1 5.0 LDH TSOP-5

NCP561SN50T1G 5.0 LDH

NOTE: Additional voltages are available upon request by contacting your ON Semiconductor representative.
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

Output Voltage

Marking Package Shipping

LDA

TSOP-5

(Pb-Free)

(Pb-Free)

(Pb-Free)

(Pb-Free)

3000 / 7″ Tape & Reel

(Pb-Free)

(Pb-Free)

(Pb-Free)

TSOP-5

(Pb-Free)

†

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9

NCP561

PACKAGE DIMENSIONS

TSOP-5

(SOT23-5, SC59-5)

SN SUFFIX

CASE 483-02

ISSUE H

NOTES:

1. DIMENSIONING AND TOLERANCING PER

NOTE 5

2X

2X

T0.10

T0.20

54

123

L

G

D

0.205XC AB

M

S

B

K

DETAIL Z

A

J

DETAIL Z

C

0.05

H

SEATING
PLANE

T

SOLDERING FOOTPRINT*

1.9

0.95

0.037

0.074

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.

4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.

5. OPTIONAL CONSTRUCTION: AN
ADDITIONAL TRIMMED LEAD IS ALLOWED
IN THIS LOCATION. TRIMMED LEAD NOT TO
EXTEND MORE THAN 0.2 FROM BODY.

MILLIMETERS

DIM MIN MAX

A 3.00 BSC
B 1.50 BSC
C 0.90 1.10
D 0.25 0.50
G 0.95 BSC
H 0.01 0.10
J 0.10 0.26
K 0.20 0.60
L 1.25 1.55

M 0 10

__

S 2.50 3.00

2.4

0.094

1.0

0.039

0.7

0.028

SCALE 10:1

ǒ

inches

mm

Ǔ

*For additional information on our Pb-Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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NCP561/D

10