Datasheet NCP5392P Datasheet (ON Semiconductor)

NCP5392P

2/3/4--Phase Controller for
CPU Applications

The NCP5392P provides up to a four--phase buck solution which
combines differential voltage sensing, differential phase current
sensing, and adaptive voltage positioning to provide accurately
regulated power for both Intel and AMD processors. Dual--edge
pulse--width modulation (PWM) combined with inductor current
sensing reduces system cost by providing the fastest initial response
to dynamic load events. Dual--edge multiphase modulation reduces
the total bul k and ceramic output capacitance required to meet
transient regulation specifications.

A high performance operational error amplifier is provided to
simplify compensation of the system. Dynamic Reference Injection
further simplifies loop compensation by eliminating the need to
compromise bet we en closed--loop transient response and Dynamic
VID performance.

In addition, NCP5392P provides an automatic power saving
feature (Auto--PSI). When Auto--PSI function is enabled, NCP5392P
will automatically detect the VID transitions and direct the Vcore
regulator in or out of low power states. As a result, the best efficiency
scheme is always chosen.

Features

 Meets Intel’s VR11.1 Specifications
 Meets AMD 6 Bit Code Specifications
 Dual--edge PWM for Fastest Initial Response to Transient Loading
 High Performance Operational Error Amplifier
 Internal Soft Start
 Dynamic Reference Injection
 DAC Range from 0.375 V to 1.6 V
 DAC Feed Forward Function
 0.5% DAC Voltage Accurac y from 1.0 V to 1.6 V
 True Differential Remote Voltage Sensing Amplifier
 Phase--to--Phase Current Balancing
 “Lossless” Differential Inductor Current Sensing
 Differential Current Sense Amplifiers for each Phase
 Adaptive Voltage Positioning (AVP)
 Oscillator Frequency Range of 100 kHz – 1 MHz
 Latched Over Voltage Protection (OVP)
 Guaranteed Startup into Pre-- Charged Loads
 Threshold Sensitive Enable Pin for VTT Sensing
 Power Good Output with Internal Delays
 Thermally Compensated Current Monitoring
 Automatic Power Saving (AUTO PSI Mode)
 Compatible to PSI Power Saving Requirements
 This is a Pb--Free Device

Applications

 Desktop Processors

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MARKING
DIAGRAM

1

401

40 PIN QFN, 6x6

MN SUFFIX

CASE 488AR

NCP5392P = Specific Device
Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb-- Free Package

*Pin 41 is the thermal pad on the bottomof thedevice.

ORDERING INFORMATION

Device Package Shipping

NCP5392PMNR2G* QFN--40

(Pb--Free)

*Temperature Range: 0Cto85C
†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.

NCP5392P

AWLYYWWG

†

2500/Tape & Reel

 Semiconductor Components Industries, LLC, 2010

November, 2010 -- Rev. 2

1 Publication Order Number:

NCP5392P/D

NCP5392P

PIN CONNECTIONS

40

39

38

37

36

35

34G433G332G231

PSI

DAC

1

EN

2

VID0

3

VID1

4

VID2

5

VID3

6

VID4

7

VID5

8

VID6

9

VID7

10

ROSC

PH_PSI

VR_RDY

APSI_EN

2/3/4--Phase Buck Controller

ILIM11IMON12VSP13VSN14DIFFOUT15COMP16VFB17VDRP18VDFB19CSSUM

VCC

12VMON

DRVON

NCP5392P

(QFN40)

20

Figure 1. NCP5392P QFN40 Pin Connections (Top View)

CS4

CS4N

CS3

CS3N

CS2

CS2N

CS1

CS1N

30

G1

29

28

27

26

25

24

23

22

21

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2

VID0
VID1

VID2
VID3
VID4

VID5
VID6

VID7/AMD

DAC

NCP5392P

Flexible DAC

Overvoltage
Protection

--

+

VSN

VSP

DIFFOUT

VFB

COMP

VDRP

VDFB

CSSUM

CS1P

CS1N

CS2P

CS2N

CS3P

CS3N

CS4P

CS4N

ROSC

ILIM

EN

VCC

+

1.3 V

+

--

+

--

+

--

+

--

+

--

Oscillator

--

+

Diff Amp

+

--

Droop Amp

-- 2 / 3

Gain = 6

Gain = 6

Gain = 6

Gain = 6

Error Amp

+

+

4.25 V

+

+

+

+

--

UVLO

+

--

+

--

+

--

+

+

+

--

+

-­ILimit

Control,

Fault Logic

and
Monitor
Circuits

G1

G2

G3

G4

IMON

DRVON

PSI

APSI_EN
PH_PSI

12VMON

VR_RDY

GND (FLAG)

Figure 2. NCP5392P Block Diagram

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3

NCP5392P

VTT

RFB

CFB1

CF

RDRP

RISO1 RISO2RT2

RFB1

RF

CH

RNOR

CDFB

12V_FILTER

2

3

4

5

6

7

8

9

1

39

14

13

15

16

17

18

19

R6R6

20

36

CDNI

RDNP

+5V

3534

VID0

VID1

VID2

VID3

VID4

VID5

VID6

VID7

EN

VR_RDY

VSN

VSP

DIFFOUT

COMP

VFB

VDRP

VDFB

CSSUM

DAC

41 11 10

12VMON

NCP5392P

GND

VCC

APSI_EN

ILIM

PH_PSI

IMON

CS1P

CS1N

CS2P

CS2N

CS3P

CS3N

CS4P

CS4N

DRVON

G1

G2

G3

G4

ROSC

37
38

40

12

30

22

21

31

24

23

32

26

25

33

28

27

29

RLIM1

RLIM2

VTTU2+5V

IMON

PSIPSI
APSI_EN

PH_PSI

12V_FILTER12V_FILTER

D1

C4

C3

C1

VCC

NCP5359

OD

IN

VCC

NCP5359

OD

IN

VCC

NCP5359

OD

IN

BST

DRH

SW

DRL

PGND

BST

DRH

SW

DRL

PGND

BST

DRH

SW

DRL

PGND

12V_FILTER12V_FILTER

12V_FILTER12V_FILTER

Q1

Q2 R2 RS1

C2

L1

CS1

+

CPU GND

VCCP

VSSN

BST

VCC

DRH

NCP5359

SW

OD

DRL

IN

PGND

Figure 3. Application Schematic for Four Phases

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4

12V_FILTER12V_FILTER

NCP5392P

VTT

RFB

CFB1

CF

RDRP

RISO1 RISO2RT2

RFB1

RF

CH

RNOR

CDFB

12V_FILTER

2

3

4

5

6

7

8

9

1

39

14

13

15

16

17

18

19

R6R6

20

36

CDNI

RDNP

+5V

3534

VID0

VID1

VID2

VID3

VID4

VID5

VID6

VID7

EN

VR_RDY

VSN

VSP

DIFFOUT

COMP

VFB

VDRP

VDFB

CSSUM

DAC

41 11 10

12VMON

NCP5392

GND

VCC

APSI_EN

ILIM

PH_PSI

IMON

CS1P

CS1N

CS2P

CS2N

CS3P

CS3N

CS4P

CS4N

DRVON

G1

G2

G3

G4

ROSC

37

38

40

12

30

22

21

31

24

23

32

26

25

33

28

27

29

RLIM1

RLIM2

VTTU2+5V

IMON

PSIPSI

APSI_EN

PH_PSI

12V_FILTER12V_FILTER

D1

C4

C3

C1

VCC

NCP5359

OD

IN

VCC

NCP5359

OD

IN

VCC

NCP5359

OD

IN

BST

DRH

SW

DRL

PGND

BST

DRH

SW

DRL

PGND

BST

DRH

SW

DRL

PGND

Q1

L1

Q2

12V_FILTER12V_FILTER

12V_FILTER12V_FILTER

RS1R2

C2

CS1

+

CPU GND

VCCP

VSSN

Figure 4. Application Schematic for Three Phases

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5

NCP5392P

VTT

RFB

CFB1

CF

RDRP

RISO1 RISO2RT2

RFB1

RF

CH

RNOR

CDFB

12V_FILTER

2

3

4

5

6

7

8

9

1

39

14

13

15

16

17

18

19

R6R6

20

36

CDNI

RDNP

+5V

3534

VID0

VID1

VID2

VID3

VID4

VID5

VID6

VID7

EN

VR_RDY

VSN

VSP

DIFFOUT

COMP

VFB

VDRP

VDFB

CSSUM

DAC

41 11 10

12VMON

NCP5392

GND

VCC

APSI_EN

ILIM

PH_PSI

IMON

CS1P

CS1N

CS2P

CS2N

CS3P

CS3N

CS4P

CS4N

DRVON

G1

G2

G3

G4

ROSC

37

38

40

12

30

22

21

31

24

23

32

26

25

33

28

27

29

RLIM1

RLIM2

VTTU2+5V

IMON

RNTC1

PSIPSI

APSI_EN

PH_PSI

12V_FILTER12V_FILTER

D1

C4

C3

C1

VCC

NCP5359

OD

IN

VCC

NCP5359

OD

IN

BST

DRH

SW

DRL

PGND

BST

DRH

SW

DRL

PGND

Q1

L1

Q2

12V_FILTER12V_FILTER

RS1R2

C2

CS1

+

CPU GND

VCCP

VSSN

Figure 5. Application Schematic for Two Phases

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6

NCP5392P

PIN DESCRIPTIONS

Pin No. Symbol Description

1 EN Threshold sensitive input. High = startup, Low = shutdown.

2 VID0 Voltage ID DAC input

3 VID1 Voltage ID DAC input

4 VID2 Voltage ID DAC input

5 VID3 Voltage ID DAC input

6 VID4 Voltage ID DAC input

7 VID5 Voltage ID DAC input

8 VID6 Voltage ID DAC input

9 VID7/AMD Voltage ID DAC input. Pull to VCC(5 V) to enable AMD 6--bit DAC code.

10 ROSC A resistance from this pin to ground programs the oscillator frequency according to fSW. This pin supplies a

11 ILIM Overcurrent shutdown threshold setting. Connect this pin to the ROSC pin via a resistor divider as shown in

12 IMON 0 mV to 900 mV analog signal proportional to the output load current. VSN referenced

13 VSP Non--inverting input to the internal differential remote sense amplifier

14 VSN Inverting input to the internal differential remote sense amplifier

15 DIFFOUT Output of the differential remote sense amplifier

16 COMP Output of the error amplifier

17 VFB Compensation Amplifier Voltage feedback

18 VDRP Voltage output signal proportional to current used for current limit and output voltage droop

19 VDFB Droop Amplifier Voltage Feedback

20 CSSUM Inverted Sum of the Differential Current Sense inputs. Av=CSSUM/CSx = --4

21 CS1N Inverting input to current sense amplifier #1

22 CS1 Non-- inverting input to current sense amplifier #1

23 CS2N Inverting input to current sense amplifier #2

24 CS2 Non-- inverting input to current sense amplifier #2

25 CS3N Inverting input to current sense amplifier #3

26 CS3 Non-- inverting input to current sense amplifier #3

27 CS4N Inverting input to current sense amplifier #4

28 CS4 Non-- inverting input to current sense amplifier #4

29 DRVON Bidirectional Gate Drive Enable

30 G1 PWM output pulse to gate driver. 3-- level output: Low = LSFET Enabled, Mid = Diode Emulation Enabled,

31 G2 PWM output pulse to gate driver. 3-- level output (see G1)

32 G3 PWM output pulse to gate driver. 3-- level output (see G1)

33 G4 PWM output pulse to gate driver. 3-- level output (see G1)

34 12VMON Monitor a 12 V input through a resistor divider.

35 VCC Power for the internal control circuits.

36 DAC DAC Feed Forward Output

37 PSI Power Saving Control. Low = power saving operation, High = normal operation. PSI signal has higher priority

38 APSI_EN APSI_EN High: Enable AUTO PSI function. When PSI = low, system will be forced into PSI mode, uncondi-

39 VR_RDY Open collector output. High indicates that the output is regulating

40 PH_PSI PH_PSI Pin select one or two phase operation in PSI mode. PH_PSI = low, two phase operation, PH_PSI =

FLAG GND Power supply return (QFN Flag)

trimmed output voltage of 2 V.

the Application Schematics. To disable the overcurrent feature, connect this pin directly to the ROSC pin. T o
guarantee correct operation, this pin should only be connected to the voltage generated by the ROSC pin; do
not connect this pin to any externally generated voltages.

High = HSFET Enabled

over APSI_EN signal.

tionally. When PSI = high, APSI_EN will determine if the system needs to be in AUTO PSI mode. Once in
AUTO PSI mode, system switches on/off PSI functions automatically based on VID change status.

high, one phase operation.

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7

NCP5392P

PIN CONNECTIONS VS. PHASE COUNT

Number of Phases G4 G3 G2 G1 CS4--CS4N CS3--CS3N CS2--CS2N CS1--CS1N

4 Phase 4

Out

3 Tie to

GND

2 Tie to

GND

MAXIMUM RATINGS

ELECTRICAL INFORMATION

Pin Symbol

COMP 5.5 V -- 0 . 3 V 10 mA 10 mA

V

DRP

V– GND + 300 mV GND – 300 mV 1mA 1mA

DIFFOUT 5.5 V -- 0 . 3 V 20 mA 20 mA

VR_RDY 5.5 V -- 0 . 3 V N/A 20 mA

VCC 7.0 V -- 0 . 3 V N/A 10 mA

ROSC 5.5 V -- 0 . 3 V 1mA N/A

IMON Output 1.1 V

All Other Pins 5.5 V -- 0 . 3 V

*All signals referenced to AGND unless otherwise noted.

Phase 3

Out

Phase 3

Out

Phase 2

Out

Phase 2

Out

Phase 2

Out

Tie to

GND

V

MAX

Phase 1

Out

Phase 1

Out

Phase 1

Out

Phase 4 CS

input

TietoCSN

pin used

TietoCSN

pin used

V

MIN

Phase 3 CS

input

Phase 3 CS

input

Phase 2 CS

input

I

SOURCE

Phase 2 CS

input

Phase 2 CS

input

TietoCSN

pin used

Phase 1 CS

Phase 1 CS

Phase 1 CS

I

SINK

5.5 V -- 0 . 3 V 5mA 5mA

input

input

input

THERMAL INFORMATION

Rating

Thermal Characteristic, QFN Package (Note 1) R

Operating Junction Temperature Range (Note 2) T

Operating Ambient Temperature Range T

Maximum Storage T emperature Range T

Symbol Value Unit

θ

JA

J

A

STG

34 C/W

0to125 C

0to+85 C

--55 to +150 C

Moisture Sensitivity Level, QFN Package MSL 1

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
*The maximum package power dissipation must be observed.

1. JESD 51--5 (1S2P Direct-- Attach Method) with 0 LFM.

2. JESD 51--7 (1S2P Direct-- Attach Method) with 0 LFM.

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8

NCP5392P

ELECTRICAL CHARACTERISTICS

(Unless otherwise stated: 0C<TA<85C; 4.75 V < VCC< 5.25 V; All DAC Codes; C

Parameter

Test Conditions Min Typ Max Unit

ERROR AMPLIFIER

Input Bias Current (Note 3)

Noninverting Voltage Range (Note 3) 0 1.3 3 V

Input Offset Voltage (Note 3) V+=V-- =1.1V -- 1 . 0 -- 1.0 mV

Open Loop DC Gain CL=60pFtoGND,

R

=10KΩ to GND

L

Open Loop Unity Gain Bandwidth CL=60pFtoGND,

R

=10KΩ to GND

L

Open Loop Phase Margin CL=60pFtoGND,

R

=10KΩ to GND

L

Slew Rate ΔVin= 100 mV, G = -- 10 V/V,

ΔV

=1.5V–2.5V,

out

C

=60pFtoGND,

L

DC Load = 125 mAtoGND

Maximum Output Voltage I

Minimum Output Voltage I

Output source current (Note 3) V

Output sink current (Note 3) V

=2.0mA 3.5 -- -- V

SOURCE

=0.2mA -- -- 50 mV

SINK

=3.5V 2 -- -- mA

out

=1.0V 2 -- -- mA

out

DIFFERENTIAL SUMMING AMPLIFIER

VSN Input Bias Current

VSN Voltage = 0 V 30 mA

VSP Input Resistance DRVON = Low

DRVON = High

VSP Input Bias Voltage DRVON = Low

DRVON = High

Input Voltage Range (Note 3) -- 0 . 3 -- 3.0 V

--3 dB Bandwidth CL=80pFtoGND,
R

=10KΩ to GND

L

Closed Loop DC Gain VS to Diffout VS+ to VS-- = 0.5 to 1.6 V 0.98 1.0 1.025 V/V

Maximum Output Voltage I

Minimum Output Voltage I

Output source current (Note 3) V

Output sink current (Note 3) V

=2mA 3.0 -- -- V

SOURCE

=2mA -- -- 0.5 V

SINK

=3V 2.0 -- -- mA

out

=0.5V 2.0 -- -- mA

out

INTERNAL OFFSET VOLTAGE

Offset Voltage to the (+) Pin of the
Error Amp and the VDRP pin

VDROOP AMPLIFIER

Input Bias Current (Note 3)

Non--inverting Voltage Range (Note 3) 0 1.3 3 V

Input Offset Voltage (Note 3) V+=V-- =1.1V -- 4 . 0 -- 4.0 mV

Open Loop DC Gain CL= 20 pF to GND including

ESD, R

=1kΩ to GND

L

Open Loop Unity Gain Bandwidth CL= 20 pF to GND including

ESD, R

=1kΩ to GND

L

Slew Rate CL= 20 pF to GND including

ESD, R

Maximum Output Voltage I

Minimum Output Voltage I

Output source current (Note 3) V

Output sink current (Note 3) V

=1kΩ to GND

L

=4.0mA 3 -- -- V

SOURCE

=1.0mA -- -- 1 V

SINK

=3.0V 4 -- -- mA

out

=1.0V 1 -- -- mA

out

3. Guaranteed by design, not tested in production.

=0.1mF)

VCC

--200 200 nA

-- 100 dB

-- 10 -- MHz

-- 80 -- 

-- 5 -- V/ms

1.5

kΩ

17

0.09

0.66

-- 10 -- MHz

-- 1.30 -- V

--200 200 nA

-- 100 dB

-- 10 -- MHz

-- 5 -- V/ms

V

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9

NCP5392P

ELECTRICAL CHARACTERISTICS

(Unless otherwise stated: 0C<TA<85C; 4.75 V < VCC< 5.25 V; All DAC Codes; C

Parameter UnitMaxTypMinTest Conditions

CSSUM AMPLIFIER

Current Sense Input to CSSUM Gain

Current Sense Input to CSSUM --3 dB
Bandwidth

Current Sense Input to CSSUM
Output Slew Rate

Current Summing Amp Output Offset

--60 mV < CS < 60 mV -- 4.00 --3.88 --3.76 V/V

CL=10pFtoGND,
R

=10kΩ to GND

L

ΔVin=25mV,CL=10pFto
GND, Load = 1 k to 1.3 V

CSx – CSNx = 0, CSx = 1.1 V -- 1 5 -- +15 mV

Voltage

Maximum CSSUM Output Voltage CSx – CSxN = --0.15 V

(All Phases) I

SOURCE

=1mA

Minimum CSSUM Output Voltage CSx – CSxN = 0.066 V

Output source current (Note 3) V

Output sink current (Note 3) V

(All Phases) I

=3.0V 1 -- -- mA

out

=0.3V 1 -- -- mA

out

SINK

=1mA

PSI (Power Saving Control, Active Low)

Enable High Input Leakage Current

Upper Threshold V

Lower Threshold V

Hysteresis V

External1KPullupto3.3V -- -- 1.0 mA

UPPER

LOWER

-- V

UPPER

LOWER

APSI_EN (AUTO PSI Function Enable, Active High)

Enable High Input Leakage Current

Upper Threshold V

Lower Threshold V

Hysteresis V

External 1k Pullup to 3.3 V -- -- 1.0 mA

UPPER

LOWER

-- V

UPPER

LOWER

PH_PSI (PSI Phase Selection)

Enable High Input Leakage Current

Upper Threshold V

Lower Threshold V

External 1k Pullup to 3.3 V -- -- 1.0 mA

UPPER

LOWER

DRVON

Output High Voltage

Sourcing 500 mA 3.0 -- -- V

Sourcing Current for Output High VCC=5V -- 2.5 4.0 mA

Output Low Voltage Sinking 500 mA -- -- 0.7 V

Sinking Current for Output Low 2.5 -- -- mA

Delay Time Propagation Delay from EN Low

to DRVON

Rise Time CL(PCB) = 20 pF, ΔVo= 10% to

90%

Fall Time CL(PCB) = 20 pF, ΔVo= 10% to

90%

Internal Pulldown Resistance 35 70 140 kΩ

VCCVoltage when DRVON
Output Valid

CURRENT SENSE AMPLIFIERS

Input Bias Current (Note 3)

CSx = CSxN = 1.4 V -- 0 -- nA

Common Mode Input Voltage Range
(Note 3)

Differential Mode Input Voltage Range
(Note 3)

3. Guaranteed by design, not tested in production.

=0.1mF)

VCC

-- 4 -- MHz

-- 4 -- V/s

3.0 -- -- V

-- -- 0.3 V

-- 650 770 mV

450 550 -- mV

-- 100 -- mV

-- 650 770 mV

450 550 -- mV

-- 100 -- mV

-- -- 0.7 V

0.3 -- -- V

-- 10 -- ns

-- 130 -- ns

-- 10 -- ns

-- -- 2.0 V

-- 0 . 3 -- 2.0 V

--120 -- 120 mV

CC

CC

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10

NCP5392P

ELECTRICAL CHARACTERISTICS

(Unless otherwise stated: 0C<TA<85C; 4.75 V < VCC< 5.25 V; All DAC Codes; C

Parameter UnitMaxTypMinTest Conditions

CURRENT SENSE AMPLIFIERS

Input Offset Voltage

Current Sense Input to PWM Gain

CSx = CSxN = 1.1 V, -- 1 . 0 -- 1.0 mV

0V<CSx--CSxN<0.1V, 5.7 6.0 6.3 V/V

(Note 3)

Current Sharing Offset CS1 to CSx All VID codes -- 2 . 5 -- 2.5 mV

IMON

to IMON Gain 1.325 V< V

V

DRP

V

to IMON --3 dB Bandwidth CL=30pFtoGND,

DRP

Output Referred Offset Voltage V

Minimum Output Voltage V

Output source current (Note 3) V

Output sink current (Note 3) V

Maximum Clamp Voltage V

R

= 100 kΩ to GND

L

DRP

DRP

=1V 300 -- -- mA

out

=0.3V 300 -- -- mA

out

DRP

R

LOAD

=1.6V,I

=1.2V,I

Voltage = 2 V,

<1.8V 1.98 2 2.02 V/V

DRP

=0mA 81 90 99 mV

SOURCE

= 100 mA -- -- 0.11 V

SINK

= 100 k

OSCILLATOR

Switching Frequency Range (Note 3)

R

Switching Frequency Accuracy 2-- or
4--Phase

Switching Frequency Accuracy
3--Phase

R

Output Voltage 1.95 2.01 2.065 V

OSC

= 49.9 kΩ 200 -- 224

OSC

R

= 24.9 kΩ 374 -- 414

OSC

R

=10kΩ 800 -- 978

OSC

R

= 49.9 kΩ 191 -- 234

OSC

R

= 24.9 kΩ 354 -- 434

OSC

R

=10kΩ 755 -- 1000

OSC

MODULATORS (PWM Comparators)

Minimum Pulse Width

FSW= 800 KHz -- 30 -- ns

Propagation Delay 20 mV of Overdrive -- 10 -- ns

0% Duty Cycle COMP Voltage when the PWM

Outputs Remain LO

100% Duty Cycle COMP Voltage when the PWM

Outputs Remain HI

PWM Ramp Duty Cycle Matching Between Any Two Phases -- 90 -- %

PWM Phase Angle Error (Note 3) Between Adjacent Phases 15 -- 15 

VR_RDY (POWER GOOD) OUTPUT

I

VR_RDY Output Saturation Voltage

=10mA, -- -- 0.4 V

PGD

VR_RDY Rise Time (Note 3) External Pullup of 1 kΩ to 1.25

=45pF,ΔVo= 10% to

V, C

TOT

90%

VR_RDY Output Voltage at Powerup
(Note 3)

VR_RDY High – Output Leakage

VR_RDYPulledupto5Vvia
2kΩ,t

100 ms  t

R(VCC)

R(V

 3 xt

 20 ms

CC

)

R(5V)

VR_RDY = 5.5 V via 1 K -- -- 0.2 mA

Current (Note 3)

VR_RDY Upper Threshold Voltage VCore Increasing, DAC = 1.3 V -- 310 270 mV

VR_RDY Lower Threshold Voltage VCore Decreasing

DAC = 1.3 V

3. Guaranteed by design, not tested in production.

=0.1mF)

VCC

-- 4 MHz

-- -- 1.15 V

100 -- 1000 kHz

kHz

kHz

-- 1.3 -- V

-- 2.3 -- V

-- 100 150 ns

-- -- 1.0 V

Below

DAC

410 370 mV

Below

DAC

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11

NCP5392P

ELECTRICAL CHARACTERISTICS

(Unless otherwise stated: 0C<TA<85C; 4.75 V < VCC< 5.25 V; All DAC Codes; C

Parameter UnitMaxTypMinTest Conditions

VR_RDY (POWER GOOD) OUTPUT

VR_RDY Rising Delay

VCore Increasing -- 500 -- ms

VR_RDY Falling Delay VCore Decreasing -- 5 -- ms

PWM OUTPUTS

Output High Voltage

Sourcing 500 mA 3.0 -- -- V

Mid Output Voltage 1.4 1.5 1.6 V

Output Low Voltage Sinking 500 mA -- -- 0.7 V

Delay + Fall Time (Note 3) CL(PCB) = 50 pF,

ΔVo = V

CC

to GND

Delay + Rise Time (Note 3) CL(PCB) = 50 pF,

ΔVo = G ND to V

CC

Output Impedance – HI or LO State Resistance to VCC(HI) or GND

(LO)

2/3/4--PhASE DETECTION

Gate Pin Source Current

Gate Pin Threshold Voltage 210 240 265 mV

Phase Detect Timer 15 20 27 ms

DIGITAL SOFT--START

Soft--Start Ramp Time

DAC=0toDAC=1.1V 1.0 -- 1.5 ms

VR11 Vboot time 400 500 600 ms

VID7/VR11/AMD INPUT

VID Upper Threshold

VID Lower Threshold V

VID Hysteresis V

V

UPPER

LOWER

UPPER

-- V

LOWER

AMD Input Bias Current 10 -- 20 mA

VR11 Input Bias Current (Note 3) 200 nA

Delay before Latching VID Change
(VID De--Skewing) (Note 3)

Measured from the edge of the

st

1

VID change

AMD Upper Threshold (Note 3) 2.9 V

AMD Lower Threshold (Note 3) 2.4 V

ENABLE INPUT

Enable High Input Leakage Current

Pullupto1.3V -- -- 200 nA

(Note 3)

VR11 Rising Threshold -- 650 770 mV

VR11 Falling Threshold 450 550 -- mV

VR11 Total Hysteresis Rising-- Falling Threshold -- 100 -- mV

AMD Upper Threshold -- 1.3 1.5 V

AMD Lower Threshold 0.9 1.1 -- V

AMD Total Hysteresis Rising -- Falling Threshold 200 mV

Enable Delay Time Measure Time from Enable

Transitioning HI to when Output
Begins

CURRENT LIMIT

to V

I

I

LIM

LIM

Gain Between V

DRP

to V

Gain in PSI 4 phase Between V

DRP

and V

and V

DRP

DRP

DRP

-- V

DRP

-- V

-- V

DFB

-- V

DFB

= 450 mV

DFB

= 650 mV

= 450 mV

DFB

= 650 mV

3. Guaranteed by design, not tested in production.

=0.1mF)

VCC

-- 10 15 ns

-- 10 15 ns

-- 75 -- Ω

60 80 150 mA

-- 650 770 mV

450 550 -- mV

-- 100 -- mV

200 -- 300 ns

2.5 4.0 ms

0.95 1 1.05 V/V

-- 0.25 -- V/V

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12

NCP5392P

ELECTRICAL CHARACTERISTICS

(Unless otherwise stated: 0C<TA<85C; 4.75 V < VCC< 5.25 V; All DAC Codes; C

Parameter UnitMaxTypMinTest Conditions

CURRENT LIMIT

to V

I

I

I

LIM

LIM

LIM

Gain in PSI 3 phase Between V

DRP

to V

Gain in PSI 2 phase Between V

DRP

Offset V

and V

and V

DRP

DRP

DRP

-- V

-- V

DFB

= 650 mV

-- V

DFB

= 650 mV

= 450 mV

= 450 mV

DRP

-- V

DFB

DRP

-- V

DFB

= 520 mV -- 5 0 0 50 mV

DFB

Delay -- 100 -- ns

OVERVOLTAGE PROTECTION

VR11 Overvoltage Threshold

VR11 PSI Overvoltage Threshold

(1.6 V DAC)

(Note 3)

AMD Overvoltage Threshold (Note 3) DAC +200 DAC +235 DAC +305 mV

AMD PSI Overvoltage Threshold

(1.55 V DAC)

(Note 3)

Delay 100 ns

UNDERVOLTAGE PROTECTION

VCC UVLO Start Threshold

VCC UVLO Stop Threshold 3.8 4.05 4.3 V

VCC UVLO Hysteresis 200 mV

12VMON UVLO

12VMON (High Threshold)

VCCValid 0.73 0.77 0.82 V

12VMON (Low Threshold) VCCValid 0.64 0.68 0.73 V

DAC (FEED FORWARD FUNCTION)

V

Output Source Current

Output Sink Current V

Max Output Voltage (Note 3) I

Min Output Voltage (Note 3) I

=3V 0.25 mA

OUT

=0.3V 1.5 mA

OUT

=2mA 3 V

source

=2mA 0.5 V

sink

VRM 11 DAC

Positive DAC Slew Rate

System Voltage Accuracy
(DACValuehasa19mVOffsetOver
the Output Value)

1.0V<DAC<1.6V

0.8V<DAC<1.0V

0.5V<DAC<0.8V

AMD DAC

Positive DAC Slew Rate

System Voltage Accuracy
(DACValuehasa19mVOffsetOver

1.0V<DAC<1.55V

0.3750 < DAC < 0.8 V

the Output Value)

V

CC

VCCOperating Current EN Low, No PWM -- 15 30 mA

3. Guaranteed by design, not tested in production.

=0.1mF)

VCC

-- 0.33 -- V/V

-- 0.5 -- V/V

DAC +150 DAC +185 DAC +200 mV

(1.6 V DAC)

+150

+200

(1.55 V DAC)

+235

+200

(1.55 V DAC)

+305

4 4.25 4.5 V

11 -- 16.5 mV/ms

--

--

--

--

--

--

0.5

5
8

-- 3.5 5 mV/ms

-- -- 0.5
5.0

mV

mV

%
mV
mV

%
mV

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13

NCP5392P

Table 1. VRM11 VID Codes

VID7

800 mV

0 0 0 0 0 0 0 0 00

0 0 0 0 0 0 0 1 01

0 0 0 0 0 0 1 0 1.60000 02

0 0 0 0 0 0 1 1 1.59375 03

0 0 0 0 0 1 0 0 1.58750 04

0 0 0 0 0 1 0 1 1.58125 05

0 0 0 0 0 1 1 0 1.57500 06

0 0 0 0 0 1 1 1 1.56875 07

0 0 0 0 1 0 0 0 1.56250 08

0 0 0 0 1 0 0 1 1.55625 09

0 0 0 0 1 0 1 0 1.55000 0A

0 0 0 0 1 0 1 1 1.54375 0B

0 0 0 0 1 1 0 0 1.53750 0C

0 0 0 0 1 1 0 1 1.53125 0D

0 0 0 0 1 1 1 0 1.52500 0E

0 0 0 0 1 1 1 1 1.51875 0F

0 0 0 1 0 0 0 0 1.51250 10

0 0 0 1 0 0 0 1 1.50625 11

0 0 0 1 0 0 1 0 1.50000 12

0 0 0 1 0 0 1 1 1.49375 13

0 0 0 1 0 1 0 0 1.48750 14

0 0 0 1 0 1 0 1 1.48125 15

0 0 0 1 0 1 1 0 1.47500 16

0 0 0 1 0 1 1 1 1.46875 17

0 0 0 1 1 0 0 0 1.46250 18

0 0 0 1 1 0 0 1 1.45625 19

0 0 0 1 1 0 1 0 1.45000 1A

0 0 0 1 1 0 1 1 1.44375 1B

0 0 0 1 1 1 0 0 1.43750 1C

0 0 0 1 1 1 0 1 1.43125 1D

0 0 0 1 1 1 1 0 1.42500 1E

0 0 0 1 1 1 1 1 1.41875 1F

0 0 1 0 0 0 0 0 1.41250 20

0 0 1 0 0 0 0 1 1.40625 21

0 0 1 0 0 0 1 0 1.40000 22

0 0 1 0 0 0 1 1 1.39375 23

0 0 1 0 0 1 0 0 1.38750 24

0 0 1 0 0 1 0 1 1.38125 25

0 0 1 0 0 1 1 0 1.37500 26

0 0 1 0 0 1 1 1 1.36875 27

0 0 1 0 1 0 0 0 1.36250 28

0 0 1 0 1 0 0 1 1.35625 29

0 0 1 0 1 0 1 0 1.35000 2A

0 0 1 0 1 0 1 1 1.34375 2B

0 0 1 0 1 1 0 0 1.33750 2C

0 0 1 0 1 1 0 1 1.33125 2D

0 0 1 0 1 1 1 0 1.32500 2E

0 0 1 0 1 1 1 1 1.31875 2F

VID6

400 mV

VID5

200 mV

VID4

100 mV

VID3

50 mV

VID2

25 mV

VID1

12.5 mV

VID0

6.25 mV

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NCP5392P

Table 1. VRM11 VID Codes

VID7

800 mV

0 0 1 1 0 0 0 0 1.31250 30

0 0 1 1 0 0 0 1 1.30625 31

0 0 1 1 0 0 1 0 1.30000 32

0 0 1 1 0 0 1 1 1.29375 33

0 0 1 1 0 1 0 0 1.28750 34

0 0 1 1 0 1 0 1 1.28125 35

0 0 1 1 0 1 1 0 1.27500 36

0 0 1 1 0 1 1 1 1.26875 37

0 0 1 1 1 0 0 0 1.26250 38

0 0 1 1 1 0 0 1 1.25625 39

0 0 1 1 1 0 1 0 1.25000 3A

0 0 1 1 1 0 1 1 1.24375 3B

0 0 1 1 1 1 0 0 1.23750 3C

0 0 1 1 1 1 0 1 1.23125 3D

0 0 1 1 1 1 1 0 1.22500 3E

0 0 1 1 1 1 1 1 1.21875 3F

0 1 0 0 0 0 0 0 1.21250 40

0 1 0 0 0 0 0 1 1.20625 41

0 1 0 0 0 0 1 0 1.20000 42

0 1 0 0 0 0 1 1 1.19375 43

0 1 0 0 0 1 0 0 1.18750 44

0 1 0 0 0 1 0 1 1.18125 45

0 1 0 0 0 1 1 0 1.17500 46

0 1 0 0 0 1 1 1 1.16875 47

0 1 0 0 1 0 0 0 1.16250 48

0 1 0 0 1 0 0 1 1.15625 49

0 1 0 0 1 0 1 0 1.15000 4A

0 1 0 0 1 0 1 1 1.14375 4B

0 1 0 0 1 1 0 0 1.13750 4C

0 1 0 0 1 1 0 1 1.13125 4D

0 1 0 0 1 1 1 0 1.12500 4E

0 1 0 0 1 1 1 1 1.11875 4F

0 1 0 1 0 0 0 0 1.11250 50

0 1 0 1 0 0 0 1 1.10625 51

0 1 0 1 0 0 1 0 1.10000 52

0 1 0 1 0 0 1 1 1.09375 53

0 1 0 1 0 1 0 0 1.08750 54

0 1 0 1 0 1 0 1 1.08125 55

0 1 0 1 0 1 1 0 1.07500 56

0 1 0 1 0 1 1 1 1.06875 57

0 1 0 1 1 0 0 0 1.06250 58

0 1 0 1 1 0 0 1 1.05625 59

0 1 0 1 1 0 1 0 1.05000 5A

0 1 0 1 1 0 1 1 1.04375 5B

0 1 0 1 1 1 0 0 1.03750 5C

0 1 0 1 1 1 0 1 1.03125 5D

0 1 0 1 1 1 1 0 1.02500 5E

0 1 0 1 1 1 1 1 1.01875 5F

VID6

400 mV

VID5

200 mV

VID4

100 mV

VID3

50 mV

VID2

25 mV

VID1

12.5 mV

VID0

6.25 mV

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NCP5392P

Table 1. VRM11 VID Codes

VID7

800 mV

0 1 1 0 0 0 0 0 1.01250 60

0 1 1 0 0 0 0 1 1.00625 61

0 1 1 0 0 0 1 0 1.00000 62

0 1 1 0 0 0 1 1 0.99375 63

0 1 1 0 0 1 0 0 0.98750 64

0 1 1 0 0 1 0 1 0.98125 65

0 1 1 0 0 1 1 0 0.97500 66

0 1 1 0 0 1 1 1 0.96875 67

0 1 1 0 1 0 0 0 0.96250 68

0 1 1 0 1 0 0 1 0.95625 69

0 1 1 0 1 0 1 0 0.95000 6A

0 1 1 0 1 0 1 1 0.94375 6B

0 1 1 0 1 1 0 0 0.93750 6C

0 1 1 0 1 1 0 1 0.93125 6D

0 1 1 0 1 1 1 0 0.92500 6E

0 1 1 0 1 1 1 1 0.91875 6F

0 1 1 1 0 0 0 0 0.91250 70

0 1 1 1 0 0 0 1 0.90625 71

0 1 1 1 0 0 1 0 0.90000 72

0 1 1 1 0 0 1 1 0.89375 73

0 1 1 1 0 1 0 0 0.88750 74

0 1 1 1 0 1 0 1 0.88125 75

0 1 1 1 0 1 1 0 0.87500 76

0 1 1 1 0 1 1 1 0.86875 77

0 1 1 1 1 0 0 0 0.86250 78

0 1 1 1 1 0 0 1 0.85625 79

0 1 1 1 1 0 1 0 0.85000 7A

0 1 1 1 1 0 1 1 0.84375 7B

0 1 1 1 1 1 0 0 0.83750 7C

0 1 1 1 1 1 0 1 0.83125 7D

0 1 1 1 1 1 1 0 0.82500 7E

0 1 1 1 1 1 1 1 0.81875 7F

1 0 0 0 0 0 0 0 0.81250 80

1 0 0 0 0 0 0 1 0.80625 81

1 0 0 0 0 0 1 0 0.80000 82

1 0 0 0 0 0 1 1 0.79375 83

1 0 0 0 0 1 0 0 0.78750 84

1 0 0 0 0 1 0 1 0.78125 85

1 0 0 0 0 1 1 0 0.77500 86

1 0 0 0 0 1 1 1 0.76875 87

1 0 0 0 1 0 0 0 0.76250 88

1 0 0 0 1 0 0 1 0.75625 89

1 0 0 0 1 0 1 0 0.75000 8A

1 0 0 0 1 0 1 1 0.74375 8B

1 0 0 0 1 1 0 0 0.73750 8C

1 0 0 0 1 1 0 1 0.73125 8D

1 0 0 0 1 1 1 0 0.72500 8E

1 0 0 0 1 1 1 1 0.71875 8F

VID6

400 mV

VID5

200 mV

VID4

100 mV

VID3

50 mV

VID2

25 mV

VID1

12.5 mV

VID0

6.25 mV

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NCP5392P

Table 1. VRM11 VID Codes

VID7

800 mV

1 0 0 1 0 0 0 0 0.71250 90

1 0 0 1 0 0 0 1 0.70625 91

1 0 0 1 0 0 1 0 0.70000 92

1 0 0 1 0 0 1 1 0.69375 93

1 0 0 1 0 1 0 0 0.68750 94

1 0 0 1 0 1 0 1 0.68125 95

1 0 0 1 0 1 1 0 0.67500 96

1 0 0 1 0 1 1 1 0.66875 97

1 0 0 1 1 0 0 0 0.66250 98

1 0 0 1 1 0 0 1 0.65625 99

1 0 0 1 1 0 1 0 0.65000 9A

1 0 0 1 1 0 1 1 0.64375 9B

1 0 0 1 1 1 0 0 0.63750 9C

1 0 0 1 1 1 0 1 0.63125 9D

1 0 0 1 1 1 1 0 0.62500 9E

1 0 0 1 1 1 1 1 0.61875 9F

1 0 1 0 0 0 0 0 0.61250 A0

1 0 1 0 0 0 0 1 0.60625 A1

1 0 1 0 0 0 1 0 0.60000 A2

1 0 1 0 0 0 1 1 0.59375 A3

1 0 1 0 0 1 0 0 0.58750 A4

1 0 1 0 0 1 0 1 0.58125 A5

1 0 1 0 0 1 1 0 0.57500 A6

1 0 1 0 0 1 1 1 0.56875 A7

1 0 1 0 1 0 0 0 0.56250 A8

1 0 1 0 1 0 0 1 0.55625 A9

1 0 1 0 1 0 1 0 0.55000 AA

1 0 1 0 1 0 1 1 0.54375 AB

1 0 1 0 1 1 0 0 0.53750 AC

1 0 1 0 1 1 0 1 0.53125 AD

1 0 1 0 1 1 1 0 0.52500 AE

1 0 1 0 1 1 1 1 0.51875 AF

1 0 1 1 0 0 0 0 0.51250 B0

1 0 1 1 0 0 0 1 0.50625 B1

1 0 1 1 0 0 1 0 0.50000 B2

1 1 1 1 1 1 1 0 OFF FE

1 1 1 1 1 1 1 1 OFF FF

VID6

400 mV

VID5

200 mV

VID4

100 mV

VID3

50 mV

VID2

25 mV

VID1

12.5 mV

VID0

6.25 mV

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NCP5392P

Table 2. AMD Processor 6--bit VID Code

(VID) Codes Nominal V

V

ID5VID4VID3VID2VID1VID0

0 0 0 0 0 0 1.550 V

0 0 0 0 0 1 1.525 V

0 0 0 0 1 0 1.500 V

0 0 0 0 1 1 1.475 V

0 0 0 1 0 0 1.450 V

0 0 0 1 0 1 1.425 V

0 0 0 1 1 0 1.400 V

0 0 0 1 1 1 1.375 V

0 0 1 0 0 0 1.350 V

0 0 1 0 0 1 1.325 V

0 0 1 0 1 0 1.300 V

0 0 1 0 1 1 1.275 V

0 0 1 1 0 0 1.250 V

0 0 1 1 0 1 1.225 V

0 0 1 1 1 0 1.200 V

0 0 1 1 1 1 1.175 V

0 1 0 0 0 0 1.150 V

0 1 0 0 0 1 1.125 V

0 1 0 0 1 0 1.100 V

0 1 0 0 1 1 1.075 V

0 1 0 1 0 0 1.050 V

0 1 0 1 0 1 1.025 V

0 1 0 1 1 0 1.000 V

0 1 0 1 1 1 0.975 V

0 1 1 0 0 0 0.950 V

0 1 1 0 0 1 0.925 V

0 1 1 0 1 0 0.900 V

0 1 1 0 1 1 0.875 V

0 1 1 1 0 0 0.850 V

0 1 1 1 0 1 0.825 V

0 1 1 1 1 0 0.800 V

0 1 1 1 1 1 0.775 V

1 0 0 0 0 0 0.7625 V

1 0 0 0 0 1 0.7500 V

1 0 0 0 1 0 0.7375 V

1 0 0 0 1 1 0.7250 V

1 0 0 1 0 0 0.7125 V

1 0 0 1 0 1 0.7000 V

1 0 0 1 1 0 0.6875 V

1 0 0 1 1 1 0.6750 V

1 0 1 0 0 0 0.6625 V

out

Units

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NCP5392P

Table 2. AMD Processor 6--bit VID Code

(VID) Codes UnitsNominal V

V

V

ID5

ID4

1 0 1 0 0 1 0.6500 V

1 0 1 0 1 0 0.6375 V

1 0 1 0 1 1 0.6250 V

1 0 1 1 0 0 0.6125 V

1 0 1 1 0 1 0.6000 V

1 0 1 1 1 0 0.5875 V

1 0 1 1 1 1 0.5750 V

1 1 0 0 0 0 0.5625 V

1 1 0 0 0 1 0.5500 V

1 1 0 0 1 0 0.5375 V

1 1 0 0 1 1 0.5250 V

1 1 0 1 0 0 0.5125 V

1 1 0 1 0 1 0.5000 V

1 1 0 1 1 0 0.4875 V

1 1 0 1 1 1 0.4750 V

1 1 1 0 0 0 0.4625 V

1 1 1 0 0 1 0.4500 V

1 1 1 0 1 0 0.4375 V

1 1 1 0 1 1 0.4250 V

1 1 1 1 0 0 0.4125 V

1 1 1 1 0 1 0.4000 V

1 1 1 1 1 0 0.3875 V

1 1 1 1 1 1 0.3750 V

V

V

ID3

ID2

V

V

ID1

ID0

out

FUNCTIONAL DESCRIPTION

General

The NCP5392P provides up to four--phase buck soluti on
which combines differential voltage sensing, differential
phase current sensing, and adaptive voltage positioning to
provide accurately regulated power necessary for both
Intel VR11.1and AMD CPU power system. NCP5392Phas
been designed to work with the NCP5359 driver.

AUTO-- PSI Function

NCP5392P makes energy saving possible without
receiving PSI signal from the CPU by wisely introducing
Auto--PSI feature. The device will monitor VID lines for
transition into/out--of Low Power States. When the VID
drops (An indication of entering power saving state), the
Auot--PSI logic will detect the transition and enable PSI
mode. On the other hand, when the VID rises (exiting
power saving mode), the Auto--PSI logic detects the
transition and exit PSI mode automatically. Auto--PSI uses
the dynamic VID(DVID) transitions of VR11.0 and
VR11.1 to shed phases. The phase shedding improves the
efficiency of the Vcore regulator eventually. In PSI mode,

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the total current limit is reduced by the ratio of the phase
count left after phase shedding.

Auto--PSI function can be activated and deactivated by
toggling APSI_EN (PIN38), but with lower priority
compared to PSI signal. When PSI (PIN37) ispulled tolow,
the system will be forced into PSI mode unconditionally,
and APSI_EN signal will be shielded.

NCP5392P can be operated up to four phases. It can be
configured as 1 or 2 phase operation when the system enter
PSI mode automatically (for example, VID down from 1.2 V
to 1.1 V). Choice of going down to 1 or 2 phases can be set
up by Pin40--PH_PSI. PH_PSI=high means one--phase
operation. PH_PSI=low means two--phase operation.

Remote Output Sensing Amplifier(RSA)

A true differential amplifier allows the NCP5392P to
measure V
ground reference point by connecting the V
point to VSP, and the V

voltage feedback with respect to the V

core

ground reference point to VSN.

core

core

This configuration keeps ground potential differences
between the local controller ground and the V

19

core

core

reference

ground

NCP5392P

reference point from affecting regulati on of V

and V

V

core

ground refere nce points. T he RSA also

core

core

between

subtracts the DAC (minus VID offset) voltage, thereby
producing an unamplified output error voltage at the
DIFFOUT pin. This output also has a 1.3 V bias voltage as
the floating ground to allow both positive and negative
error voltages.

Precision Programmable DAC

A precision programmable DAC is provided and system
trimmed. This DAC has 0.5% accuracy over the entire
operating temperature range of the part. The DAC can be
programmed to support either Intel VR11 or AMD 6--bit
VID code specifications.

High Performance Voltage Error Amplifier

The error amplifier is designed to provide high slew rate
and bandwidth. Although not required when operating as
the controller of a voltage regulator, a capacitor from
COMP to VFB is required for stable unity gain test
configurations.

Gate Driver Outputs and 2/3/4 Phase Operation

The part can be configured to run in 2--, 3--, or 4--phase
mode. In 2--phase mode, phases 1 and 3 should be used to
drive the external gate drivers as shown in the 2--phase
Applications Schematic, G2 and G4 must be grounded. In
3--phase mode, gate out put G4 must be grounded as shown
in the 3--pha se Applications Schematic. In 4--phase mode
all 4 gate outputs are used as shown in the 4 --phase
Applications Schematic. The Current Sense inputs of
unused channels should be connected to VCCP shown in
the Application Schematics. Please refer to table “PIN
CONNECTIONS vs. PHASE COUNTS” for details.

Differential Current Sense Amplifiers and Summing
Amplifier

Four differential amplifiers are provided to sense the output
current of each phase. The inputs of each current sense
amplifier must be connected across the current sensing
element of the phase controlled by the corresponding gate
output (G1, G2, G3, or G4). If a phase is unused, the
differential inputs to that phase’s current sense amplifier must
be shorted together and connected to the output as shown in
the 2-- and 3--phase Application Schematics.

The current signals sensed from inductor DCR are fed into
a summing amplifier to have a summed--up output (CSS UM).
Signal of CSSUM combines information of total current of all
phases in operation.

The outputs of current sense ampl ifiers control t hree
functions. First, the summing current signal (CCSUM) of
all phases will go through DROOP amplifier and join the
voltage feedback loop for output voltage positioning.
Second, the output signal from DROOPamplifier also goes
to ILIM amplifier to monitor the output current limit.
Finally, the individual phase current contributes to the
current balance of all phases by offsetting their ramp
signals of PWM comparators.

Thermal Compensation Amplifier with VDRP and VDFB
Pins

Thermal compensation amplifier is an internal amplifier
in the path of droop current feedback for additional
adjustment of the gain of summing current and temperature
compensation. The way thermal compensation is
implemented separately ensures minimum interference to
the voltage loop compensation network.

Oscillator and Triangle Wave Generator

A programmable precision oscillator is provided. The
oscillator’s frequency is programmed by the resistance
connected from the ROSC pin to ground. The user will
usually form this re sistance from two resistors in order to
create a voltage divider that uses the ROSC output voltage
as the reference for creating the current limit setpoint
voltage. The oscillator frequency range is 100 kHz per
phase to 1.0 MHz per phase. The oscillator generates up to
4 symmetricaltriangle waveformswith amplitudebetween

1.3 V and 2.3 V. The triangle waves have a phase delay
between them such that for 2--, 3-- and 4--phase operation
the PWM outputs are separated by 180, 120,and 90 angular
degrees, respectively.

PWM Comparators with Hysteresis

Four PWM comparators receive an error signal at their
noninverting input. E ach comparator receives one of the
triangle waves at its inverting output. The output of each
comparator generates the PWM outputs G1, G2, G3, and G4.

During steady state operation, the duty cycle will center
on the valley of the triangle waveform, with steady state
duty cycle calculated by V

. During a transient event,

out/Vin

both high and low comparator output transitions shiftphase
to the points where the error signal intersects the down and
up ramp of the triangle wave.

PROTECTION FEATURES

Undervoltage Lockout

An undervoltage lockout (UVLO) senses the VCCinput.
During power--up, the input voltage to the controller is
monitored, and the PWM outputs and the soft--start circuit
are disabled until the input voltage exceeds the threshold
voltage of the UVLO comparator. The UVLO comparator
incorporates hysteresis to avoid chattering.

Overcurrent Shutdown

A programmable overcurrent function i s incorporated
within the IC. A comparator and latch make up this
function. The inverting input of the comparator is
connected to the ILIM pin. The voltage at this pin sets the
maximum output current the converter can produce. The
ROSC pin provides a convenient and accurate reference
voltage from which a resistor divider can create the
overcurrent setpoint voltage. Although not actually
disabled, tying the ILIM pin directly to the ROSC pin sets
the limit above useful levels -- effectively disabling
overcurrent shutdown. The comparator noninverting input

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20

NCP5392P

is the summed current information from the VDRP minus
offset voltage. The overcurrent latch is set when the current
information exceeds the voltage at the ILIM pin. The
outputs are pulled low, and the soft--start is pulled low. The
outputs will remai n disabled until the V
removed and re--applied, or the ENABLE input is brought
low and then high.

Output Overvoltage and Undervoltage Protection and
Power Good Monitor

An output voltage monitor is incorporated. During normal
operation, if the output voltage is 180 mV (typical) over the
DAC voltage, the VR_RDY goes low , the DRVON signal
remains high, the PWM outputs are set low. The outputs will
remain disabled until the V

voltage is removed and

CC

reapplied. During normal operation, if the output voltage falls
more than 350 mV below the DAC setting, the VR_RDY pin
will be set low until the output voltage rises.

voltage is

CC

Figure 6. Typical Load Step Response

(full load, 35 A -- 100 A)

Soft--Start

There are two possible soft--start modes: AMD and
VR11. AMD mode simply ramps V

from 0 V directly

core

to the DAC setting at a fixed rate. The VR11 mode ramps

to 1.1 V boot vol tage at a fixed rate of 0.8 mV/mS,

V

core

pauses at 1.1 V for around 500 mS, reads the VID pins to
determine the DAC setting. Then ramps V

to the final

core

DAC setting at the Dynamic VID slew rate of up to

12.5 mV/mS. Typical AMD and VR11 soft--start sequences
are shown in the following graphs (Figure 9 and 10).

APPLICATION INFORMATION

The NCP5392P demo board for the NCP5392P is
available by request. It is configured as a four phase
solution with decoupling designed to provide a 1 mΩ load
line under a 100 A step load.

Startup Procedure

Start by installing the test tool software. It is best to
power the test tool from a separate ATX power supply. The
test tool should be set to a valid VID code of 0.5 V or above
in order for the controller to start. Consult the VTT help
manual for more detailed instruction.

Step Load Testing

The VTT tool is used to generate the di/dtstep load.
Select the dynamic loading option in the VTT test tool
software. Set the desired step load size, frequency, duty,
and slew rate. See Figure 6.

Dynamic VID Testing

The VTT tool provides for VID stepping based on the
Intel Requirements. Select the Dynamic VID option.
Before enabling the test set the lowest VID to 0.5 V or
greaterand setthe highestVIDto a valuethat is greater than
the lowest VID selection, then enable the test. See Figures
7 and 8.

Figure 7. 1.6 V to 0.5 V Dynamic VID response

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21

NCP5392P

Figure 8. Dynamic VID Settling Time Rising

(CH1: VID1, CH2: DAC, CH3:VCCP)

Design Methodology

Decoupling the VCCPinontheIC

An RC input filter is required as shown in the VCCpin to
minimize supply noise on the IC. The resistor should be
sized such that it does not generate a large voltage drop
between 5 V supply and the IC.

Understanding Soft--Start

The controller supports two different startup routines. An
AMD ramp to the initial VID code, or a VR11 Ramp to the

1.1 V boot voltage, with a pause to capture the VID code
then resume ramping t o target value based on internal slew
rate limit. The initial ramp rate was set to be 0.8 mV/mS.

Figure 10. AMD Startup

Programming the Current Limit and the Oscillator
Frequency

The demo board is set for an operating frequency of

approximately 330 kHz. The R

pin provides a 2.0 V

OSC

reference voltage which is divided down with a resistor
divider and fed into the current limit pin ILIM. Then
calculate the individual RLIM1 and RLIM2 values for the
divider. The series resistors RLIM1 and RLIM2 sink
current from the ILIM pin to ground. This current is
internally mirrored into a capacitor to create an oscillator.
The period is proportional to the resistance a nd frequency
is inversely proportional to the total resistance. The total
resistance may be estimated by Equation 1. This equation
is valid for the individual phase frequency in both three and
four phase mode.

R

≅ 20947 × F

osc

30.5 kΩ ≅ 20947 × 330

SW

−1.1262

−1.1262

(eq. 1)

Figure 9. VR11.1 Startup

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NCP5392P

S

O

S

O

S

U

60

current of all phases multiplied by a controlled gain

50

(Acssum*Adrp). DCR sensed inductor current is a function
of the winding temperature. The best approach is to set the

40

maximum current limit based on expected average
maximum temperature of the inductor windings,

30

Rosc-- kohm

20

10

Calculation
Real

0

100 1000

Freq--kHz

Figure 11. ROSC vs. Frequency

For multiphase controller, the ripple current can be calculated as,

− N ⋅ V

(V

Ipp =

in

L ⋅ FSW⋅ V

Therefore calculate the current limit voltage as below,

V

In Equation 4, A

CSSUM

LIMIT

V

LIMIT

and A

≅ A

≅ A

are the gain of current summing amplifier and droop amplifier.

DRP

CSSUM

CSSUM

⋅ A

⋅ A

DRP

DRP

⋅ DCR

⋅ DCR

Tmax

Tmax

⋅ (I

⋅I

The current limit function is based on the total sensed

DCR

) ⋅ V

out

in

MIN_OCP

MIN_OCP

= DCR

Tmax

out

⋅+0.5 ⋅ Ipp)

⋅+0.5 ⋅

(1 + 0.00393 ⋅ (T

25C

(V

− N ⋅ V

in

L ⋅ FSW⋅ V

out

) ⋅ V

in

max

out

− 25))



(eq. 2)

(eq. 3)

(eq. 4)

Acssum Adrp

I1

I2
I3
I4

+

Ilim

RISO1

RSUM

RNOR

RT2

--

+

Figure 12. ACSSUM and ADRP

As introduced before, V

LIMIT

divider connected to Rosc pin, thus,

R

R

LIM1

ISO1

1

+ R

LIM2

+ R

+ R

I

2

A

DRP

V

A

=−

LIMIT

CSSUM

(R

NOR

= 2V⋅

=−4

R

NOR

+ R

⋅ (R

I

RISO2

+

--

OCP

event

comes from a resistor

⋅ COEpsi

LIM2

+ RT2)

ISO2

+ RT2) ⋅ R

(eq. 5)

(eq. 6)

M

R

and R

ISO1

temperature sense resistor placed near inductor. R

are in series with RT2, the NTC

ISO2

SUM

the resistor connecting between pin VDFB and pin
CSSUM. If PSI = 1, PSI function is off, the current limit
follows the Equation 7; if PSI = 0, the power saving mode
will be enabled, COEpsi is a coefficient for the current
limiting related with power saving function (PSI), the
current limit can be calculated from Equation 8. COEpsi
value is one over the original phase count N. Refer to the
PSI and phase shedding section for more details.

is

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NCP5392P

Final Equations for the Current Limit Threshold

Final equations are described based on two conditions: normal mode and PSI m ode.

2V⋅R

LIM2

R

I

(normal) ≅

LIMIT

I

LIMIT

(PSI) ≅

4 ⋅

R

⋅(R

4 ⋅

NOR

(R

NOR+RISO1+RISO2

R

⋅(R

NOR

(R

NOR+RISO1+RISO2

ISO1+RISO2

ISO1+RISO2

+RT2)⋅R

+RT2)

+RT2)⋅R

+RT2)

2V⋅R

R

LIM1+RLIM2

SUM

N is the number of phases involved in the circuit.

The inductors on the demo board have a DCR at 25Cof

0.6 mΩ. Selecting the closest available values of 21.3 kΩ
for R

and9.28kΩ for R

LIM1

yields a nominal

LIM2

operating frequency of 330 kHz. Select R
= 1 k, RT2=10K(25C), R

NOR/RSUM

application diagram). That results to an approximate
current limit of 133 A at 100C for a four phase operation
and 131 A at 25C. The total sensed current can be
observed as a scaled voltage at the VDRP with a positive
no--load offset of a pproximately 1.3 V.

Inductor Selection

When using inductor current sensing it is recommended
that the inductor does not saturate by more than 10% at
maximum load. The inductor also must not go into hard
saturation before current limit trips. The demo board
includes a four phase output filter using the T44 --8 core
from Micrometals with 3 turns and a DCR target of0.6 mΩ
@25C. Smaller DCR values can be used, however,
current sharing accuracy and droop accuracy decrease as
DCR decreases. Use the NCP5392P design aide for
regulationaccuracy calculationsfor specific valueof DCR.

LIM1+RLIM2

⋅ DCR

SUM

LIM2

⋅ COEpsi

⋅ DCR

1=1k,R

ISO

= 2, (refer to

(1 + 0.00393 ⋅ (T

25C

(1 + 0.00393 ⋅ (T

25C

ISO2

inductor

− 25))

inductor

Inductor Current Sensing Compensation

The NCP5392P uses the inductor current sensing
method. An RC filter is selected to cancel out the
impedance from inductor and recover the current
information through the inductor’s DCR. This is done by
matching the RC time constant of the sensing filter to the
L/DCR time constant. The first cut approach is to use a 0.1
mF capacitor for C and then solve for R.

R

(T) =

sense

0.1 ⋅ mF ⋅ DCR

Because the inductor value is a function of load and
inductor temperature final selection of R is best done
experimentally on the bench by monitoring the V
and performing a step load test on the actual solution.

− 25))

− 0.5 ⋅

− 0.5 ⋅

(V

25C

− N ⋅ V

(V

in

L ⋅ FSW⋅ V

− V

out

in

L ⋅ FSW⋅ V

) ⋅ V

) ⋅ V

out

out

in

(eq. 7)

out

in

(eq. 8)

(eq. 9)

L

⋅ (1 + 0.00393(T − 25))

droop

pin

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24

NCP5392P

Simple Average SPICE Model

A simple state average model shown in Figure 13 ca n be used t o determine a stable solution and provide insight into the

control system.

GAIN = 1

VRamp_min

1.3V

Unity Gain BW=15MHz

Voff

Voff

1E3

RSUM

1k

RF

2.2k

0

R8

1k

V3

12V

CH

22p

{-- 2/3*4}

RDFB

2k

C5

10.6p

0

C4

10.6p

0

5.11k

CF

1.8n

R6

1k

0
12

22p

1E3

R12

+

--

GAIN = {6}

0

1

{185e--9/4}

CDFB

Vdrp

CFB1

680P

E1

L

+

--

E

2

{0.6E--3/4}

RFB1

RFB

1k

Voff

DCR

RDAC

50

69.8

1 2

2

{3.5e--9/6}

1

Figure 13. NCP5392P Average SPICE Model

LBRD

100p

CBulk
{560e--6*6}

ESRBulk
{7e--3/6}

ESLBulk

CDAC

12n

Voff set

1.3V

0

RBRD

0.75m
CCer

2

{1.5e--9/18}

1

DC = 1.2V

AC = 0

R11

1k

R9

1k

{22e--6*18}

ESRCer

{1.5e--3/18}

0Aac

ESLCer

0Adc

VDAC

TRAN = PULSE
(0 0.05 400u 5u 5u 500u 1000u)

0

Vdrp

R10

1E3

2k

C6

10.6p

Voff

0

I2 = 110

TD = 100u

TR = 50n

TF = 50n

PW = 100u

PER = 200u

I1 = 50

IMON

I1

Vout

0

Compensation and Output Filter Design

If the required output filter and switching frequency are
significantly different, it’s best to use the available PSPICE
models to design the compensation and output filter from
scratch.

The design target for this demo board was 1.0 mΩ up to

2.0 MHz. The phase switching frequency is currently set to
330 kHz. It can easily be seen that the board impedance of

0.75 mΩ between the load and the bulk capacitance has a
large effect on the output filter. In this case the six 560 mF
bulk capacitors have an ESR of 7.0 mΩ. Thus the bulk ESR

plus the board impedance is 1.15 mΩ +0.75mΩ or

1.9 mΩ. The actual output filter impedance does not drop
to 1.0 mΩ until the ceramic breaks in at over 375 kHz. The
controller must provide some loop gain slightly less than
one out to a frequency in excess 300 kHz. At frequencies
below where the bulk capacitance ESR breaks with the
bulk capacitance, the DC--DC converter must have
sufficiently high gain to control the output impe dance
completely. Standard Type--3 compensation works well
with the NCP5392P.

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25

dB

NCP5392P

Zout Open Loop

Zout Closed Loop

Open Loop Gain with Current Loop Closed

Voltage Loop Compensation Gain

80

60

40

20

0

-- 2 0

-- 4 0

-- 6 0

-- 8 0

--100
100 1000 10000 100000 1000000 10000000

1mOhm

Figure 14. NCP5392P Circuit Frequency Response

The goal is to compensate the system such that the
resulting gain generates constant output impedance from
DC up to the frequency where the ceramic takes over
holding the impedance below 1. 0 mΩ. See the example of
the locations ofthe polesand zerosthat wereset to optimize
the model above.

By matching the following equations a good set of
starting compensation values can be found for a typical
mixed bulk and ceramic capacitor type output filter.

=

2π ⋅ C

1

Bulk

⋅ (RBRD + ESR

Cer

) ⋅ C

1

(eq. 10)

Bulk

(eq. 11)

Bulk

1

2π ⋅ CF ⋅ RF

2π ⋅ CFB1 ⋅ (RFB1 + RFB)

=

2π ⋅ (RBRD + ESR

1

RFBshould be set to provide optimal thermal
compensation in conjunction with thermistor R
and R

. With RFBset to 1.0 kΩ,R

ISO2

FB1

T2,RISO1

is usually set to

100 Ω for m aximum phase boost, and the value of RF is
typically set to 3.0 kΩ.

Droop Injection and Thermal Compensation

The VDRP signal is generated by summing the sensed
output currents for each phase. A droop amplifier is added
to adjust the total gain to approximately eight. VDRP is
externally summed into the feedback network by the
resistor RDRP. This introduces an offset which is
proportional to the output current thereby forcing a
controlled, resistive output impedance.

Frequency

)

CH

RT

RL

IBias

RDRP
RISO2

RISO1

RSUM

RSx

CSx

Droop

Amp

RNOR

Gain = 4

CSSUM

Amp

RFB1

+

--

--

+

1.3 V

+

--

Gain = 1

CFB1

RFB

1.3 V

1.3 V

+

RF

--

+

Error
Amp

CF

+

--

PWM

Comparator

+

Figure 15. Droop Injection and Thermal

Compensation

RDRP determi nes the target output impedance by the

basic equation:

V

out

= Z

I

out

R

=

DRP

out

R

=

FB

R

FB

⋅ DCR ⋅ A

Z

CSSUM

out

R

DRP

⋅ DCR ⋅ A

CSSUM

⋅ A

DRP

⋅ A

DRP

(eq. 12)

(eq. 13)

The value of the inductor’s DCR is a function of

temperature according to the Equation 14:

DCR (T) = DCR

⋅ (1 + 0.00393 ⋅ (T − 25))

25C

(eq. 14)

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26

NCP5392P

Actual DCR increases by temperature, the system can be
thermally compensated to cancel this effect to a great
degree by adding an NTC in parallel with R

NOR

to reduce
the droop gain as the temperature increases. The NTC
device is nonlinear. Puttinga resistorin serieswith theNTC
helps make the device appear more linear with

⋅ DCR

R

Z

(T) =

out

FB

⋅ (1 + 0.00393 ⋅ (T − 25)) ⋅ A

25C

temperature. The series resistor issplit and inserted onboth
sides of the NTC to reduce noise injection into the feedback
loop. The recommended total value for R
approximately 1.0 kΩ.

The output impedance varies with inductor t emperature

by the equation:

R

DRP

CSSUM

By including the NTC RT2and the series isolation resistors the new equation becomes:

R

⋅ DCR

R

Z

(T) =

out

FB

⋅ (1 + 0.00393 ⋅ (T − 25)) ⋅ A

25C

The typical equation of an NTC is based on a curve fit

R

CSSUM

DRP

Acssum Adrp

NOR

⋅

(R

NOR+RISO1+RISO2

Equation 17

1

RT2(T) = RT2

25C

⋅ e

β



273+T

−

298

1



(eq. 17)

The demo board use a 10 kΩ NTC with a β value of3740.

Figure 16 showsthe comparison of the compensated output
impedance and uncompensated output impedance varying
with temperature.

0.0013

0.0012

0.0011

Ohm

0.0009

0.0008

0.0007

0.0006

0.001

25 45 65 85 105

Figure 16. Z

Zout
Zout(uncomp)

Celsius

vs. Temperature

out

IMON for Current Monitor

Since VDRP signal reflects the current information of all
phases. It ca n be fed i nto the IMON amplifier for current
monitoring as shown in Figure 17. IMON amplifier has a
fixed gain of 2 with an offset when VDRP is equal to 1.3 V,
the internal floating reference voltage. The IMON
amplifier will be saturated at an maximum output of1.09 V
therefore the total gain of current should be carefully
considered to make the maximum load current indicated by
the IMON output. Figure 18 shows a typical of the relation
between IMON output and the load current.

I1
I2

+

I3
I4

Ilim

1.05

0.84

0.63

0.42

Vimon--V

0.21

0

0 102030405060708090100

Figure 18. IMON Output vs. Output Current

Power Saving Indicator (PSI) and Phase Shedding

VR11.1 requires the processor to provide an output
signal to the VR controller to indicate when the processor
is in a low power state. NCP5392P use the status of PSI pin
to decide if there is a need to change its operating state to
maximize efficiency at light loads. When PSI = 0, the PSI

RISO1

RSUM

Figure 17. IMON Circuit

function will be enabled, and VR system wil l be running at
a single phase power saving mode.

The PSI signal will de--assert 1 ms prior to moving to a
normal power state.

At power saving mode, NCP5392P works with the
NCP5359 driver to represent diode emulation mode at light
load for further power saving.

When system switches on PSI function, a phase shedding
will be presented. Only one or two phases (depending on

⋅ A

DRP

⋅(R

ISO1+RISO2

RNOR

Vimon vs. Iout

Iout--A

+RT2)⋅R

RT2

--

+

+RT2)

ISO1

SUM

RISO2

plus R

+

--

+

--

Gain = 2

ISO2

(eq. 15)

(eq. 16)

OCP

event

Imon

is

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27

NCP5392P

PH_PSI) are active in the emulation mode while other
phases are shed. Figure 19 indicates a PSI--on transition
from a3--phase mode to a single phase mode. While staying
stable in PSI mode, the PWM signal of phase 1 will vary
from a mid--state level (1.5 V typical) to high level while
other phases all go to mid--state level. Vice verse, when PSI
signal goes high, the system will go back to the original
phase mode such as shown in Figure 20.

Auto--PSI Function:

In Auto--PSI mode (APSI_EN=1, PSI=1), the device will
monitor VID lines for transition into/out--of Low Power
States. Figure 21 to 24 describe the Auto--PSI function
during VID transitions, in one--phase and two--phase
operation respectively.

Figure 21. 10 A Load, VID Down, into PSI (One Phase)

Figure 19. PSI turns on, CH1: PWM1, CH2: PWM2,

CH3: PWM3, CH4: PSI

Figure 20. PSI turns off, CH1: PWM1, CH2: PWM2,

CH3: PWM3, CH4: PSI

Figure 22. 10 A Load, VID Up, Out of PSI (One Phase)

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28

NCP5392P

Figure 23. 10 A Load, VID Down, into PSI (Two Phase)

voltage even during a dynamic change in the VID setting
during operation.

Figure 25. VR11.1, 1.6 V OVP Event

Figure 24. 10 A Load, VID Up, Out of PSI

(Two Phase)

OVP Improved Performance

The overvoltage protection threshold is not adjustable.
OVP protection is enabled as soon as soft--start begins and
is disabled when part is disabled. When OVP is tripped, the
controller commands all four gate drivers to enable their
low side MOSFETs and VR_RDY transitions low. In order
to recover from an OVPcondition, V

must fall below the

CC

UVLO threshold. See the state diagram for further details.
The OVP circuit monitors the output of DIFFOUT. If the
DIFFOUT signal reaches 180 mV (typical) above the
nominal 1.3 V offset the OVP will trip and VRRDY will be
pulled low, after eight consecutive OVP events are
detected, all PWMs will be latched. The DIFFOUT signal
is the difference between the output voltage and the DAC
voltage (minus 19 mV if in VR11.1 modes) plus the 1.3 V
internal offset. This results in the OVPtracking on the DAC

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Figure 26. AMD, 1.55 V OVP Event

Gate Driver and MOSFET Selection

ON Semiconductor provides the NCP5359 as a
companion gate driver IC. The NCP5359 driver is
optimized to work with a range of MOSFETs commonly
used in CPU applications. The NCP5359 provides special
functionality including power saving mode operation and
is required for high performance dynamic VID operation.
Contact your local ON Semiconductor applications
engineer for MOSFET recommendations.

Board Stackup and Board Layout

Close attention should be paid to the routing of the sense
traces and control lines that propagate away from the
controller IC. Routing should follow the demo board
example. For further inform ation or layout review contact
ON Semiconductor.

29

EN

VID

NCP5392P

SYSTEM TIMING DIAGRAM

12 V (Gate Driver)

UVLO

5 V (Controller)

UVLO

3.5 ms

Valid VID

DRVON

VSP--VSN

VR_RDY

UVLO

EN

DRVON

1 msmin

1.5 ms

500 ms

500 ms

Figure 27. Normal Startup

12 V (Gate Driver)

UVLO

5 V (Controller)

POR

3.5 ms

VID

VSP--VSN

VR_RDY

1.5 ms

1ms

500 ms

Figure 28. Driver UVLO Limited Startup

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30

Valid VID

1 msmin

500 ms

NCP5392P

12345678

Diffout ~ 1.3 V

VR_RDY

DRVON = High

VSP = VID -- 19 mV

185 mV

12345678

185 mV

Figure 29. OVP Shutdown

VDRP

VR_RDY

DRVON

+1.3

I

limit

Figure 30. Non-- PSI Current Limit

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31

PIN ONE

a

LOCATION

2X

2X

40X

EXPOSED PAD

C

C

0.05

0.15 C

0.15

0.10 C

0.08 C

L

40X

b

40X

A0.10 B

TOP VIEW

C

SIDE VIEW

11

10

1

40

BOTTOM VIEW

PACKAGE DIMENSIONS

D A B

(A3)

A1

D2

20

40X

21

E2

30

31

36X

e

NCP5392P

QFN40 6x6, 0.5P

CASE 488AR --01

ISSUE A

E

A

SEATING

C

PLANE

K

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.

2. CONTROLLING DIMENSIONS: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN

0.25 AND 0.30mm FROM TERMINAL

4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.

MILLIMETERS

DIM MIN MAX

A 0.80 1.00
A1 0.00 0.05
A3 0.20 REF

b 0.18 0.30

D 6.00 BSC
D2 4.00 4.20

E 6.00 BSC

e 0.50 BSC

L 0.30 0.50

K 0 . 2 0 -- -- --

4.20E2 4.00

SOLDERING FOOTPRINT*

6.30

4.20

40X

0.65
1

4.20

6.30

40X

0.30

DIMENSIONS: MILLIMETERS

*For additional information on our Pb--Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

36X

0.50 PITCH

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