Datasheet NCP1560HDR2 Datasheet (MOTOROLA)

NCP1560

Full Featured Voltage Mode
PWM Controller

The NCP1560 PWM controller contains all the features and
flexibility needed to implement voltage-mode control in high
performance single ended DC/DC converters. This device cost
effectively reduces system part count with the inclusion of a high
voltage start-up regulator that operates over a wide input range of

21.5 V to 150 V. The NCP1560 provides two control outputs, OUT1
which controls the main PWM switch and OUT2 with adjustable
over-lap delay, which can control a synchronous rectifier switch or an
active clamp/reset switch. Other distinctive features include: two
mode over current protection, line under/over voltage lockout, fast
line feedforward, soft start and a maximum duty cycle limit.

Features

• Minimum Operating Voltage of 21.5 V

• Internal High Voltage Start-up Regulator

• Dual Control Outputs with Adjustable Overlap Delay

• Single Resistor Oscillator Frequency Setting

• Fast Line Feedforward

• Line Under/Over Voltage Lockout

• Dual Mode Over Current Protection

• Programmable Maximum Duty Cycle Control

• Maximum Duty Cycle Proportional to Line Voltage

• Programmable Soft Start

• Precision 5.0 V Reference

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MARKING
DIAGRAM

16

SO-16

16

1

ORDERING INFORMATION

Device Package Shipping

NCP1560HDR2 SO-16 2500/Tape & Reel

D SUFFIX

CASE 751B

NCP1560 = Device Code
A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week

NCP1560

AWLYWW

1

T ypical Applications

• Telecommunication Power Converters

• Industrial Power Converters

• High Voltage Power Modules

• +42 V Automotive Systems

• Control Driven Synchronous Rectifier Power Converters

 Semiconductor Components Industries, LLC, 2003

January, 2003 - Rev. 5

1 Publication Order Number

NCP1560/D

NCP1560

UV/OV

CSKIP

DC

MAX

V

CS

R

FF

High Voltage

in

Start-up

Regulator

5.0 V

Reference

UV

Fault

Detection

T

Modulator

Delay

Logic

Output
Drivers

Oscillator

V

AUX

V

REF

OUT1

OUT2

t

D

V

EA

SS

GND

Figure 1. Simplified Block Diagram

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2

V

in

V

in

V

AUX

C

AUX

GND

UV/OV

CSKIP

C

CSKIP

CS

C

SS

R

T

R

FF

V

16

14

2

5

SS

R

FF

1

6

9

4

in

7

T

1.49 V

11 A

V

+

1.3 V*

-

I

FF

13.8 mA

+

11 V/7 V

-

+

+

-

-

+

3.6 V

-

V

REF

Disable

One Shot

Pulse

(600 ns)

+

-

+

0.6 V

-

+

0.5 V

-

REF

Disable_ss

STOP

* Trimmed during
manufacturing to obtain

1.3 V with RT = 101 k

5.3 k

6.7 k

NCP1560

Disable

One Shot

Pulse

(250 ns)

Disable_V

REF

S

Monotonic

Dominant)

Start

Latch

(Reset

Q

R

+

STOP

Disable_ss

-

­+

Clock

-

+
+
2 V

-

+

­+

-

Soft Start

Comparator

S

Output

Latch

(Reset

Dominant)

R

Q

Delay

Logic

CURRENT MIRROR

Oscillator Ramp

I

2 V

1

2

10 pF

One Shot

Pulse

FF Ramp
(Adjustable)

+

­2 V

2 V

+

-

I

1

+

-

Clock

V

I 

125 k

+
+
V

-

-

10 pF

C

FF

V

AUX

5.0 V Reference
DIS

Disable_V

V

AUX

Comparator

+

-

20 k

Max DC

+

Comparator

-

2 V

+

V

DC(inv)

-

REF

V

AUX

DIS

PWM

40 k

32 k

27 k

DIS

2 k

10

V

12
t

15

13

11

D

V

REF

R

OUT2

V

REF

8

D

OUT1

EA

R

MDP

DC

MAX

R

P

Figure 2. NCP1560 Functional Block Diagram

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3

NCP1560

PIN DESCRIPTION

Pin Name Application Information

1 V

in

2 UV/OV Input supply voltage is scaled down and sampled by means of a resistor divider. The supply voltage must

3 NC Not Connected.
4 FF An external resistor between Vin and this pin adjusts the amplitude of the FF Ramp in proportion to Vin. By

5 CS Over current sense input. If the CS voltage exceeds 0.48 V or 0.57 V, the converter enters the Cycle by

This pin is connected to the bulk DC input voltage supply. A constant current source supplies current from
this pin to the capacitor connected on the V
range is 21.5 V to 150 V.

pin. The charge current is typically 13.8 mA. Input voltage

AUX

be scaled down between 1.52 V and 3.61 V within the specified input voltage range.

varying the feedforward ramp amplitude in proportion to the input voltage, changes in loop bandwidth are
eliminated.

Cycle or Cycle Skip current limit mode, respectively.

6 CSKIP The capacitor connected between this pin and ground sets the Cycle Skip period. A soft start sequence

follows at the conclusion of the fault period.
7 R
8 DC

T

MAX

A single external resistor between this pin and GND sets the oscillator fixed frequency.

An external resistor between this pin and GND sets the voltage on the Max DC Comparator inverting in-

put. The duty cycle is limited by comparing the voltage on the Max DC Comparator inverting input to the

Feedforward Ramp.
9 SS An internal 6.2 A current source charges the external capacitor connected to this pin. The duty cycle is

limited during start-up by comparing the voltage on this pin to the Oscillator Ramp.

10 V

EA

The error signal from an external error amplifier is fed into this input and compared to the Feedforward

Ramp. A series diode and resistor offset the voltage on this pin before it is applied to the PWM Compara-

tor inverting input.

11 V
12 t

REF

D

Precision 5.0 V reference output. Maximum output current is 6 mA.

An external resistor between V

tions.

and this pin sets the overlap delay between OUT1 and OUT2 transi-

REF

13 OUT2 Output of the PWM controller with leading and trailing edge overlap delay. OUT2 can be used to drive a

synchronous rectifier topology, an active clamp/reset switch, or both.

14 GND Control circuit ground.
15 OUT1 Main output of the PWM controller.
16 V

AUX

Positive input supply voltage. This pin is connected to an external capacitor for energy storage. An inter-

nal current supplies current from Vin to this pin. Once the voltage on V

source turns OFF. It turns ON again once V

the IC via this pin, by means of an auxiliary winding.

falls to 7 V. During normal operation, power is supplied to

AUX

reaches 11 V, the current

AUX

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4

NCP1560

MAXIMUM RATINGS (Note 1)

Rating

Input Line Voltage V
Auxiliary Supply Voltage V
Auxiliary Supply Input Current I
OUT1 and OUT2 Voltage V
OUT1 and OUT2 Output Current I

5.0 V Reference Voltage V

5.0 V Reference Output Current I
All Other Inputs/Outputs Voltage V
All Other Inputs/Outputs Current I
Operating Junction Temperature T
Storage Temperature Range T
Power Dissipation at TA = 25°C P
Thermal Resistance, Junction to Ambient R

1. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute maximum-rated conditions is not implied. Functional
operation should be restricted to the Recommended Operating Conditions.
A.This device series contains ESD protection and exceeds the following tests:

Pin 1 is the HV start-up of the device and is rated to the max rating of the part, or 150 V.

Machine Model Method 150 V.

Pins 2-16: Human Body Model 4000 V per MIL-STD-883, Method 3015.

Machine Model Method 200 V.

Symbol Value Unit

in

AUX

AUX

OUT

OUT

REF

REF

IO

IO

stg

D



J

JA

-0.3 to 150 V

-0.3 to 16 V
35 mA

-0.3 to (V

+ 0.3 V) V

AUX

10 mA

-0.3 to 6.0 V

6.0 mA

-0.3 to V

REF

10 mA

-40 to 125 °C

-55 to 150 °C

0.77 W
130 °C/W

V

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NCP1560

ELECTRICAL CHARACTERISTICS (V

R

= 60.4 k, RFF = 432 k, for typical values TJ = 25°C, for min/max values, TJ = -40°C to 125°C, unless otherwise noted)

D

Characteristic

START-UP CONTROL AND V

Regulation

V

AUX

Start-up Threshold/V
Minimum Operating V
Hysteresis

AUX

AUX

Minimum Start-up Voltage (Pin 1)
I

START

= 1.0 mA, V

AUX

= V

Start-up Circuit Output Current

V

= 0 V

AUX

T

= 25°C

J

T

= -40°C to 125°C

J

= V

V

AUX

TJ = 25°C
T

= -40°C to 125°C

J

AUX(on)

- 0.2 V

Start-up Circuit Off-State Leakage Current (Vin = 150 V)

TJ = 25°C
T

= -40°C to 125°C

J

Start-up Circuit Breakdown Voltage (Note 2)

I

START(off)

= 50A, TJ = 25°C

Auxiliary Supply Current After V

Outputs Disabled

V

= 0 V

EA

= 0.7 V

V

UV/OV

Outputs Enabled

REGULATOR

AUX

Regulation Peak (V

Valley Voltage After Turn-On

- 0.2 V

AUX(on)

Turn-On

AUX

= 48 V, V

in

AUX

= 12 V, VEA = 2 V, RT = 101 k, C

AUX

Symbol Min Typ Max Unit

increasing)

V
V

V

START(min)

I

START(off)

AUX(on)
AUX(off)

V

I

START

V

(BR)DS

I

AUX1

I

AUX2

I

AUX3

= 6800 pF,

CSKIP

10.5

6.6

H

-

11.0

7.0

4.0

- 19.3 21.5

13
10

10

8

-

-

17.5

-

13.8

-

23

-

150 - - V

-

-

-

2.7

1.3

4.6

LINE UNDER/OVERVOLTAGE DETECTOR

Undervoltage Threshold (V

Increasing) V

in

Undervoltage Hysteresis V
Overvoltage Threshold (Vin Increasing) V
Overvoltage Hysteresis V

Undervoltage Propagation Delay to Output t
Overvoltage Propagation Delay to Output t

UV

UV(H)

OV

OV(H)

UV

OV

1.40 1.52 1.64 V

0.080 0.098 0.120 V

3.47 3.61 3.75 V

- 0.145 - V

- 250 - ns

- 160 - ns

CURRENT LIMIT

Cycle by Cycle Threshold Voltage
Propagation Delay to Output (VEA = 2.0 V)

VCS = I

to 2.0 V, measured when V

LIM1

reaches 0.5 V

OUT

OH

Cycle Skip Threshold Voltage I
Cycle Skip Charge Current (V

= 0 V) I

CSKIP

I

LIM1

t

ILIM

LIM2

CSKIP

0.44 0.48 0.52 V

- 90 150 ns

0.54 0.57 0.62 V

8.0 12.3 15 A

2. Guaranteed by design only.

11.5

V

7.4

­V

mA

21
25

17
19

A

50

100

mA

5.0

2.5

6.5

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6

NCP1560

ELECTRICAL CHARACTERISTICS (V

R

= 60.4 k, RFF = 432 k, for typical values TJ = 25°C, for min/max values, TJ = -40°C to 125°C, unless otherwise noted)

D

Characteristic

= 48 V, V

in

= 12 V, VEA = 2 V, RT = 101 k, C

AUX

= 6800 pF,

CSKIP

Symbol Min Typ Max Unit

OSCILLATOR

Frequency (RT = 101 k, Vin = 36 V)
TJ = 25°C
T

= -40°C to 125°C

J

Frequency (RT = 59 k, Vin = 36 V, VEA = 1 V)
TJ = 25°C
T

= -40°C to 125°C

J

f

OSC1

f

OSC2

285
280

456
444

300

480

MAXIMUM DUTY CYCLE COMPARATOR

Maximum Duty Cycle (Vin = 36 V, VEA = 3 V, TJ = 25°C)
RP = 0 , R

= open, R

R

P

MDP

MDP

= open

= open

Open Circuit Voltage V

DC

MAX

DCMAX

57
75

62
80

0.40 0.47 0.60 V

SOFT START

Charge Current (VSS = 1.0 V) I
Discharge Current (VSS = 5.0 V, V

= 3.7 V) I

UV/OV

SS(C)

SS(D)

5.0 6.2 7.4 A
20 52.5 - mA

PWM COMPARATOR

Input Resistance (V1 = 1.25 V, V2 = 1.50 V)

R

= (V2 - V1)/(I2 - I1)

IN(VEA)

Lower Input Threshold V
Delay to Output (from VOH to 0.5 VOH) t

R

IN(VEA)

EA(L)

PWM

8.0 22 60 k

0.3 0.7 0.9 V

- 200 - ns

5.0 V REFERENCE

Output Voltage (I
Load Regulation (I
Line Regulation (V

= 0 mA) V

REF

= 0 to 6 mA) V

REF

= 7.5 to 16 V) V

AUX

REF

REF(Load)

REF(Line)

4.9 5.0 5.1 V

- 10 50 mV

- 50 100 mV

CONTROL OUTPUTS

Output Voltage (I

Low State
High State

Overlap Delay (Vin = 36 V)
RD = 1 M

Leading
Trailing

R

= 60 k

D

Leading
Trailing

OUT

= 0 mA)

V

OL

V

OH

t

D

50
32

-

-

-

-

0.25

11.8

200
170

90
72

Drive Resistance (Vin = 15 V)

Sink (V

Source (V
Rise Time (CL = 100 pF, 10% to 90% of VOH) t
Fall Time (CL = 100 pF, 90% to 10% of VOH) t

= 0 V, V

EA

EA

OUT

= 3 V, V

= 2 V)

OUT

= 10 V)

R

SNK

R

SRC

on

off

20
50

40
90

- 30 - ns

- 12 - ns

kHz

315

-

320

kHz

504

-

516

%
66
85

V

-

­ns

-

-

130
130



80

170

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NCP1560

Typical Characteristics

12
11

START-UP

10

THRESHOLD

9

8
7

6

, AUXILIARY SUPPLY VOLTAGE (V)

AUX

5

V

MINIMUM

OPERATING

THRESHOLD

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 3. Auxiliary Supply Voltage Thresholds

versus Junction T emperature

17.5

17.0

16.5

16.0

15.5

15.0

CURRENT (mA)

14.5

, START-UP CIRCUIT OUTPUT

14.0

START

I

13.5

V

, AUXILIARY SUPPLY VOLTAGE (V) Vin, LINE VOLTAGE (V)

AUX

Figure 5. Start-up Circuit Output Current

versus Auxiliary Supply Voltage

1251007550250-25-50

Vin = 48 V

20
19

Vin = 48 V

18
17

V

= 0 V

16

AUX

15
14
13

CURRENT (mA)

, START-UP CIRCUIT OUTPUT

12

V

AUX

= V

AUX(on)

- 0.2 V

11

START

I

150 150

10

1251007550250-25-50

Figure 4. Start-up Circuit Output Current

versus Junction T emperature

20

16

12

8

TJ = -40°C

TJ = 25°C

TJ = 125°C

CURRENT (mA)

4

, START-UP CIRCUIT OUTPUT

START

I

0

121086420

V

AUX

= V

AUX(on)

- 0.2 V

1501251007550250

Figure 6. Start-up Circuit Output Current

versus Line V oltage

40

V

= 12 V

AUX

35
30
25
20
15

, START-UP CIRCUIT OFF-

10

5

STATE LEAKAGE CURRENT (A)

START(off)

I

0

Figure 7. Start-up Circuit Off-State Leakage

Current versus Line Voltage

4.0

TJ = -40°C

3.5

V

AUX

3.0
VEA = 0 V

TJ = 25°C

2.5

2.0

TJ = 125°C

1.5

V

UV/OV

= 0 V

1.0

0.5

, AUXILIARY SUPPLY CURRENT (mA)

0

AUX

I

1501251007550250

Vin, LINE VOLTAGE (V) TJ, JUNCTION TEMPERATURE (°C)

Figure 8. Auxiliary Supply Current versus

Junction Temperature

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8

= 12 V

1251007550250-25-50

150

NCP1560

Typical Characteristics

7

f

6

5

4

3
2

, OPERATING AUXILIARY

SUPPLY CURRENT (mA)

1

AUX3

I

0

OSC

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 9. Operating Auxiliary Supply Current

versus Junction T emperature

160

150

140

130

120

, UV/OV THRESHOLD

110

UV/OV(H)

100

VOLTAGE HYSTERESIS (mV)

V

90

TJ, JUNCTION TEMPERATURE (°C)

Figure 11. Line Under/Over Voltage Thresholds

Hysteresis versus Junction T emperature

120

115

110
105
100

, CURRENT LIMIT

ILIM

t

PROPAGATION DELAY (ns)

V

= 12 V

AUX

Measured from VOH to 0.5 V

95
90
85
80
75

70

TJ, JUNCTION TEMPERATURE (°C)

Figure 13. Current Limit Propagation Delay

versus Junction T emperature

= 440 kHz

OV HYSTERESIS

UV HYSTERESIS

OH

f

OSC

f

OSC

7550

V

= 12 V

AUX

DC  50%

= 300 kHz

= 87 kHz

1251007550250-25-50

4.0

3.5

3.0

2.5

2.0

1.5

, UV/OV VOLTAGE (V)

1.0

UV/OV

V

0.5

150 150

0

OV THRESHOLD

UV THRESHOLD

Figure 10. Line Under/Overvoltage Thresholds

versus Junction T emperature

600
575
550
525
500
475
450
425

, CURRENT LIMIT THRESHOLDS (mV)

400

LIM

I

150125100250-25-50

CYCLE SKIP

CYCLE BY CYCLE

TJ, JUNCTION TEMPERATURE (°C)

Figure 12. Current Limit Thresholds versus

Junction Temperature

450
400
350
300
250
200
150
100

, OSCILLATOR FREQUENCY (kHz)

50

osc

f

1251007550250-25-50

150

0

TJ, JUNCTION TEMPERATURE (°C)

RT = 68 k

RT = 101 k

RT = 390 k

Figure 14. Oscillator Frequency versus

Junction Temperature

1251007550250-25-50

150

1251007550250-25-50

1251007550250-25-50

150

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NCP1560

Typical Characteristics

315

310

305

300

295

290

, OSCILLATOR FREQUENCY (kHz)

osc

f

285

T

, JUNCTION TEMPERATURE (°C)

J

Figure 15. Oscillator Frequency versus

Junction Temperature

19
18

17
16
15
14
13
12
11
10

9

FEEDFORWARD INTERNAL RESISTANCE (k)

TJ, JUNCTION TEMPERATURE (°C) IFF, FEEDFORWARD CURRENT (A)

Figure 17. Feedforward Internal Resistance

versus Junction T emperature

100

90

RP = OPEN, R

80

70

RP = 0 , R

, MAXIMUM DUTY CYCLE (%)

60

MAX

DC

50

TJ, JUNCTION TEMPERATURE (°C)

MDP

Figure 19. Maximum Duty Cycle versus

Junction Temperature

5025

= OPEN

MDP

= OPEN

5025

RT = 101 k

1251007550250-25-50

Vin = 36 V
R

= 432 k

FF

600

500

400

300

200

100

, OSCILLATOR FREQUENCY (kHz)

osc

f

0

150

Figure 16. Oscillator Frequency versus

90
80
70
60
50
40
30

, MAXIMUM DUTY CYCLE (%)

20

MAX

10

DC

0

150125100750-25-50

TJ = 125°C

Figure 18. Maximum Duty Cycle versus

7.0

6.5

6.0

5.5

5.0

4.5

4.0

3.5

, SOFT START CHARGE CURRENT (A)

3.0

150125100750-25-50

SS(C)

I

DISCHARGE

Figure 20. Soft Start Charge/Discharge

Currents versus Junction Temperature

TJ = 25°C
DC  50%

RT, TIMING RESISTOR (k)

Timing Resistor

Vin = 36 V
V

= 3.0 V

EA

V

DCMAX

TJ = -40°C

375300

Feedforward Current

CHARGE

TJ, JUNCTION TEMPERATURE (°C)

350

= 0 V

1251007550250-25-50

40030025020015010050

525450225150750

I

SS(D)

70

, SOFT START DISCHARGE CURRENT (mA)
65
60

55
50
45
40
35

30

150

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10

NCP1560

Typical Characteristics

50

40

30

20

INPUT RESISTANCE (k)

EA

, V

10

IN(VEA)

0

R

5.03

5.01

4.99

4.97

4.95

, REFERENCE VOLTAGE (V)

REF

V

4.93

225

200

175

-25 1257525
TJ, JUNCTION TEMPERATURE (°C)

Figure 21. VEA Input Resistance versus

Junction Temperature

I

= 0 mA

REF

I

= 6 mA

REF

1251007550250-25-50

TJ, JUNCTION TEMPERATURE (°C)

Figure 23. Reference Voltage versus Junction

Temperature

TJ = 25°C

LEADING

TRAILING

0.85

0.75

0.65

0.55

INPUT THRESHOLD (V)

, PWM COMPARATOR LOWER

0.45

EA(L)

V

0.35

150100500-50

350

300

250

200

150

100

50

, OUTPUTS OVERLAP DELAY (ns)

D

t

0

150

200

160

50 75

TJ, JUNCTION TEMPERATURE (°C)

Figure 22. PWM Comparator Lower Input

Threshold versus Junction Temperature

RD = 1 M, LEADING

RD = 60 k, LEADING

7550250-25-50

T

, JUNCTION TEMPERATURE (°C)

J

Figure 24. Outputs Overlap Delay versus

Junction Temperature

Vin = 36 V
V

= 12 V

AUX

= 100 k

R

MDP

150125100250-25-50

150125100

150

125

100

, OUTPUTS OVERLAP DELAY (ns)

D

t

75
50

RD, DELAY RESISTOR (k)

Figure 25. Outputs Overlap Delay versus

Delay Resistor

120

80

40

OUTPUTS DRIVE RESISTANCE ()

10008006004002000

0

SNK/SRC

R

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11

R

SRC (VEA

R

SNK (VEA

= 0 V, V

= 3 V, V

OUT

OUT

= 10 V)

= 2 V)

50 75

T

, JUNCTION TEMPERATURE (°C)

J

Figure 26. Outputs Drive Resistance Voltage

versus Junction T emperature

150125100250-25-50

NCP1560

Typical Characteristics

80

Measured from 10% to 90% of V

70

V

= 12 V

AUX

60
50
40
30
20

, OUTPUTS RISE TIME (ns)

on

t

10

0

CL, LOAD CAPACITANCE (pF)

TJ = 25°C

OH

TJ = 125°C

TJ = -40°C

1751257525

Figure 27. Outputs Rise Time versus Load

Capacitance

DETAILED OPERATING DESCRIPTION

The NCP1560 PWM controller contains all the features
and flexibility needed for implementation of Voltage-Mode
Control in high performance DC/DC converters. This
device cost effectively reduces system part count with the
inclusion of a high voltage start-up regulator. The NCP1560
provides two control outputs. Output 1 controls the main
switch of a forward or flyback topology. Output 2 has an
adjustable overlap delay, which can be used to control an
active clamp/reset switch, a synchronous rectifier switch, or
both. Other distinctive features include: two mode
overcurrent protection, line under/over voltage lockout, fast
line feedforward, soft start and a maximum duty cycle limit.
The Functional Block Diagram is shown in Figure 2.

The features included in the NCP1560 provide all the
advantages of Current-Mode Control, fast line feedforward,
and cycle by cycle current limit. It eliminates the
disadvantages of low power jitter, slope compensation and
noise susceptibility.

High Voltage Start-up Regulator

The NCP1560 contains an internal high voltage start-up
regulator that eliminates the need for external start-up
components. In addition, this regulator increases the
efficiency of the supply as it uses no power when in the
normal mode of operation, but instead uses power supplied
by an auxiliary winding.

The start-up regulator c onsists o f a c onstant c urrent s ource
that supplies current from the input line voltage (V
capacitor on the V
typically 13.8 mA. Once V

AUX

pin (C

AUX

). The start-up current is

AUX

reaches 11 V, the start- up

regulator turns O FF a nd t he o utputs a re e nabled. W hen V

) to the

in

AUX

reaches 7 V, the outputs are disabled and the start- up
regulator turns ON. This “ 7-11” mode o f o peration i s known
as Dynamic Self Supply ( DSS). The V

pin can be biased

AUX

externally above 7 V once the outputs are enabled to prevent

200150100500

35

Measured from 90% to 10% of V

30

V

= 12 V

AUX

25

20

15

10

, OUTPUTS FALL TIME (ns)

off

5

t

0

CL, LOAD CAPACITANCE (pF)

OH

TJ = 125°C

TJ = 25°C

TJ = -40°C

1751257525

200150100500

Figure 28. Outputs Fall Time versus Load

Capacitance

the start-up regulator from turning ON. It is recommended
to bias the V

pin using an auxiliary supply generated out

AUX

of an auxiliary winding from the power transformer. An
independent voltage supply can also be used. However, if
V

is biased before the outputs are enabled or while a

AUX

fault is present, the One Shot Pulse Generator (Figure 2) will
not be enabled and the outputs will remain OFF.

As the D SS s ources c urrent t o t he V

be placed between C

and the auxiliary supply as shown

AUX

in Figure 29. This will allow the NCP1560 to charge C

pin, a diode s hould

AUX

AUX

while preventing t he start-up regulator f rom s ourcing c urrent
into the auxiliary supply.

I

V

in

13.8 mA

Disable

V

AUX

I

AUX

START

Figure 29. Recommended V

C

AUXIsupply

To auxiliary supply

Configuration

AUX

Power to the controller while operating in the self-bias or
DSS mode is provided by C
sized such that a V

AUX

. Therefore, C

AUX

AUX

must be

voltage greater than 7 V is
maintained while the outputs are switching and the
converter reaches regulation. Also, the V

discharge time

AUX

(from 11 V t o 7 V) must be greater that the soft start charge
period to assure the converter turns ON.

The start-up circuit is rated at a maximum voltage of
150 V. If the device operates in the DSS mode, power
dissipation should be controlled to avoid exceeding the
maximum power dissipation of the controller.

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12

NCP1560

Line Under/Over Voltage Shutdown

The NCP1560 incorporates a line under/over voltage
shutdown (UV/OV) circuit. The under voltage (UV)
threshold is 1.52 V and the over voltage threshold (OV) is

3.61 V, for a ratio of 1:2.4.

The UV/OV circuit can be biased using an external
resistor divider from the input line. The resistor divider must

V

AUX(on)

V

AUX

V

AUX(off)

0 V

V

UV/OV Voltage

OV

V

UV

0 V

OUT2

be sized to enable the controller once V

is within the

in

required operating range. If the UV or OV threshold is
reached, the soft start capacitor is discharged, and the
outputs are immediately disabled with no overlap delay as
shown in Figure 30. Also, if an UV condition is detected, the

5.0 V Reference Supply is disabled.

UV or OV Fault

Propagation delay to
outputs (t

UV

or tOV)

0 V

OUT1

0 V

Figure 30. UV/OV Fault Timing Diagram

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13

NCP1560

Once the UV or OV condition is removed and V

AUX

reaches 11 V, the controller initiates a soft start cycle.
Figure 31 shows the relationship between the UV/OV
voltage, the outputs and the soft start voltage.

V

AUX(on)

V

AUX

V

AUX(off)

0 V
2 V
0 V

0 V

OUT2

0 V

OUT1

0 V

UV/OV Voltage

Soft Start Voltage

The UV/OV pin can also be used to implement a remote
enable/disable function. Biasing the UV/OV pin below its
UV threshold disables the converter.

SOFT START

Figure 31. Soft Start Timing Diagram (Using Auxiliary Winding)

Feedforward Ramp Generator

The NCP1560 incorporates line feedforward (FF) to
compensate for changes in line voltage. A FF Ramp
proportional to V

is generated and compared to VEA. If the

in

line voltage changes, the FF Ramp slope changes
accordingly. The duty cycle will be adjusted immediately
instead of waiting for the line voltage change to propagate
around the system and be reflected back on VEA.

A resistor between V

and the FF pin (RFF) sets the

in

feedforward current (IFF). The FF Ramp is generated by
charging an internal 10 pF capacitor (CFF) with a constant
current proportional to IFF. The FF Ramp is finished
(capacitor is discharged) once the Oscillator Ramp reaches

2.0 V. Please refer to Figure 2 for a functional drawing of the
Feedforward Ramp generator.

I

is usually a few hundred microamps, depending on the

FF

operating frequency and the required duty cycle. If the
operating frequency and maximum duty cycle are known,
I

is calculated using the equation below:

FF

CFF V

I



where V

FF

is the voltage on the inverting input of the

DC(inv)

6.7 k  t

Max DC Comparator and t

DC(inv)

on(max)

 125 k

on(max)

is the maximum ON time.

Figure 18 shows the relationship between IFF and DC

MAX

For example, if a system is designed to operate at 300 kHz,
with a 60% maximum duty cycle at 36 V, the DC
be grounded and I

T 

t

on(max)

I

FF

is calculated as follows:

FF

1

f

 DC

CFF V



10 pF 0.888 V  125 k



1



300 kHz

MAX

6.7 k  t

6.7 k  2.0 s

 3.33 s

 T  0.6 3.33 s  2.0 s

DC(inv)

 125 k

on(max)

 82.8 A

MAX

pin can

As the minimum line voltage is 36 V, the required

feedforward resistor is calculated using the equation below:

V



I

in

FF

 12.0 k 

R

FF

36 V

82.8 A

 12.0 k  434 k

From the above calculations it can be observed that IFF is
controlled predominantly by the value of RFF, as the
resistance seen into the FF pin is only 12 k. If a tight
maximum duty cycle control over temperature is required,
RFF should have a low thermal coefficient.

.

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NCP1560

Current Limit

The NCP1560 has two over current protection modes,
cycle by cycle and cycle skip. It allows the NCP1560 to
handle momentary and hard shorts differently for the best
tradeoff in performance and safety. The outputs are disabled
typically 90 ns after a current limit fault is detected.

The cycle by cycle mode terminates the conduction cycle
(reducing the duty cycle) if the voltage on the CS pin
exceeds 0.48 V. The cycle skip mode is enabled if the voltage
on the CS pin reaches 0.57 V. Once a cycle skip fault is
detected, the outputs are disabled, the soft start and cycle
skip capacitors are discharged, and the cycle skip period
(T

CSKIP

) commences.

V

AUX(on)

V

AUX

V

AUX(off)

0 V

OUT2

NORMAL

OPERATION

I

LIM1

I

LIM2

RESET

The cycle skip period is set by an external capacitor

(C

). Once a cycle skip fault is detected, the cycle skip

CSKIP

capacitor is discharged followed by a charge cycle. The
charge current is 12.3 A. The cycle skip period ends when
the voltage on the cycle skip capacitor reaches 2.0 V. The
cycle skip capacitor is calculated using the equation below:

T

C

CSKIP

CSKIP  12.3 A



2V

Using the above equation, a cycle skip period of 11.0 s
requires a cycle skip capacitor of 68 pF. The differences
between the cycle by cycle and cycle skip modes are
observed in Figure 32.

NORMAL

SOFT START

OPERATION

0 V

OUT1

0 V

I

LIM2

I

LIM1

CS Voltage

0 V

T

CSKIP

Cycle Skip

0 V

Once the cycle skip period is complete and V

Voltage

Figure 32. Over Current Faults Timing Diagram

reaches

AUX

11 V, a soft start sequence commences. The possible
minimum OFF time is set by C

. However, the actual

CSKIP

OFF time is generally greater than the cycle skip period
because it is the cycle skip period added to the time it takes
V

to reach 11 V.

AUX

Oscillator

The NCP1560 oscillator frequency is set by a single
external resistor connected between the RT pin and GND.
The oscillator is designed to operate up to 500 kHz.

The voltage on the RT pin is laser trim adjusted during
manufacturing to 1.3 V for an RT of 101 k. A current set
by R

generates an Oscillator Ramp by charging an internal

T

10 pF capacitor as shown in Figure 2. The period ends
(capacitor is discharged) once the Oscillator Ramp reaches

2.0 V. If RT increases, the current and the Oscillator Ramp
slope decrease, thus reducing the frequency. I f RT decreases,
the opposite effect is obtained. Figure 16 shows the
relationship between R

and the oscillator frequency.

T

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15

NCP1560

Maximum Duty Cycle

A dedicated internal comparator limits the maximum ON
time of OUT1 by comparing the FF Ramp to V
FF Ramp voltage exceeds V

, the output of the Max

DC(inv)

DC(inv)

. If the

DC Comparator goes high. This will reset the Output Latch,
thus turning OFF the outputs and limiting the duty cycle.

Duty cycle is defined as:

t

on

DC 

 ton f

T

Therefore, the maximum ON time can be set to yield the
desired DC if the operating frequency is known. The
maximum ON time is set by adjusting the FF Ramp to reach
V

in a time equal to t

DC(inv)

as shown in Figure 33.

on(max)

The maximum ON time should be set for the minimum line
voltage. As line voltage increases, the slope of the FF Ramp
increases. This reduces the duty cycle below DC

MAX

, which
is a desirable feature as the duty cycle is inversely
proportional to line voltage.

Oscillator Ramp

2 V

0 V

T

5.0 V Reference

The NCP1560 includes a precision 5.0 V reference output.

The reference output is biased directly from V

AUX

and it can
supply up to 6 mA. Load regulation is 50 mV and line
regulation is 100 mV within the specified operating range.

It is recommended to bypass the reference output with a

0.1 F ceramic capacitor. The reference output is disabled
when an UV fault is present.

PWM Comparator

The output of an external error amplifier is compared to
the FF Ramp by means of the PWM Comparator. The
external error amplifier drives the V

0.7 V offset between the V

EA

input. There is a

EA

input and the PWM
Comparator inverting input. The offset is provided by a
series diode and resistor. If the voltage on the VEA input is
below 0.7 V, the outputs are disabled.

The PWM Comparator controls the duty cycle by turning
OFF the outputs once the FF Ramp voltage exceeds the
offset V
DC from 0% to DC

where, V

voltage. The VEA range required to control the

EA

is given by the equation below:

MAX

I

FF  DC

V

EA(L)

 V

is the PWM comparator lower input

EA(L)

EA





186.56 pf f

 V

EA(L)



threshold.

FF Ramp

0 V

t

on(max)

Figure 33. Maximum ON Time Limit Waveforms

V

DC(inv)

An internal resistor divider from a 2.0 V reference is used

to set V

0.88 V. If the pin is floating, V
equivalent to 60% or 80% of a 1.5 V FF Ramp. V

DC(inv)

. If the DC

pin is grounded, V

MAX

DC(inv)

is

DC(inv)

is 1.19 V. This is

can

DC(inv)

be adjusted to other values by using an external resistor
network on the DC

pin. For example, if the minimum

MAX

line voltage is 36 V, RFF is 434 k, operating frequency is
300 kHz and a maximum duty cycle of 70% is required,
V

is calculated as follows:

DC(inv)

V

DC(inv)

V

DC(inv)

88.2 A 6.7 k  2.33 s



IFF 6.7 k  t



CFF 125 k

10 pF 125 k

on(max)

1.10 V

This can be achieved by connecting a 45.3 k resistor

from the DC

pin to GND. The maximum duty cycle

MAX

limit can be disabled connecting a 100 k resistor between
the DC

MAX

and V

REF

pins.

Soft Start

Soft start (SS) allows the converter to gradually reach
steady state operation, thus reducing start-up stress and
surges on the system. The duty cycle is limited during a soft
start sequence by comparing the Oscillator Ramp to the SS
voltage (V

) by means of the Soft Start Comparator.

SS

A 6.2 A current source starts to charge the capacitor on
the SS pin once faults are removed and V

reaches 11 V.

AUX

The Soft Start Comparator controls the duty cycle while the
SS voltage is below 2.0 V . Once VSS reaches 2.0 V, it exceeds
the Oscillator Ramp voltage and the Soft Start Comparator
does not limit the duty cycle. Figure 34 shows the
relationship between the outputs duty cycle and the soft start
voltage.

Oscillator
Ramp

OUT2

OUT1

V

SS

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16

Figure 34. Soft Start Timing Diagram

NCP1560

If the soft start period is too long, V

may discharge to

AUX

7 V before the converter output is completely in regulation
causing the outputs to be disabled. If the converter output is
not completely discharged when the outputs are re-enabled,
the converter will eventually reach regulation exhibiting a
non-monotonic start-up behavior. But, if the converter
output is completely discharged when the outputs are
re-enabled, the cycle may repeat and the converter will not
start.

In the event of an UV, OV , or cycle skip fault, the soft start
capacitor is discharged. Once the fault is removed, a soft
start cycle commences. The soft start steady state voltage is
approximately 4.1 V.

Control Outputs

The NCP1560 has two in-phase control outputs, OUT1
and OUT2, with adjustable overlap delay (t

). OUT2

D

precedes OUT1 during a low to high transition and OUT1
precedes OUT2 at any high to low transition. Figure 35
shows the relationship between OUT1 and OUT2.

tD (Trailing)tD (Leading)

OUT1

OUT2

Figure 35. Control Outputs Timing Diagram

Generally, OUT1 controls the main switching element.
Output 2, once inverted, can control a synchronous rectifier.
The overlap delay prevents simultaneous conduction.
Output 2 can also be used to control an active clamp reset.

Once V

reaches 11 V, the internal start-up circuit is

AUX

disabled and the One Shot Pulse Generator is enabled. If no
faults are present, the outputs turn ON. Otherwise, the
outputs remain OFF until the fault is removed and V

AUX

reaches 11 V again.

The control outputs are biased from V

. The outputs

AUX

can supply up to 10 mA each and their high state voltage is
usually 0.2 V below V

. Therefore, the auxiliary supply

AUX

voltage should not exceed the maximum input voltage of the
driver stage.

If the control outputs need to drive a large capacitive load,
a driver should be used between the NCP1560 and the load.
ON Semiconductor’s MC33152 is a good selection for an
integrated driver. Figures 27 and 28 shows the relationship
between the output’s rise and fall times vs capacitive load.

Time Delay

The overlap delay between the outputs is set connecting
a resistor (R

) between the tD and V

D

pins. A minimum

REF

overlap delay of 80 ns is obtained when RD is 60 k. If R
is not present, the delay is 200 ns.

The output duty cycle can be adjusted from 0% to 85%
selecting appropriate values of RFF and V

DC(inv)

. It should
be noted that the overlap delay may cause OUT2 to reach
100% duty cycle. Therefore, if OUT2 is used, the maximum
duty cycle of OUT2 needs to be kept below 100%. The
maximum overlap delay, t

, depends on the maximum

D(max)

duty cycle and frequency of operation. The maximum
overlap delay is calculated using the equation below.

t

D(max)

(1  DC)



ƒ

2

For example, if the converter operates at a frequency of
300 kHz with a maximum duty cycle of 80%, the maximum
allowed overlap delay is 333 ns. However, this is a
theoretical limit and variations over the complete operating
range should be considered when selecting the overlap
delay.

Additional Information

A 100 W DC-DC converter for telecom systems was
designed and implemented using the NCP1560. The
converter design is discussed in Application Note
AND8105/D.

D

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17

NCP1560

PACKAGE DIMENSIONS

SO-16

D SUFFIX

CASE 751B-05

ISSUE J

-T-

-A-

16 9

-B-

18

G

K

C

SEATING

PLANE

D

16 PL

0.25 (0.010) A

M

S

B

T

S

8 PLP

0.25 (0.010) B

M

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

M

S

X 45

R



F

J

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019

F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7



P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

INCHESMILLIMETERS

The product described herein (NCP1560) may be covered by one or more U.S. patents. There may be other patents pending.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

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For additional information, please contact your local
Sales Representative.

NCP1560/D

18