Page 1
NCP1532
Dual Output Step-Down
Converter 2.25 MHz
High-Efficiency, Out of
Phase Operation, Low
Quiescent Current, Source
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up to 1.6 A
The NCP1532 dual step down DCDC converter is a monolithic
integrated circuit dedicated to supply core and I/O voltages of new
multimedia design in portable applications powered from 1−cell
Li−ion or 3 cell Alkaline / NiCd / NiMH batteries.
Both channels are externally adjustable from 0.9 V to 3.3 V and can
source totally up to 1.6 A, 1.0 A maximum per channel. Converters are
running at 2.25 MHz switching frequency which reduces component
size by allowing the use of small inductor (down to 1 mH) and
capacitors and operates 180° out of phase to reduce large amount of
current demand on the battery. Automatic switching PWM/PFM mode
and synchronous rectification offer improved system efficiency. The
device can also operate into fixed frequency PWM mode for low noise
applications where low ripple and good load transients are required.
Additional features include integrated soft−start, cycle−by−cycle
current limit and thermal shutdown protection. The device can also be
synchronized to an external clock signal in the range of 2.25 MHz.
The NCP1532 is available in a space saving, ultra low profile
3x3 x 0.55 mm 10 pin mDFN package.
Features
• Up to 97% Efficiency
• 50 mA Quiescent Current
• Synchronous Rectification for Higher Efficiency
• 2.25 MHz Switching Frequency, 180° Out of Phase
• Sources up to 1.6 A, 1.0 A Maximum per Channel
• Adjustable Output Voltage from 0.9 V to 3.3 V
• Mode Selection Pin: Eco Mode or Low Noise Mode
• 2.7 V to 5.5 V Input Voltage Range
• Thermal Limit Protection
• Short Circuit Protection
• All pins are fully ESD Protected
• This is a Pb−Free Device
Typical Applications
• Cellular Phones, Smart Phones and PDAs
• Digital Still Cameras
• MP3 Players and Portable Audio Systems
• Wireless and DSL Modems
• Portable Equipment
MARKING
DIAGRAM
UDFN10
MU SUFFIX
CASE 506AT
Aa = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
Device Package Shipping
NCP1532MUAATXG UDFN10
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
(may be 1 or 2 characters)
PIN CONNECTION
FB1
110
EN1
2
VIN
3
4
SW1
GND
5
(Top View)
UDFN10
ORDERING INFORMATION
(Pb−Free)
9
8
7
6
1532
AA
AaLYWG
G
FB2
EN2
POR
SW2
MODE/
SYNC
3000 /
Tape & Reel
†
© Semiconductor Components Industries, LLC, 2011
October, 2011 − Rev. 6
1 Publication Order Number:
NCP1532/D
Page 2
NCP1532
VIN
ONOFF
2.25 MHz Range
ONOFF
ONOFF
NOTE: Exposed pad of UDFN10 package − named pin11 − must be connected to system ground.
3
VIN
5
GND
2
EN1
6
MODE/SYNC
9
EN2
FB1
FB2
10
4
18pF
1
8
7
18pF
SW1
11
POR
SW2
2.2mH
2.2mH
VOUT1
10mF
POR
VOUT2
10mF
Figure 1. NCP1532 Typical Application
PIN FUNCTION DESCRIPTION
Pin Pin Name Type Description
1 FB1 Analog Input Feedback voltage from the output 1. This is the input to the error amplifier.
2 EN1 Digital Input Enable for converter 1. This pin is active HIGH (higher than 1.2 V) and is turned off by
3 VIN Analog / Power
Input
4 SW1 Analog Output Connection from power MOSFETs of output 1 to the Inductor.
5 GND Analog Ground This pin is the GROUND reference for the analog section of the IC. The pin must be
6 MODE/SYNC Digital Input Combination Mode Selection and Oscillator Synchronization. If this pin is LOW, the
7 SW2 Analog Output Connection from power MOSFETs of output 2 to the Inductor.
8 POR Digital Output Power On Reset. This is an open drain output. This output is shutting down when each
9 EN2 Digital Input Enable for converter 2. This pin is active HIGH (higher than 1.2 V) and is turned off by
10 FB2 Analog Input Feedback voltage from the output 2. This is the input to the error amplifier.
11 Exposed Pad Power Ground This pin is the GROUND reference for the NFET power stage of the IC. The pin must
logic LOW (lower than 0.4 V.
Do not leave this pin floating.
Power supply input for the PFET power stage, analog and digital blocks. The pin must
be decoupled to ground by a 10 mF ceramic capacitor.
connected to the system ground by 10 mF low ESR ceramic capacitor.
regulator runs in automatic switching PFM/PWM. With a HIGH level (equal or lower
Analog Input voltage), the converter runs in PWM mode only. This pin can be also synchronized to an external clock in the range of 2.25 MHz; in this case the device runs in
PWM mode only. Insert the clock before enabling the part is recommended to force
external synchronization. Do not let this pin floating.
Following rule is being used:
output voltages are less than 90% of their nominal values and goes high after 120 ms
when active outputs are within regulation. A pullup resistor around 500k should be
connected between POR and V
logic LOW (lower than 0.4 V). Do not let this pin floating.
be connected to the system ground and to both input and output capacitors.
”0”: Eco mode, automatic switching PFM/PWM, 180° out of phase.
“1”: Low noise, forced PWM mode, 180° out of phase.
”CLK”: External synchronization, forced PWM mode, 0° in phase.
, V
OUT1
or V
IN
depending on the supplied device.
OUT2
VIN or VOUT
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NCP1532
BLOCK DIAGRAM
FB1
EN1
VIN
SW1
GND
EA1
1
2
3
4
5
VREF VREF
Logic
Control
EA1 EA2
PVIN
AVIN AVIN
Q1
PWM/PFM
Q2
Control
UVLO
Thermal
Shutdown
Voltage
Reference
Oscillator
Ramp Generator
0° 180°
PWM/PFM
Control
Logic
Control
VIN
EA2
VIN
Q3
Q4
PVIN
10
9
8
7
6
FB2
EN2
POR
SW2
MODE/SYNC
ILIMIT ILIMIT
Figure 2. Simplified Block Diagram
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NCP1532
MAXIMUM RATINGS
Rating Symbol Value Unit
Minimum Voltage All Pins V
Maximum Voltage All Pins (Note 1) V
Maximum Voltage EN1, EN2, MODE V
Thermal Resistance Junction−to−Air (UDFN10 Package)
Thermal Resistance Using Recommended Board Layout (Note 8)
Operating Ambient Temperature Range (Notes 6 and 7) T
Storage Temperature Range T
Junction Operating Temperature (Notes 6 and 7) T
Latchup Current Maximum Rating TA = 85°C (Note 4) Other Pins L
ESD Withstand Voltage (Note 3)
Human Body Model
min
max
max
R
q
JA
A
stg
J
u
V
esd
Machine Model
Moisture Sensitivity Level (Note 5) MSL 1 per IPC
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at T
2. According JEDEC standard JESD22−A108B
3. This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM) per JEDEC standard: JESD22−A114
Machine Model (MM) per JEDEC standard: JESD22−A115
4. Latchup current maximum rating per JEDEC standard: JESD78.
5. JEDEC Standard: J−STD−020A.
6. In applications with high power dissipation (low V
considerations − thermal dissipation vias, traces or planes and PCB material − can significantly improve junction to air thermal resistance
(for more information, see design and layout consideration section). Environmental conditions such as ambient temperature Ta brings
R
q
JA
thermal limitation on maximum power dissipation allowed.
, high I
IN
), special care must be paid to thermal dissipation issues. Board design
OUT
The following formula gives calculation of maximum ambient temperature allowed by the application: T
Where
is the junction temperature,
T
J
is the maximum power dissipated by the device (worst case of the application), and R
P
d
resistance.
q
7. To prevent permanent thermal damages, this device include a thermal shutdown which engages at 180°C (typical).
8. Board recommended UDFN10 layout is described in Layout Considerations section.
−0.3 V
7.0 V
VIN + 0.3 V
200
°C/W
40
−40 to 85 °C
−55 to 150 °C
−40 to 150 °C
$100 mA
2.0
200
= 25°C
A
= T
A(max)
is the junction−to−ambient thermal
JA
J(max)
− (R
q
JA
kV
V
x Pd)
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NCP1532
ELECTRICAL CHARACTERISTICS
(Typical values are referenced to TA = +25°C, Minimum and Maximum values are referenced −40°C to +85°C ambient temperature,
unless otherwise noted, operating conditions V
Rating
INPUT VOLTAGE
Input Voltage Range
Quiescent Current,
No Switching, No Load
No Load
Standby Current EN1 = EN2 = GND I
Under Voltage Lockout VIN Falling V
Under Voltage Hysteresis V
ANALOG AND DIGITAL PIN
Positive Going Input High Voltage Threshold
Negative Going Input High Voltage Threshold EN1, EN2, MODE/SYNC V
Digital Threshold Hysteresis EN1, EN2, MODE/SYNC V
External Synchronization (Note 11)
Minimum
Maximum
POWER ON RESET (Note 9)
Power On Reset Threshold
Power On Reset Hysteresis V
Power On Reset Delay (See Page 12) T
OUTPUT PERFORMANCES
Feedback Voltage Threshold
Minimum Output Voltage V
Maximum Output Voltage V
Output Voltage Accuracy (Note 10) Room Temperature
Output Voltage load regulation
NCP1532MUAATXG
Load transient response
Rise/Falltime 1 ms
Output Voltage Line Regulation
Load = 100 mA
Line Transient Response
Load = 100 mA
Output Voltage Ripple I
Soft−Start Time Time from EN to 90% of Output
Switching Frequency F
Duty Cycle D − − 100 %
= 3.6 V, V
IN
OUT1
= V
= 1.2 V, unless otherwise noted).
OUT2
Conditions Symbol Min Typ Max Unit
MODE/SYNC = GND I
EN1, EN2, MODE/SYNC V
MODE/SYNC F
V
Falling
OUT
FB1, FB2 V
Overtemperature Range
Overtemperature
Load = 100 mA to 600 mA
10 mA to 100 mA load step
(PFM to PWM mode)
200 mA to 600 mA load step
(PWM to PWM mode)
VIN = 2.7 V to 5.5 V V
3.6 V to 3.2 V Line Step
(Falltime = 50 ms)
= 0 mA
OUT
I
= 300 mA
OUT
Voltage
V
STB
UVLO
UVLOH
HYS
SYNC
V
PORT
PORH
POR
OUT
OUT
DV
V
LOADR
V
LOADT
LINER
V
LINET
V
RIPPLE
t
START
IN
Q
IH
IL
FB
OUT
SW
2.7 − 5.5 V
−
−
50
60
70
−
− 0.3 1.0
2.2 2.4 2.55 V
− 100 − mV
1.2 − − V
− − 0.4 V
− 100 − mV
MHz
−
−
1.8
3.0
−
−
− 89% − V
− 3% − V
− 116 − ms
− 0.6 − V
− 0.9 − V
− 3.3 − V
−
−3%
$1%
$2%−+3%
− −0.6 −
−
−
40
85
−
−
− 0.05 − %
− 6.0 − mV
−
−
8.0
3.0
−
mV
−
− 230 350
1.8 2.25 2.7 MHz
mA
mA
%
%
mV
PP
PP
ms
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NCP1532
ELECTRICAL CHARACTERISTICS
(Typical values are referenced to TA = +25°C, Minimum and Maximum values are referenced −40°C to +85°C ambient temperature,
unless otherwise noted, operating conditions V
Rating UnitMaxTypMinSymbolConditions
POWER SWITCHES
High−Side MOSFET On−Resistance
Low−Side MOSFET On−Resistance R
High−Side MOSFET Leakage Current I
Low−Side MOSFET Leakage Current I
PROTECTION
DC−DC Short Circuit Protection
Thermal Shutdown Threshold T
Thermal Shutdown Hysteresis T
9. Refer to Power On Reset section for more information.
10.The overall output voltage tolerance depends upon the accuracy of the external resistor (R1 and R2).
11.Guaranteed by design.
= 3.6 V, V
IN
OUT1
= V
= 1.2 V, unless otherwise noted).
OUT2
Peak Inductor Current I
R
ONHS
ONLS
LEAKHS
LEAKLS
PK
SD
SDH
− 400 −
− 300 −
− 0.05 −
− 0.01 −
1.2 1.6 − A
− 180 − °C
− 40 − °C
mW
mW
mA
mA
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TABLE OF GRAPHS
h
I
q ON
I
q OFF
F
SW
V
LOADR
V
LOADT
V
LINER
t
START
I
PK
V
UVLO
VIL, V
Efficiency vs. Output Current 3, 4, 5, 6, 7, 8
Quiescent Current, PFM no load vs. Input Voltage 11
Standby Current, EN Low vs. Input Voltage 10
Switching Frequency vs. Ambient Temperature 16
Load Regulation vs. Load Current 13
Load Transient Response 14, 15
Line Regulation vs. Output Current 12
Soft Start 18
Short Circuit Protection 19
Under Voltage Lockout Threshold vs. Ambient Temperature 20
Enable Threshold vs. Ambient Temperature 21
IH
NCP1532
TYPICAL CHARACTERISTICS FOR STEP DOWN CONVERTER FIGURE
1000
950
900
850
800
750
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
0
Iout1 (mA)
50
100
150
200
250
300
350
400
450
500
550
600
650
700
750
Iout2 (mA)
800
850
900
950
Eff (%)
0.9−0.95
0.85−0.9
0.8−0.85
0.75−0.8
0.7−0.75
1000
Figure 3. Efficiency vs. Output Current (VIN = 3.6 V, V
MODE/SYNC Pin = GND
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OUT1
= 1.8 V, V
= 1.8 V, Temperature = 255C)
OUT2
Page 8
NCP1532
100
90
80
70
60
50
40
EFFICIENCY (%)
PFM
30
20
PWM
10
0
0 100 200 300 400 500 600
I
, OUTPUT CURRENT (mA)
OUT1
Figure 4. Efficiency vs. Output Current
100
95
90
85
80
75
70
65
60
EFFICIENCY (%)
55
50
45
40
0 1000800600400200
= 3.6 V, V
V
IN
I
, OUTPUT CURRENT (mA)
OUT1
= 1.2 V, EN2 = GND
OUT1
25°C
−40°C
85°C
Figure 6. Efficiency vs. Output Current
V
= 3.6 V, V
IN
= 1.2 V, EN2 = GND,
OUT1
Temperature = 255C
100
95
90
85
80
75
70
65
60
EFFICIENCY (%)
55
50
45
40
0 1000800600400200
I
, OUTPUT CURRENT (mA)
OUT1
V
V
OUT
OUT
= 3.3 V
= 1.2 V
Figure 8. Efficiency vs. Output Current
V
= 3.6 V, EN2 = GND, Temperature = 255C
IN
100
90
80
70
60
50
40
EFFICIENCY (%)
30
20
10
0
1 10 100 1000
PFM
PWM
I
, OUTPUT CURRENT (mA)
OUT1
Figure 5. Efficiency vs. Output Current
100
95
90
85
80
75
70
65
60
EFFICIENCY (%)
55
50
45
40
0 1000800600400200
= 3.6 V, V
V
IN
I
, OUTPUT CURRENT (mA)
OUT1
= 1.2 V, EN2 = GND
OUT1
2.7 V
3.6 V
V
BAT
= 5.5 V
Figure 7. Efficiency vs. Output Current
V
= 1.2 V, EN2 = GND, Temperature = 255C
OUT1
100
99
98
97
96
95
94
93
EFFICIENCY (%)
92
91
90
5.5 3.03.54.04.55.0
VIN, INPUT VOLTAGE (V)
Figure 9. Maximum Efficiency vs. Input Voltage
V
OUT1
= V
OUT2
= 3.3 V I
OUT1
= I
OUT2
= 100 mA
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NCP1532
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
, STANDBY CURRENT (mA)
SB
I
0.1
0
2.5 5.04.54.03.53.0
V
, INPUT VOLTAGE (V)
IN
Figure 10. Standby Current vs. Input Voltage
V
= 3.6 V, EN1 = EN2 = GND,
IN
Temperature = 255C
20
15
10
5
85°C
0
5.5
60
55
50
45
40
35
30
, QUIESCENT CURRENT (mA)
25
q
I
20
2.5 5.04.54.03.53.0 5.5
Buck1 & Buck2
Buck1
VIN, INPUT VOLTAGE (V)
Buck2
Figure 11. Quiescent Current vs. Input Voltage
V
20
15
10
= 3.6 V, V
IN
5
0
FB1
= V
FB2
= 0.8 V
−40°C
−5
LINE REG (mV)
−10
−15
−20
5.2 3.23.74.24.7 2.7
25°C
−40°C
VIN, INPUT VOLTAGE (V)
Figure 12. Line Regulation
V
OUT1
= 1.2 V, I
= 100 mA, EN2 = GND
OUT1
−5
−10
LOAD REGULATION (mV)
−15
−20
0
25°C
200 400 600 800 1000
I
, OUTPUT CURRENT (mA)
OUT1
85°C
Figure 13. Load Regulation
V
= 3.6 V, V
IN
= 1.2 V, EN2 = GND
OUT1
Figure 14. Load Transient and Crosstalk,
= 3.6 V V
V
IN
200 mA to 600 mA V
I
= 600 mA, 8 mV Crosstalk
OUT2
OUT1
= 1.2 V, I
OUT2
from
OUT1
= 1.2 V,
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Figure 15. Load Transient and Crosstalk,
= 3.6 V V
V
IN
to 600 mA V
OUT1
OUT2
= 1.2 V, I
= 1.2 V, I
from 200 mA
OUT1
= 600 mA,
OUT2
8 mV Crosstalk
9
Page 10
5
4
3
2
1
0
, DRIFT (%)
−1
SW
F
−2
−3
−4
−5
−50 100250−25 125
TEMPERATURE (°C)
V
BAT
3.6 V
= 5.5 V
7550
Figure 16. Switching Frequency vs.
Temperature
NCP1532
2.7 V
Figure 17. External Synchronization,
F
= 2.93 MHz
sync
Figure 18. Soft−Start Typical Behavior
V
= 3.6 V, V
IN
I
OUT1
2.5
2.49
2.48
2.47
2.46
2.45
2.44
2.43
2.42
2.41
2.4
2.39
UVLO THRESHOLD (V)
2.38
2.37
2.36
2.35
−50 100250−25 1257550 −50 100250−25 1257550
TEMPERATURE (°C)
OUT1
= I
= V
= 600 mA
OUT2
UVLOrise
UVLOfall
OUT2
= 1.2 V,
Figure 20. UVLO Thresholds VIN = 3.6 V,
I
OUT1
= I
OUT2
= 2 mA
Figure 19. Current Peak Inductor Protection
V
= 3.6 V, V
IN
OUT1
= 1.2 V, I
EN2 = GND
1.2
1.1
1.0
0.9
0.8
0.7
0.6
ENABLE THRESHOLD (V)
0.5
0.4
TEMPERATURE (°C)
Figure 21. Enable Thresholds VIN = 3.6 V,
I
OUT1
= I
OUT1
V
IL
OUT2
= 2 mA
Short to GND,
V
IH
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NCP1532
DC/DC OPERATION DESCRIPTION
Detailed Description
The NCP1532 uses a constant frequency, current mode
step−down architecture. Both the main (P−channel
MOSFET) and synchronous (N−channel MOSFET)
switches are internal.
The output voltages are set by the external resistor divider
in the range of 0.9 V to 3.3 V and can source 1600 mA
totally depending on device option.
The NCP1532 works with two modes of operation;
PWM/PFM depending on the current required. In PWM
mode, the device can supply voltage with a tolerance of
$3% and 90% efficiency or better. Lighter load currents
cause the device to automatically switch into PFM mode to
reduce current consumption (I
= 50 mA) and extended
q
battery life. For low noise applications, by pulling the
MODE/SYNC Pin to V
, the device operates in PWM
IN
mode only.
Additional features include soft−start, undervoltage
protection, current overload protection and thermal
shutdown protection. As shown on Figure 1, only six
external components are required for implementation. The
part uses an internal reference voltage of 0.6 V. It is
recommended to keep NCP1532 in shutdown until the input
voltage is 2.7 V or higher. To reduce power demand on the
battery, the two DC−DC operates out of phase. This reduces
significantly spikes on V
line. Using external
in
synchronization, the two channels are working on same
signal phase. See MODE/SYNC section for more
information.
PWM Operating Mode
In this mode, the output voltage of the device is regulated
by modulating the on−time pulse width of the main switch
Q1 at a fixed 2.25 MHz frequency.
The switching of the PMOS Q1 is controlled by a flip−flop
driven by the internal oscillator and a comparator that
compares the error signal from an error amplifier with the
sum of the sensed current signal and compensation ramp.
The driver switches ON and OFF the upper side transistor
(Q1) and switches the lower side transistor in either ON state
or in current source mode.
At the beginning of each cycle, the main switch Q1 is
turned ON by the rising edge of the internal oscillator clock.
The inductor current ramps up until the sum of the current
sense signal and compensation ramp becomes higher than
the error amplifier’s voltage. Once this has occurred, the
PWM comparator resets the flip−flop, Q1 is turned OFF
while the synchronous switch Q2 is turned ON. Q2 replaces
the external Schottky diode to reduce the conduction loss
and improve the efficiency. To avoid overall power loss, a
certain amount of dead time is introduced to ensure Q1 is
completely turned OFF before Q2 is being turned ON.
Figure 22. PWM Switching Waveforms
V
= 3.6 V, V
IN
I
OUT1
PFM Operating Mode
= I
OUT1
OUT2
= V
OUT2
= 100 mA
= 1.2 V,
Under light load conditions, the NCP1532 enters in low
current PFM mode of operation to reduce power
consumption. The output regulation is implemented by
pulse frequency modulation. If the output voltage drops
below the threshold of PFM comparator a new cycle will be
initiated by the PFM comparator to turn on the switch Q1.
Q1 remains ON during the minimum on time of the structure
while Q2 is in its current source mode. The peak inductor
current depends upon the drop between input and output
voltage. After a short dead time delay where Q1 is switched
OFF, Q2 is turned in its ON state. The negative current
detector will detect when the inductor current drops below
zero and sends the signal to turn Q2 in current source mode
to prevent a too large deregulation of the output voltage.
When the output voltage falls below the threshold of the
PFM comparator, a new cycle starts immediately.
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NCP1532
Figure 23. PFM Switching Waveforms
V
= 3.6 V, V
IN
I
OUT1
Soft−Start
The NCP1532 uses soft−start to limit the inrush current
when the device is initially powered up or enabled.
Soft−start is implemented by gradually increasing the
reference voltage until it reaches the full reference voltage.
During startup, a pulsed current source charges the internal
soft−start capacitor to provide gradually increasing
reference voltage. When the voltage across the capacitor
ramps up to the nominal reference voltage, the pulsed
current source will be switched off and the reference voltage
will switch to the regular reference voltage.
Cycle−by−Cycle Current Limitation
From the block diagram (Figure 2), an I
used to realize cycle−by−cycle current limit protection. The
comparator compares the SW pin voltage with the reference
voltage, which is biased by a constant current. If the inductor
current reaches the limit, the ILIM comparator detects the
SW voltage falling below the reference voltage and releases
the signal to turn off the switch Q1. The cycle−by−cycle
current limit is set at 1600 mA (nom).
Low Dropout Operation
The NCP1532 offers a low input to output voltage
difference. The NCP1532 can operate at 100% duty cycle on
both channels.
In this mode the PMOS (Q1) remains completely ON. The
minimum input voltage to maintain regulation can be
calculated as:
VIN(min) + V
• V
• I
• R
• R
: Output Voltage (V)
OUT
: Maximum Output Current
OUT
: P−Channel Switch R
DS(on)
INDUCTOR
(max) ) (I
OUT
: Inductor Resistance (DCR)
OUT1
= I
= V
OUT2
OUT
= 1.2 V,
OUT2
= 0 mA
LIM
(R
DS(on)_RINDUCTOR
DS(on)
comparator is
)
(eq. 1)
Power On Reset
The Power On Reset (POR) is pulled low when either
active converter is out of 89% of their regulation. When
active outputs are in the range of regulation, a counter starts
to provide the POR signal with a delay equal to 262,144
clock cycles. The delay is depending on internal clock
frequency. If only one channel is active, POR runs only on
the active output until the other converter is disabled. When
this regulator becomes enabled, POR drops down until the
second output reaches its voltage range. A pullup resistor
(around 500 k) is needed to this open drain output. This
resistor may be connected to V
one regulator if the device supplied cannot accept V
IO. In the case of POR being tied to V
NCP1532 is off. In the case of POR being tied to V
or to an output voltage of
IN
on the
IN
, POR is high when
IN
OUT
, POR
is low when NCP1532 is off.
Figure 24. POR Behavior vs. V
OUT1
Leave the POR pin unconnected when not used.
Mode Selection and Frequency Synchronization
The MODE/SYNC pin is a multipurpose pin which
provides mode selection and frequency synchronization.
When this pin is connected to ground, auto−switching
PFM/PWM mode is selected which provides the best
efficiency at light load and quiescent current with a good
ripple compromise (less than 8 mV). Connecting this pin to
V
enables PWM mode of operation, which provides the
IN
best low noise solution, low ripple and low load transient
performance.
NCP1532 can also be synchronized to an external clock
signal in the range from internal switching frequency to
3.0 MHz. Lower frequency causes the part enters one time
in PFM/PWM mode, and the other time in PWM mode.
Insert the clock before enabling the part is recommended to
force external synchronization. This function allows
synchronizing NCP1532 with another switching device
such as the switching output of another DC to DC converter
forced in PWM mode. This decreases noise dispersion
generated by the converters.
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NCP1532
Undervoltage Lockout
The Input voltage VIN must reach 2.4 V (typ) before the
NCP1532 enables the DC/DC converter output to begin the
start up sequence (see soft−start section). The UVLO
threshold hysteresis is typically 100 mV.
Shutdown Mode
When the EN pin has applied voltage of less than 0.4 V,
the NCP1532 will be disabled. In shutdown mode, the
internal reference, oscillator and most of the control
circuitries are turned off. Therefore, the typical current
consumption will be 0.3 mA (typical value). Applying a
voltage above 1.2 V to EN pin will enable the DC/DC
converter for normal operation. The device will go through
soft−start to normal operation.
APPLICATION INFORMATION
Output Voltage Selection
The output voltage is programmed through an external
resistor divider connected from V
to FB then to GND.
OUT
For low power consumption and noise immunity, the
resistor from FB to GND (R2) should be in the [100 kW
600 k] range. If R2 is 200 k given the VFB is 0.6 V, the
current through the divider will be 3.0 mA.
The formula below gives the value of V
, given the
OUT
desired R1 and the R2 value:
V
+ VFB ǒ1 )
OUT
• V
• V
: Output Voltage (V)
OUT
: Feedback Voltage = 0.6 V
FB
• R1: Feedback Resistor from V
OUT
Ǔ
R2
to FB
(eq. 2)
R1
• R2: Feedback Resistor from FB to GND
Input Capacitor Selection
In PWM operating mode, the input current is pulsating
with large switching noise. Using an input bypass capacitor
can reduce the peak current transients drawn from the input
supply source, thereby reducing switching noise
significantly. The capacitance needed for the input bypass
capacitor depends on the source impedance of the input
supply.
The maximum RMS current occurs at 50% duty cycle
with maximum output current, which is IO, max/2.
For NCP1532, a low profile ceramic capacitor of 10 mF
should be used for most of the cases. For effective bypass
results, the input capacitor should be placed as close as
possible to the VIN Pin. Capacitors with 10 V rated voltage
are recommended to avoid DC bias effect over input voltage
range.
Thermal Shutdown
Internal Thermal Shutdown circuitry is provided to
protect the integrated circuit in the event that the maximum
junction Temperature is exceeded. If the junction
temperature exceeds 180°C, the device shuts down. In this
mode all power transistors and control circuits are turned
off. The device restarts in soft start after the temperature
drops below 140°C. This feature is provided to prevent
catastrophic failures from accidental device overheating.
Short Circuit Protection
When one output is shorted to ground, the device limits
the inductor current. The duty−cycle is minimum and the
consumption on the input line is 300 mA (typ). When the
short circuit condition is removed, the device returns to the
normal mode of operation.
Table 1. LIST OF INPUT CAPACITOR
Murata GRM21BR61A106
Taiyo Yuden JMK212BJ106
TDK C2012X5R1A106
Output L−C Filter Design Considerations
10 mF
10 mF
10 mF
The NCP1532 is built in 2.25 MHz frequency and uses
current mode architecture. The correct selection of the
output filter ensures good stability and fast transient
response.
Due to the nature of the buck converter, the output L−C
filter must be selected to work with internal compensation.
For NCP1532, the internal compensation is internally fixed
and it is optimized for an output filter of L = 2.2 mH and
C
= 10 mF.
OUT
The corner frequency is given by:
f +
2p L C
1
Ǹ
+
2p 2.2 mH 10mF
OUT
1
Ǹ
+ 34 kHz
(eq. 3)
The device operates with inductance value of 2.2 mH. If
the corner frequency is moved, it is recommended to check
the loop stability depending of the accepted output ripple
voltage and the required output current. Take care to check
the loop stability. The phase margin is usually higher than
45°.
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NCP1532
Table 2. Table 2: L−C FILTER EXAMPLE
Inductance (L) Output Capacitor (C
1.0 mH 22 mF
2.2 mH 10 mF
4.7 mH 4.7 mF
Inductor Selection
OUT
)
The inductor parameters directly related to device
performances are saturation current and DC resistance and
inductance value. The inductor ripple current (DI
L
decreases with higher inductance:
V
DIL+
• DI
: Peak−to−Peak Inductor Ripple Current
L
OUT
L f
SW
ǒ
1 *
V
OUT
V
Ǔ
IN
(eq. 4)
• L: Inductor Value
• f
: Switching Frequency
SW
The saturation current of the inductor should be rated
higher than the maximum load current plus half the ripple
current:
DI
IL(max) + IO(max) )
• I
(max): Maximum Inductor Current
L
• I
(max): Maximum Output Current
O
L
2
The inductor’s resistance will factor into the overall
efficiency of the converter. For best performances, the DC
resistance should be less than 0.3 W for good efficiency.
Table 3. LIST OF INDUCTOR
FDK MIPW3226 series
TDK
Taiyo Yuden LQ CBL2012
Coil craft
VLF3010AT series
TFC252005 series
DO1605 Series
LPS4018 series
(eq. 5)
Output Capacitor Selection
Selecting the proper output capacitor is based on the
desired output ripple voltage. Ceramic capacitors with low
ESR values will have the lowest output ripple voltage and
are strongly recommended. The output capacitor requires
either an X7R or X5R dielectric. We recommend to place a
capacitor with rated voltage much higher than the output
voltage selected by the external divider. Capacitors with
10 V rated voltages are recommended from 2.0 V to 3.3 V
output voltages.
)
The output ripple voltage in PWM mode is given by:
SW
1
C
) ESR
OUT
DV
Table 4. LIST OF OUTPUT CAPACITOR
Murata
Taiyo Yuden
TDK
Feed−Forward Capacitor Selection
OUT
+ DIL
ǒ
4 f
GRM219R61A475
GRM21BR61A106
JMK212BY475MG
JMK212BJ106MG
C2012X5R1A475
C2012X5R1A106
The feed−forward capacitor sets the feedback loop
response and is critical to obtain good loop stability. Given
that the compensation is internally fixed, an 18 pF or higher
ceramic capacitor is needed. Choose a small ceramic
capacitor X7R or X5R or COG dielectric.
Ǔ
4.7 mF
10 mF
4.7 mF
10 mF
4.7 mF
10 mF
(eq. 6)
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NCP1532
LAYOUT CONSIDERATIONS
Electrical Layout Considerations
Implementing a high frequency DC−DC converter
requires respect of some rules to get a powerful portable
application. Good layout is key to prevent switching
regulators to generate noise to application and to
themselves.
Electrical layout guide lines are:
• Use short and large traces when large amount of current
is flowing.
• Keep the same ground reference for input and output
capacitors to minimize the loop formed by high current
path from the battery to the ground plane.
• Isolate feedback pin from the switching pin and the
current loop to protect against any external parasitic
signal coupling. Add a feed−forward capacitor between
VOUT and FB which adds a zero to the loop and
participates to the good loop stability. A 18 pF
SW1
trace
Vout1
trace
capacitor is recommended to meet compensation
requirements. A four layer PCB with a ground plane
and a power plane will help NCP1532 noise immunity
and loop stability.
Thermal Layout Considerations
High power dissipation in small package leads to thermal
consideration such as:
• Enlarge the V
trace and add several vias that are
IN
connected to power plane.
• Connect the GND pin to the top plane.
• Join top, bottom and each ground plane together using
several free vias in order to increase dissipation
capability.
For high ambient temperature and high power dissipation
requirements, refer to notes 7, 8, and 9 to prevent any
thermal issue.
FB1
trace
MODE
/SYNC
trace
Vin trace
POR
trace
SW2
trace
PGND
Vout2
trace
Figure 25.
En1
trace
En2
trace
FB2
trace
GND
plane
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10X
PIN ONE
REFERENCE
2X
2X
0.10 C
0.08 C
10X
0.15 C
0.15 C
L
NCP1532
PACKAGE DIMENSIONS
UDFN10 3x3, 0.5P
CASE 506AT
ISSUE A
NOTES:
D
A
B
E
A3
A
A1
SEATING
C
PLANE
D2
8X
1
e
5
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
DIMAMIN NOM MAX
A1 0.00 0.03 0.05
A3 0.127 REF
b 0.18 0.25 0.30
D 3.00 BSC
D2 2.40 2.50 2.60
E 3.00 BSC
E2
K
L
MILLIMETERS
0.45 0.50 0.55
1.70 1.80 1.90
e 0.50 BSC
0.19 TYP
0.30 0.40 0.50
SOLDERING FOOTPRINT*
2.6016
2.1746
1.8508
3.3048
E2
10X
K 10
6
b
10X
A0.10 C
B
0.05 C
NOTE 3
10X
0.5651
10X
0.3008
0.5000 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NCP1532/D
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