Page 1
NCP1521B
1.5 MHz, 600 mA Step-Down
DC-DC Converter
High−Efficiency, Low Ripple, Adjustable
Output Voltage
The NCP1521B step−down DC−DC converter is a monolithic
integrated circuit optimized for portable applications powered from one
cell Li−Ion or three cell Alkaline/NiCd/NiMH batteries. The part,
available in adjustable output voltage versions ranging from 0.9 V to
3.9 V, is able to deliver up to 600 mA. It uses synchronous rectification
to increase efficiency and reduce external part count. The device also
has a built−in 1.5 MHz (nominal) oscillator which reduces component
size by allowing smaller inductors and capacitors. Automatic switching
PWM/PFM mode offers improved system efficiency.
Additional features include integrated soft−start, cycle−by−cycle
current limiting and thermal shutdown protection. The NCP1521B is
available in a space saving, low profile TSOP5 and UDFN6 packages.
Features
• Up to 96% Efficiency
• Best−In−Class Ripple, including PFM Mode
• Sources up to 600 mA
• 1.5 MHz Switching Frequency
• Adjustable Output Voltage from 0.9 V to 3.9 V
• Synchronous Rectification for Higher Efficiency
• 2.7 V to 5.5 V Input Voltage Range
• Low Quiescent Current
• Shutdown Current Consumption of 0.3 mA
• Thermal Limit Protection
• Short Circuit Protection
• All Pins are Fully ESD Protected
• This is a Pb−Free Device
Typical Applications
• Cellular Phones, Smart Phones and PDAs
• Digital Still/Video Cameras
• MP3 Players and Portable Audio Systems
• Wireless and DSL Modems
• Portable Equipment
• USB Powered Devices
http://onsemi.com
MARKING
DIAGRAM
5
TSOP−5
5
1
GAL = Specific Device Code
A = Assembly Location
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
ZC = Specific Device Code
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device Package Shipping
NCP1521BSNT1G TSOP−5
NCP1521BMUTBG UDFN6
NCP1521BMUTAG UDFN6
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
SN SUFFIX
CASE 483
UDFN6
MU SUFFIX
CASE 517AB
(Pb−Free)
(Pb−Free)
(Pb−Free)
GALAYWG
G
1
1
ZCMG
2
G
3
3000/Tape & Reel
3000/Tape & Reel
3000/Tape & Reel
6
5
4
†
VIN
CIN
OFF ON
Figure 1. Typical Application − TSOP−5
© Semiconductor Components Industries, LLC, 2013
August, 2013 − Rev. 6
1
VIN
GND
2
EN
3
LX
FB
5
4
L VOUT
COUT
R1
R2
OFF ON
Cff
VIN
1 Publication Order Number:
1
EN
GND
2
VIN
3
Figure 2. Typical Application − UDFN6
FB
LX
GND
6
5
4
R2
R1
NCP1521B/D
VOUT
Page 2
NCP1521B
100%
95%
90%
85%
80%
75%
70%
65%
EFFICIENCY (%)
60%
55%
50%
0 100 200 300 400 500 600 700
I
(mA)
OUT
Figure 3. Efficiency vs. Output Current
V
OUT
VIN = 4.2 V
TA = 25°C
= 3.3 V
V
battery
Enable
4.7 mF
VIN
1
GND
2
EN
3
LOGIC
CONTROL
& THERMAL
SHUTDOWN
Q1
Q2
PWM/PFM
CONTROL
I
LIMIT
REFERENCE
VOLTAGE
Figure 4. Simplified Block Diagram
LX
FB
2.2 mH
5
10 mF
R1
4
R2
18 pF
http://onsemi.com
2
Page 3
NCP1521B
PIN FUNCTION DESCRIPTION
Pin No.
TSOP5
1 3 VIN Analog /
2 2, 4 GND Analog /
3 1 EN Digital Input Enable for switching regulators. This pin is active HIGH and is turned off by
4 6 FB Analog Input Feedback voltage from the output of the power supply. This is the input to the
5 5 LX Analog Output Connection from power MOSFETs to the Inductor.
Pin No.
UDFN6
Pin Name Type Description
Power supply input for the PFET power stage, analog and digital blocks. The
Power Input
pin must be decoupled to ground by a 4.7 mF ceramic capacitor.
This pin is the GND reference for the NFET power stage and the analog sec-
Power Ground
tion of the IC. The pin must be connected to the system ground.
logic LOW on this pin. Do not let this pin float.
error amplifier.
PIN CONNECTIONS
VIN
GND
EN
1
2
3
LX
5
4
FB
EN
GND
VIN
1
2
3
FB
6
5
LX
4
GND
(Top View)
Figure 5. Pin Connections − TSOP5 Figure 6. Pin Connections − UDFN6
MAXIMUM RATINGS
Rating Symbol Value Unit
Minimum Voltage All Pins V
Maximum Voltage All Pins (Note 2) V
Maximum Voltage EN, FB, LX V
Thermal Resistance, Junction −to−Air
min
max
max
R
q
JA
(with Recommended Soldering Footprint) TSOP5
UDFN6
Operating Ambient Temperature Range T
Storage Temperature Range T
Junction Operating Temperature T
A
stg
j
Latch−up Current Maximum Rating (TA = 85°C) (Note 4) Lu $100 mA
ESD Withstand Voltage (Note 3)
V
esd
Human Body Model
Machine Model
Moisture Sensitivity Level (Note 5) MSL 1 per IPC
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = 25°C.
2. According to JEDEC standard JESD22−A108B.
3. This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM) per JEDEC standard: JESD22−A114.
Machine Model (MM) per JEDEC standard: JESD22−A115.
4. Latchup current maximum rating per JEDEC standard: JESD78.
5. JEDEC Standard: J−STD−020A.
−0.3 V
7.0 V
VIN + 0.3 V
°C/W
300
260
−40 to 85 °C
−55 to 150 °C
−40 to 125 °C
2.0
kV
200
V
http://onsemi.com
3
Page 4
NCP1521B
ELECTRICAL CHARACTERISTICS (Typical values are referenced to T
ambient temperature, unless otherwise noted, operating conditions VIN = 3.6 V, V
= +25°C, Min and Max values are referenced −40°C to +85°C
A
= 1.2 V, unless otherwise noted.)
OUT
Pin
Rating
TSOP UDFN
Symbol Min Typ Max Unit
VIN PIN
Input Voltage Range
Quiescent Current, PFM No Switching 1 3 I
Standby Current, EN Low 1 3 I
Undervoltage Lockout (VIN Falling) 1 3 V
1 3 V
IN
q ON
q OFF
UVLO
2.7 − 5.5 V
− 30 45 mA
− 0.2 1.5 mA
2.2 2.4 2.55 V
EN PIN
Positive going Input High Voltage Threshold, EN0 Signal 3 1 V
Negative going Input High Voltage Threshold, EN0 Signal 3 1 V
EN High Input Current, EN = 3.6 V 3 1 I
IH
IL
ENH
1.2 − − V
− − 0.4 V
− 2.0 − mA
OUTPUT
Output Voltage Accuracy (Note 6)
Ambient Temperature
Overtemperature Range
Feedback Voltage Threshold 4 6 V
Minimum Output Voltage V
Maximum Output Voltage V
Maximum Output Voltage for USB or 5 V Rail Powered Applications
Vin from 4.3 V to 5.5 V (Note 7)
Output Voltage load regulation Overtemperature
I
= 100 mA to 600 mA
OUT
Load Transient Response, Rise/Falltime 1 ms
10 mA to 100 mA Load Step
200 mA to 600 mA Load Step
Output Voltage Line Regulation, I
VIN = 2.7 V to 5.5 V
Line Transient Response, I
3.6 V to 3.0 V Line Step (Falltime=50 ms)
Output Voltage Ripple, I
Output Voltage Ripple, I
OUT
= 300 mA (PWM Mode) V
OUT
= 0 mA (PFM Mode) V
OUT
= 100 mA,
OUT
= 100 mA,
Peak Inductor Current 5 5 I
Oscillator Frequency 5 5 F
V
V
V
V
V
V
OUT
FB
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
LIM
OSC
−
−3.0
$1.0
$2.0
−
3.0
− 0.6 − V
− 0.9 − V
− 3.3 − V
− 3.9 −
%/mA
−
0.0005
−
−
−
−
35
80
−
−
−
−
− 0.05 −
mV
− 6 −
− 2.0 − mV
− 8.0 − mV
− 1200 − mA
1.3 1.5 1.8 MHz
Duty Cycle 5 5 − − − 100 %
Soft−Start Time T
Thermal Shutdown Threshold T
Thermal Shutdown Hysteresis T
START
SD
SDH
− 320 500 ms
− 160 − °C
− 25 − °C
POWER SWITCHES
P−Channel On−Resistance RLxH − 400 − mW
N−Channel On−Resistance RLxL − 400 − mW
P−Channel Leakage Current I
N−Channel Leakage Current I
LeakH
LeakL
− 0.05 − mA
− 0.01 − mA
6. The overall output voltage tolerance depends upon the accuracy of the external resistor (R1, R2).
7. Functionality guaranteed per design and characterization, see chapter ”USB or 5 V Rail Powered Applications”.
%
V
mV
%
PP
http://onsemi.com
4
Page 5
NCP1521B
TABLE OF GRAPHS
Typical Characteristics for Step−down Converter Figure
I
STB
I
q
V
OUT
Eff Efficiency vs. Output Current 11, 12, 13 and 29
Freq Switching Frequency vs. Input Voltage 14
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
Standby Current vs. Input Voltage 7
Quiescent Current, PFM No Switching vs. Input Voltage 8
Output Voltage Accuracy vs. Temperature 9 and 10
Soft−Start vs. Time 15
Short Circuit Protection vs. Time 16
Line Regulation vs. Input Voltage 17 and 18
Line Transient vs. Time 19 and 20
Load Regulation vs. Output Current 21, 22 and 30
Load Transient vs. Time 23, 24, 25 and 26
1.0
0.9
EN = 0 V
I
OUT
= 0 mA
0.8
0.7
0.6
(mA)
0.5
STB
0.4
I
0.3
0.2
0.1
0
2.7 3.2 3.7 4.2 4.7 5.2
VIN, INPUT VOLTAGE (V)
Figure 7. Shutdown Current vs. Supply Voltage
35
EN = V
IN
I
OUT
= 0 mA
34
33
32
31
30
QUIESCENT CURRENT (mA)
29
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VIN, INPUT VOLTAGE (V)
Figure 8. Quiescent Current PFM No Switching
vs. Supply Voltage
http://onsemi.com
5
Page 6
NCP1521B
1.0%
0.5%
I
= 30 mA
I
= 30 mA
OUT
OUT
0%
ACCURACY (%)
−0.5%
−1.0%
−40 0 40 80
TEMPERATURE (°C)
I
OUT
= 600 mA
Figure 9. Output Voltage Accuracy vs. Temperature
= 3.6 V, V
(V
IN
100%
95%
90%
85%
80%
75%
70%
EFFICIENCY (%)
65%
60%
55%
50%
0 100 200 300 400 500 600
I
, OUTPUT CURRENT (mA)
OUT
OUT
= 1.2 V)
V
= 1.8 V
OUT
V
= 0.9 V
OUT
V
OUT
= 3.3 V
Figure 11. Efficiency vs. Output Current
= 3.6 V, TA = 255C)
(V
IN
1.0%
0.5%
VIN = 2.7 V
VIN = 5.5 V
0%
ACCURACY (%)
VIN = 3.6 V
−0.5%
−1.0%
−40 0 40 80
TEMPERATURE (°C)
Figure 10. Output Voltage Accuracy vs. Temperature
= 1.2 V, I
(V
OUT
100%
95%
90%
85%
80%
75%
70%
EFFICIENCY (%)
65%
60%
55%
50%
VIN = 3.6 V
0 100 200 300 400 500 600
VIN = 2.7 V
VIN = 5.5 V
I
, OUTPUT CURRENT (mA)
OUT
OUT
= 200 V)
Figure 12. Efficiency vs. Output Current
= 1.2 V, TA = 255C)
(V
OUT
100%
95%
90%
85%
80%
75%
70%
EFFICIENCY (%)
65%
60%
55%
50%
0 100 200 300 400 500 600
I
, OUTPUT CURRENT (mA)
OUT
25°C
−40°C
85°C
Figure 13. Efficiency vs. Output Current
= 3.6 V, V
(V
IN
OUT
= 1.2 V)
1.8
1.7
1.6
1.5
FREQUENCY (MHz)
1.4
1.3
http://onsemi.com
6
−40°C
25°C
2.7 3.2 3.7 4.2 4.7 5.2
VIN, INPUT VOLTAGE (V)
85°C
Figure 14. Switching Frequency vs. Input
Voltage (V
OUT
= 1.2 V, I
= 300 mA)
OUT
Page 7
V
OUTIN
2 V/div
V
OUT
500 mV/div
I
LX
200 mV/div
Time
100 ms/div
NCP1521B
Time
2.5 ms/div
I
LX
500 mV/div
V
OUT
200 mV/div
Figure 15. Typical Soft−Start
= 3.6 V, V
(V
IN
1.25
1.24
1.23
1.22
1.21
1.20
1.19
1.18
, OUTPUT VOLTAGE (V)
1.17
OUT
V
1.16
1.15
2.7 3.2 3.7 4.2 4.7 5.2
VIN, INPUT VOLTAGE (V)
OUT
85°C
= 1.2 V, I
25°C
= 250 mA)
OUT
Figure 17. Line Regulation
V
IN
1 V/div
(V
OUT
= 1.2 V, I
= 100 mA)
OUT
−40°C
Figure 16. Short−Circuit Protection
= 3.6 V, V
(V
IN
1.25
1.24
1.23
1.22
1.21
1.20
1.19
1.18
, OUTPUT VOLTAGE (V)
1.17
OUT
V
1.16
1.15
I
= 1 mA
OUT
I
= 100 mA
OUT
I
= 600 mA
OUT
2.7 3.2 3.7 4.2 4.7 5.2
VIN, INPUT VOLTAGE (V)
OUT
= 1.2 V)
Figure 18. Line Regulation
= 1.2 V, TA = 255C)
(V
OUT
V
IN
1 V/div
Time
20 ms/div
Figure 19. 3.0 V to 3.6 V Line Transient
(Risetime = 50 ms, V
OUT
= 255C)
T
A
= 1.2 V, I
OUT
V
OUT
20 mV/div
= 100 mA,
(Risetime = 50 ms, V
http://onsemi.com
7
V
OUT
20 mV/div
Time
20 ms/div
Figure 20. 3.6 V to 3.0 V Line Transient
OUT
= 255C)
T
A
= 1.2 V, I
= 100 mA,
OUT
Page 8
NCP1521B
0
1.5
1.0
0.5
0
−0.5
LOAD REGULATION (%)
−1.0
−1.5
0 100 200 300 400 500 600
I
, (mA)
OUT
−40°C
85°C
Figure 21. Load Regulation
(V
V
OUT
50 mV/div
= 3.6 V, V
IN
OUT
= 1.2 V)
25°C
1.5
1.0
0.5
0
−0.5
LOAD REGULATION (%)
−1.0
−1.5
0 100 200 300 400 500 60
VIN = 5.5 V
VIN = 3.6 V
I
, (mA)
OUT
VIN = 2.7 V
Figure 22. Load Regulation
= 1.2 V, TA = 255C)
(V
OUT
V
OUT
50 mV/div
I
OUT
50 mA/div
Figure 23. 10 mA to 100 mA Load Transient
= 3.6 V, V
(V
IN
V
OUT
50 mV/div
I
OUT
200 mA/div
= 1.2 V, TA = 255C)
OUT
Figure 25. 200 mA to 600 mA Load Transient
(V
IN
= 3.6 V, V
= 1.2 V, TA = 255C)
OUT
I
OUT
50 mA/div
Figure 24. 100 mA to 10 mA Load Transient
= 3.6 V, V
(V
IN
I
OUT
200 mA/div
= 1.2 V, TA = 255C)
OUT
V
OUT
50 mV/div
Figure 26. 600 mA to 200 mA Load Transient
= 3.6 V, V
(V
IN
= 1.2 V, TA = 255C)
OUT
http://onsemi.com
8
Page 9
NCP1521B
OPERATION DESCRIPTION
Overview
The NCP1521B uses a constant frequency, current mode
step−down architecture. Both the main (P−Channel
MOSFET) and synchronous (N−Channel MOSFET)
switches are internal.
It delivers a constant voltage from either a single Li−Ion
or three cell NiMH/NiCd battery to portable devices such
as cell phones and PDA. The output voltage is set by an
external resistor divider. The NCP1521B sources at least
600 mA, depending on external components chosen.
The NCP1521B works with two modes of operation;
PWM/PFM depending on the current required. In PWM
mode, the device can supply voltage with a tolerance of
"3% and 90% efficiency or better. Lighter load currents
cause the device to automatically switch into PFM mode
for reduced current consumption and extended battery life.
Additional features include soft−start, undervoltage
protection, current overload protection, and thermal
shutdown protection. As shown in Figure 1, only six
external components are required. The part uses an internal
reference voltage of 0.6 V. It is recommended to keep the
part in shutdown mode until the input voltage is 2.7 V or
higher.
PWM Operating Mode
In this mode, the output voltage of the NCP1521B is
regulated by modulating the on−time pulse width of the
main switch Q1 at a fixed frequency of 1.5 MHz. The
switching of the PMOS Q1 is controlled by a flip−flop
driven by the internal oscillator and a comparator that
compares the error signal from an error amplifier with the
sum of the sensed current signal and compensation ramp.
This driver switches ON and OFF the upper side transistor
(Q1) and switches the lower side transistor (Q2) in either
ON state or in current source mode. At the beginning of
each cycle, the main switch Q1 is turned ON while Q2 is
in its current source mode by the rising edge of the internal
oscillator clock. The inductor current ramps up until the
sum of the current sense signal and compensation ramp
becomes higher than the error voltage amplifier. Once this
has occurred, the PWM comparator resets the flip−flop, Q1
is turned OFF and the synchronous switch Q2 is turned in
its ON state. Q2 replaces the external Schottky diode to
reduce the conduction loss and improve the efficiency. To
avoid overall power loss, a certain amount of dead time is
introduced to ensure Q1 is completely turned OFF before
Q2 is being turned ON.
V
OUT
10mV/div
I
Lx
100mA/div
V
Lx
2V/div
200 ns/div
Figure 27. PWM Switching Waveform
= 3.6 V, V
(V
IN
PFM Operating Mode
OUT
= 1.2 V, I
= 600 mA)
OUT
Under light load conditions, the NCP1521B enters in low
current PFM mode operation to reduce power
consumption. The output regulation is implemented by
pulse frequency modulation. If the output voltage drops
below the threshold of PFM comparator, a new cycle will
be initiated by the PFM comparator to turn on the switch
Q1. Q1 remains ON during the minimum on time of the
structure while Q2 is in its current source mode. The peak
inductor current depends upon the drop between input and
output voltage. After a short dead time delay where Q1 is
switched OFF, Q2 is turned in its ON state. The negative
current detector will detect when the inductor current drops
below zero and sends the signal to turn Q2 to current source
mode to prevent a too large deregulation of the output
voltage. When the output voltage falls below the threshold
of the PFM comparator, a new cycle starts immediately.
V
out
10mV/div
V
Lx
2V/div
I
Lx
100mA/div
http://onsemi.com
9
Figure 28. PFM Mode Switching Waveform
(V
IN
= 3.6 V, V
OUT
= 1.2 V, I
OUT
= 0 mA)
Page 10
NCP1521B
Cycle−by−Cycle Current Limitation
From the block diagram (Figure 4), an I
comparator
LIM
is used to realize cycle−by−cycle current limit protection.
The comparator compares the LX pin voltage with the
reference voltage, which is biased by a constant current. If
the inductor current reaches the limit, the I
comparator
LIM
detects the LX voltage falling below the reference voltage
and releases the signal to turn off the switch Q1. The
cycle−by−cycle current limit is set at 1200 mA (nom).
Short Circuit Protection
When the output is shorted to ground, the device limits
the inductor current. The duty−cycle is minimum and the
consumption on the input line is 300 mA (Typ). When the
short circuit condition is removed, the device returns to the
normal mode of operation.
Soft−Start
The NCP1521B uses soft−start (300 ms Typ) to limit the
inrush current when the device is initially enabled.
Soft−start is implemented by gradually increasing the
reference voltage until it reaches the full reference voltage.
During startup, a pulsed current source charges the internal
soft−start capacitor to provide gradually increasing
reference voltage. When the voltage across the capacitor
ramps up to the nominal reference voltage, the pulsed
current source will be switched off and the reference
voltage will switch to the regular reference voltage.
Shutdown Mode
Forcing this pin to a voltage below 0.4 V will shut down
the IC. In shutdown mode, the internal reference, oscillator
and most of the control circuitries are turned off. Therefore,
the typical current consumption will be 0.3 mA (typical
value). Applying a voltage above 1.2 V to EN pin will
enable the device for normal operation. The typical
threshold is around 0.7 V. The device will go through
soft−start to normal operation.
Thermal Shutdown
Internal Thermal Shutdown circuitry is provided to
protect the integrated circuit in the event that the maximum
junction temperature is exceeded. If the junction
temperature exceeds 160°C, the device shuts down. In this
mode switch Q1 and Q2 and the control circuits are all
turned off. The device restarts in soft−start after the
temperature drops below 135°C. This feature is provided
to prevent catastrophic failures from accidental device
overheating, and it is not intended as a substitute for proper
heatsinking.
Low Dropout Operation
The NCP1521B offers a low input to output voltage
difference. The NCP1521B can operate at 100% duty
cycle. In this mode the PMOS (Q1) remains completely on.
The minimum input voltage to maintain regulation can
be calculated as:
V
IN(min)
• V
OUT
• I
OUT
• R
DS(on)
• R
INDUCTOR
USB or 5 V Rail Powered Applications
+ V
OUT(max)
) (I
OUT
(R
: Output Voltage (Volts)
: Max Output Current
: P−Channel Switch R
: Inductor Resistance (DCR)
DS(on)
DS(on)
) R
INDUCTOR
))
(eq. 1)
For USB or 5 V rail powered applications, NCP1521B is
able to supply voltages up to 3.9 V, 600 mA, operating in
PWM mode only, with high efficiency (Figure 29), low
output voltage ripple and good load regulation results over
all current range (Figure 30).
100
90
25°C
80
70
EFFICIENCY (%)
60
50
0 100 200 300 400 500 600
I
, OUTPUT CURRENT (mA)
OUT
Figure 29. Efficiency vs. Output Current
= 5.0 V, V
(V
IN
2.0
1.5
1.0
0.5
0
−0.5
−1.0
LOAD REGULATION (%)
−1.5
−2.0
0 100 200 300 400 500 600
Figure 30. Load Regulation
= 5.0 V, V
(V
IN
I
OUT
OUT
, (mA)
OUT
= 3.9 V)
= 3.9 V)
25°C
−40°C
85°C
−40°C
85°C
http://onsemi.com
10
Page 11
NCP1521B
APPLICATION INFORMATION
Output Voltage Selection
The output voltage is programmed through an external
resistor divider connected from V
to FB then to GND.
OUT
For low power consumption and noise immunity, the
resistor from FB to GND (R2) should be in the
[100 k−600 k] range. If R2 is 200 k given the VFB is 0.6 V,
the current through the divider will be 3.0 mA.
The formula below gives the value of V
, given the
OUT
desired R1 and the R1 value:
V
+ VFB (1 )
OUT
• V
• V
: Output Voltage (Volts)
OUT
: Feedback Voltage = 0.6 V
FB
• R1: Feedback Resistor from V
OUT
R1
)
R2
to FB
(eq. 2)
• R2: Feedback Resistor from FB to GND
Input Capacitor Selection
In PWM operating mode, the input current is pulsating
with large switching noise. Using an input bypass capacitor
can reduce the peak current transients drawn from the
input supply source, thereby reducing switching noise
significantly. The capacitance needed for the input bypass
capacitor depends on the source impedance of the input
supply.
The maximum RMS current occurs at 50% duty cycle
with maximum output current, which is I
For NCP1521B, a low profile, low ESR ceramic
capacitor of 4.7 mF should be used for most of the cases. For
effective bypass results, the input capacitor should be
placed as close as possible to the VIN pin.
Table 1. List of Input Capacitor
Murata GRM188R60J475KE
GRM21BR71C475KA
Taiyo Yuden JMK212BY475MG
TDK C2012X5ROJ475KB
C1632X5ROJ475KT
Output L−C Filter Design Considerations
The NCP1521B operates at 1.5 MHz frequency and uses
current mode architecture. The correct selection of the
output filter ensures good stability and fast transient
response.
Due to the nature of the buck converter, the output L−C
filter must be selected to work with internal compensation.
For NCP1521B, the internal compensation is internally
fixed and it is optimized for an output filter of L = 2.2 mH
and C
OUT
= 10 mF.
out_max
/2.
The corner frequency is given by:
fc+
1
Ǹ
2p L C
OUT
+
2p 2.2 mH 10 mF
1
Ǹ
+ 34 kHz
(eq. 3)
The device is intended to operate with inductance values
between 1.0 mH and maximum of 4.7 mH.
If the corner frequency is moved, it is recommended to
check the loop stability depending on the output ripple
voltage accepted and output current required. For lower
frequency, the stability will be increased; a larger output
capacitor value could be chosen without critical effect on
the system. On the other hand, a smaller capacitor value
increases the corner frequency and it should be critical for
the system stability. Take care to check the loop stability.
The phase margin is usually higher than 45°.
Table 2. L−C Filter Example
Inductance (L) Output Capacitor (C
1.0 mH 22 mF
2.2 mH 10 mF
4.7 mH 4.7 mF
Inductor Selection
out
)
The inductor parameters directly related to device
performances are saturation current and DC resistance and
inductance value. The inductor ripple current (DIL)
decreases with higher inductance:
DIL+
V
OUT
L f
SW
V
OUT
ǒ
1−
Ǔ
V
IN
(eq. 4)
DIL peak to peak inductor ripple current
L inductor value
fSW switching frequency
The saturation current of the inductor should be rated
higher than the maximum load current plus half the ripple
current:
DI
DI
L(MAX)
DI
O(MAX)
I
L(MAX)
+ I
O(MAX)
Maximum inductor current
Maximum Output current
)
L
2
(eq. 5)
The inductor’s resistance will factor into the overall
efficiency of the converter. For best performances, the DC
resistance should be less than 0.3 W for good efficiency.
http://onsemi.com
11
Page 12
NCP1521B
Table 3. LIST OF INDUCTOR
FDK MIPW3226 Series
TDK VLF3010AT Series
Taiyo Yuden LQ CBL2012
Coil craft DO1605−T Series
LPO3010
Output Capacitor Selection
Selecting the proper output capacitor is based on the
desired output ripple voltage. Ceramic capacitors with low
ESR values will have the lowest output ripple voltage and
are strongly recommended. The output capacitor requires
either an X7R or X5R dielectric.
The output ripple voltage in PWM mode is given by:
DV
OUT
+ DIL
ǒ
4 fSW C
1
OUT
) ESR
Ǔ
(eq. 6)
In PFM mode (at light load), the output voltage is
regulated by pulse frequency modulation. The output
voltage ripple is independent of the output capacitor value.
It is set by the threshold of PFM comparator.
Table 4. LIST OF OUTPUT CAPACITOR
Murata GRM188R60J475KE 4.7 mF
GRM21BR60J106ME19L 10 mF
GRM188R60OJ106ME 10 mF
Taiyo Yuden JMK212BY475MG 4.7 mF
JMK212BJ106MG 10 mF
TDK C2012X5ROJ475KB 4.7 mF
C2012X5ROJ226M 22 mF
C2012X5ROJ106K 10 mF
Feed−Forward Capacitor Selection
The feed−forward capacitor sets the feedback loop
response and is critical to obtain good loop stability.
Given that the compensation is internally fixed, a fixed
18 pF or higher ceramic capacitor is needed. Choose a
small ceramic capacitor X7R or X5R or COG dielectric.
http://onsemi.com
12
Page 13
NCP1521B
PACKAGE DIMENSIONS
TSOP−5
CASE 483−02
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
NOTE 5
2X
2X
T0.10
T0.20
54
123
L
G
D
0.205XC AB
M
S
B
K
DETAIL Z
A
J
DETAIL Z
C
0.05
H
SEATING
PLANE
T
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5. OPTIONAL CONSTRUCTION: AN
ADDITIONAL TRIMMED LEAD IS ALLOWED
IN THIS LOCATION. TRIMMED LEAD NOT TO
EXTEND MORE THAN 0.2 FROM BODY.
MILLIMETERS
DIM MIN MAX
A 3.00 BSC
B 1.50 BSC
C 0.90 1.10
D 0.25 0.50
G 0.95 BSC
H 0.01 0.10
J 0.10 0.26
K 0.20 0.60
L 1.25 1.55
M 0 10
__
S 2.50 3.00
SOLDERING FOOTPRINT*
1.9
0.95
0.037
1.0
0.039
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
0.074
0.028
0.7
2.4
0.094
SCALE 10:1
mm
ǒ
inches
Ǔ
http://onsemi.com
13
Page 14
NCP1521B
a
PACKAGE DIMENSIONS
UDFN6 2x2, 0.65P
CASE 517AB−01
ISSUE B
NOTES:
D
A
B
E
2X
2X
PIN ONE
REFERENCE
0.10 C
0.10 C
A3
0.10 C
A
6X
0.08 C
A1
C
SEATING
PLANE
D2
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
MILLIMETERS
DIMAMIN MAX
0.45 0.55
A1 0.00 0.05
A3 0.127 REF
b 0.25 0.35
D 2.00 BSC
D2 1.50 1.70
2.00 BSC
E
0.80 1.00
E2
e 0.65 BSC
K
0.20 ---
L
0.25 0.35
SOLDERING FOOTPRINT*
0.95
1
6X
0.47
6X
0.40
4X
6X
L
1
e
3
E2
1.70
0.65
PITCH
2.30
6X
K
6
BOTTOM VIEW
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf . SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products
for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical
experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components
in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall
indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney
fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was
negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws
and is not for resale in any manner.
4
6X
b
A0.10 C
0.05 C
*For additional information on our Pb−Free strategy and soldering
B
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DIMENSIONS: MILLIMETERS
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
http://onsemi.com
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your loc
Sales Representative
NCP1521B/D
14
Loading...