Datasheet NCP1396ADR2G Specification

NCP1396A, NCP1396B

High Performance Resonant
Mode Controller featuring
High--Voltage Drivers

The NCP1396 A/B offers everything needed to build a reliable and
rugged resona nt mode power supply. Its unique architecture includes
a 500 kHz Voltage Controlled Oscillator whose control mode brings
flexibility when an ORing function is a necessity, e.g. in multiple
feedback paths implementations. Thanks to its proprietary
high--voltage technology, the controller welcomes a bootstrapped
MOSFET driver for half--bridge applications accepting bulk voltages
up to 600 V. Protections featuring various reaction times, e.g.
immediate shutdown or timer--based event, brown--out, broken
opto--coupler detection etc., contribute to a safer converter design,
without engende ring additional circuitry complexity. An adjustable
deadtime also helps lowering the shoot--through current contribution
as the switching frequency increases.

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16

1

SO--16, LESS PIN 13

D SUFFIX

CASE 751AM

MARKING

DIAGRAMS

16

NCP1396xG

AWLYWW

1

Features

 High--frequency Operation from 50 kHz up to 500 kHz
 600 V High--Voltage Floating Driver
 Selectable Minimum Switching Frequency with 3% Accuracy
 Adjustable Deadtime from 100 ns to 2 ms.
 Startup Sequence via an Adjustable Soft--start
 Brown--out Protection for a Simpler PFC Association
 Latched Input for Severe Fault Conditions, e.g. Over Temperature

or OVP

 Timer--based Input with Auto--recovery Operation for Delayed

Event Reaction

 Enable Input for Immediate Eve nt Reaction or Simple ON/OFF

Control

 V

Operationupto20V

CC

 Low Startup Current of 300 mA
 1 A / 0.5 A Peak Current Sink / Source Drive Capability
 Common Collector Optocoupler Connection for Easier ORing
 Internal Temperature Shutdown
 B Version features 10 V V

Startup Threshold

CC

 These are Pb-- Free Devices

Typical Applications

 Flat Panel Display Power Converters
 High Power AC/DC Adapters for Notebooks
 Industrial and Medical Power Sources
 Offline Battery Chargers

x=AorB
A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
G = Pb--Free Package

PIN CONNECTIONS

1

CSS

Fmax

2

Ctimer

3

Rt

4

BO

5

FB

6

DT

7

Fast Fault

See detailed ordering and shipping information in the package
dimensions section on page 24 of this data sheet.

8

(Top View)

ORDERING INFORMATION

16

15

14

12

11

10

9

Vboot

Mupper

HB

VCC

Mlower

GND

Slow Fault

 Semiconductor Components Industries, LLC, 2010

November, 2010 -- Rev. 7

1 Publication Order Number:

NCP1396/D

HV

U2A

Fmax

C9

R19C8R9

OVPFB

U3A

R7

Fast

Input

C10

R14 R18

R13

Rt

R6

NCP1396A, NCP1396B

R8R17

U5

1

2

3

4

5

6

7

8

16

15

14

12

11

10

9

R24

R20

C12

D8

R21

Slow Input

R10

R11

M1

M2

R23

+

C6

L1

C13

D9

D3

C11

+

C7

C14

R22

D7

R16

T1

C1

D4

D1

D2

U1

R4

+

C2

FB OVP

R3

C4

C3

Vout

R12

R1R5

U3BU2B

D6

R2

Soft--

start

Timer

Skip

Selection

DTBO

Figure 1. Typical Application Example

PIN FUNCTION DESCRIPTION

Pin No. Pin Name Function Pin Description

1 CSS Soft--start Select the soft--start duration

2 Fmax Frequency clamp A resistor sets the maximum frequency excursion

3 Ctimer Timer duration Sets the timer duration in presence of a fault

4 Rt Timing resistor Connecting a resistor to this pin, sets the minimum oscillator frequency

5 BO Brown--Out Detects low input voltage conditions. When brought above Vlatch, it fully

6 FB Feedback Injecting current in this pin increases the oscillation frequency up to Fmax.

7 DT Dead--time A simple resistor adjusts the dead--time width

8 Fast Fault Quick fault detection Fast shut--down pin. Upon release, a clean startup sequence occurs. Can be

9 Slow Fault Slow fault detection When asserted, the timer starts to countdown and shuts down the controller

10 GND Analog ground --

11 Mlower Low side output Drives the lower side MOSFET

12 V

CC

Supplies the controller Thecontrolleracceptsupto20V

13 -- -- --

14 HB Half-- bridge connection Connects to the half--bridge output

15 Mupper High side output Drives the higher side MOSFET

16 Vboot Bootstrap pin ThefloatingVCCsupply for the upper stage

reached for VFB = 1 V

latches off the controller.

used for skip cycle purposes.

at the end of its time duration.

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2

Vdd

Vdd

NCP1396A, NCP1396B

Temperature

Shutdown

Rt

I = Imax for Vfb = 5.3 V
I = 0 for Vfb < Vfb_min

Fmax

Tim er

Vref

Vref

Vdd

Vref

If FAULT Itimer else 0

+

Vdd

C

Itimer

Vref

Imin
Vfb  Vfb_off

IDT

Vdd

Imax
Vfb = 5

+

--

+

PON
Reset
Fault

+

--

DT Adj.

SS

Timeout
Fault

S

D

Q

PON
Reset

Fault

Timeout
Fault

Vref

Management

FF

VCC

BO
Reset

Fast
Fault

Level

Shifter

UVLO

Clk

Q

R

50% DC

V

BOOT

Mupper

HB

NC

V

CC

SS

FB

DT

BO

RFB

Slow
Fault

ISS

IBO

+

Vfb_fault

Vdd

+

Vref Fault

+

--

IDT

+

VBO

Fault

Filter

Mlower

GND

Fast
Fault

+

G=1

> 0 only

--

V=V(FB)--Vfb_min

+

Vfb_min

Vref

20 msNoise

Filter

+

--

+

--

+

Vlatch

20 msNoise

Filter

Vdd

Deadtime

Adjustment

--

+

Vref Fault

Q

Q

S

R

PON Reset

20 ns Noise

+

+

--

Figure 2. Internal Circuit Architecture

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3

NCP1396A, NCP1396B

MAXIMUM RATINGS

Rating Symbol Valu e Unit

High Voltage bridge pin, pin 14 VBRIDGE --1to600 V

Floating supply voltage VBOOT--

VBRIDGE

High side output voltage VDRV_HI VBRIDGE-- 0.3 to

Low side output voltage VDRV_LO --0.3toVCC+0.3 V

Allowable output slew rate dVBRIDGE/dt 50 V/ns

Power Supply voltage, pin 12 V

CC

Maximum voltage, all pins (except pin 11 and 10) -- --0.3to10 V

Thermal Resistance -- Junction--to-- Air, SOIC version R

Operating Junction Temperature Range T

Maximum Junction Temperature T

Storage Temperature Range T

θ

JA

J

JMAX

STG

ESD Capability, Human Body Model (All pins except HV Pins) -- 2 kV

ESD Capability, Machine Model -- 200 V

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.

1. This device series contains ESD protection and exceeds the following tests:

Human Body Model 2000V per JESD22--A114--B
Machine Model Method 200V per JESD22--A115--A.

2. This device meets latch--up tests defined by JEDEC Standard JESD78.

0to20 V

V

VBOOT+0.3

20 V

130 C/W

--40 to +125 C

+150 C

--60 to +150 C

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4

NCP1396A, NCP1396B

ELECTRICAL CHARACTERISTICS

(For typical values TJ=25C, for min/max values TJ=--40C to +125C, Max TJ= 150C, VCC= 12 V, unless otherwise noted.)

Characteristic

SUPPLY SECTION

Turn--on threshold level, V

going up – A version 12 VCC

CC

Turn--on threshold level, VCCgoing up – B version 12 VCC

Minimum operating voltage after turn-- on 12 VCC

Startup voltage on the floating section 16--14 Vboot

Cutoff voltage on the floating section 16--14 Vboot

Startup current, VCC<VCC

ON

0C<TJ< +125C

-- 4 0 C<T

< +125C

J

VCClevel at which the internal logic gets reset 12 VCC

Internal IC consumption, no output load on pin 15/14 – 11/10, Fsw =
300 kHz

Internal IC consumption, 1 nF output load on pin 15/14 – 11/10, Fsw =
300 kHz

Consumption in fault mode (All drivers disabled, VCC>V

) 12 ICC3 -- 1.2 -- mA

CC(min)

VOLTAGE CONTROL OSCILLATOR (VCO)

Characteristic

Minimum switching frequency, Rt = 18 kΩ on pin 4, Vpin 6 = 0.8 V , DT =
300 ns

Maximum switching frequency, Rfmax = 1.3 kΩ on pin 2, Vpin 6 > 5.3 V,
Rt = 18 kΩ, DT = 300 ns

Feedback pin swing above which Δf=0 6 FBSW -- 5.3 -- V

Operating duty-- cycle symmetry 11- -15 DC 48 50 52 %

Delay before any driver re--start in fault mode -- Tdel -- 20 -- ms

FEEDBACK SECTION

Characteristic

Internal pull--down resistor 6 Rfb -- 20 -- kΩ

Voltage on pin 6 below which the FB level has no VCO action 6 Vfb_min -- 1.2 -- V

Voltage on pin 6 below which the controller considers a fault 6 Vfb_off -- 0.6 -- V

DRIVE OUTPUT

Characteristic

Output voltage rise--time @ CL = 1 nF, 10--90% of output signal 15--14/1

Output voltage fall--time @ CL = 1 nF, 10--90% of output signal 15--14/1

Source resistance 15--14/1

Sink resistance 15-- 14/1

Dead time with RDT=10kΩ frompin7toGND 7 T_dead 250 300 340 ns

Maximum dead--time with RDT=82kΩ frompin7toGND 7 T_dead--max -- 2 -- ms

Minimum dead-- time, RDT=3kΩ frompin7toGND 7 T_dead--min -- 100 -- ns

Leakage current on high voltage pins to GND 14,

Pin Symbol Min Typ Max Unit

ON

ON

(min)

ON

(min)

12 Istartup --

reset

12.3 13.4 14.3 V

9.5 10.5 11. 5 V

8.5 9.5 10.5 V

8 9 10 V

7.4 8.4 9.4 V

--

--

300

--

350

-- 6.5 -- V

12 ICC1 -- 4 -- mA

12 ICC2 -- 11 -- mA

Pin Symbol Min Typ Max Unit

4 Fsw min 58.2 60 61.8 kHz

2 Fsw max 425 500 575 kHz

Pin Symbol Min Typ Max Unit

Pin Symbol Min Typ Max Unit

1--10

1--10

1--10

1--10

T

r

T

f

R

OH

R

OL

-- 40 -- ns

-- 20 -- ns

-- 13 -- Ω

-- 5.5 -- Ω

IHV_LEAK -- -- 5 mA

15,16

mA

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5

NCP1396A, NCP1396B

ELECTRICAL CHARACTERISTICS

(For typical values TJ=25C, for min/max values TJ=--40C to +125C, Max TJ= 150C, VCC= 12 V, unless otherwise noted.)

TIMERS

Characteristic

Timer charge current 3 Itimer -- 160 -- mA

Timer duration with a 1 mF capacitor anda1MΩ resistor 3 T--timer -- 25 -- ms

Timer recurrence in permanent fault, same values as above 3 T--timerR -- 1.4 -- s

Voltage at which pin 3 stops output pulses 3 VtimerON 3.5 4 4.4 V

Voltage at which pin 3 re--starts output pulses 3 VtimerOFF 0.9 1 1.1 V

Soft-- start ending voltage 1 VSS -- 2 -- V

Soft-- start charge current 0C<TJ< +125C

Soft-- start duration with a 100 nF capacitor (Note 3) 1 T--SS -- 1.8 -- ms

PROTECTION

Characteristic

Reference voltage for fast input (Note 4) 8--9 VrefFaultF 1.00 1.05 1.10 V

Hysteresis for fast input (Note 4) 8--9 HysteFaultF -- 80 -- mV

Reference voltage for slow input 0C<TJ< +125C

Hysteresis for slow input 8--9 HysteFaultS -- 60 -- mV

Propagation delay for fast fault input drive shutdown 8 TpFault -- 55 90 ns

Brown-- Out input bias current 5 IBObias -- 0.02 -- mA

Brown-- Out level (Note 4) 5 VBO 0.99 1.04 1.09 V

Hysteresis current, Vpin5 > VBO – A version 0C<TJ< +125C

Hysteresis current, Vpin5 > VBO – B version 0C<TJ< +125C

Latching voltage 5 Vlatch 3.6 4 4.4 V

Temperature shutdown -- TSD 140 -- -- C

Hysteresis -- TSDhyste -- 30 -- C

3. The A version does not activate soft-- start (unless the feedback pin voltage is below 0.6 V) when the fast--fault is released, this is for skip cycle

implementation. The B version does activate the soft--start upon release of the fast--fault input for any feedback conditions.

4. Guaranteed by design

-- 4 0 C<T

-- 4 0 C<T

-- 4 0 C<T

-- 4 0 C<T

< +125C

J

< +125C

J

< +125C

J

< +125C

J

Pin Symbol Min Typ Max Unit

1 ISS 80

75

Pin Symbol Min Typ Max Unit

8--9 VrefFaultS 0.95

0.92

5 IBO_A 21.51926.5

5 IBO_B 86

80

110
110

1.00

1.00

26.5

106
106

125
130

1.05

1.05

31.5
33

126
132

mA

V

mA

mA

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6

NCP1396A, NCP1396B

V

Y

TYPICAL CHARACTERISTICS -- A VERSION

13.55

13.5

13.45

13.4

(V)

13.35

13.3

CC(on)

13.25

13.2

13.15

13.1

-- 4 0 5 5 0

TEMPERATURE (C)

Figure 3. V

60.2

60.1

60.0

(kHz)

59.9

59.8

CC(on)

9.60

9.58

9.56

9.54

9.52

(V)

9.50

9.48

CC(min)

9.46

V

9.44

9.42

9.40

95 110 65 80

125--10 35 80--25 20 65

9.38

-- 4 0 5 5 0

TEMPERATURE (C)

Figure 4. V

501

500

499

498

497

CC(min)

125--10 35 110-- 25 20 95

59.7

FREQUENC

59.6

59.5

59.4

-- 4 0 5 6 5

35 80

TEMPERATURE (C)

Figure 5. Fsw min Figure 6. Fsw max

29

27

25

23

21

RFB (kΩ)

19

17

15

-- 4 0 5 6 5

35 80

TEMPERATURE (C)

496

FREQUENCY (kHz)

495

494

493

125--10 50 110--25 20 95

125--10 50 110--25 20 95

-- 4 0 5 6 5

TEMPERATURE (C)

1.060

1.055

1.050

1.045

1.040

1.035

VrefFaultFF (V)

1.030

1.025

1.020

-- 4 0 5 6 5

TEMPERATURE (C)

50 80

35 80

125--10 35 110--25 20 95

125--10 50 110-- 25 20 95

Figure 7. Pulldown Resistor (RFB)

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7

Figure 8. Fast Fault (VrefFaultF)

NCP1396A, NCP1396B

TYPICAL CHARACTERISTICS -- A VERSION

20

19

18

17

16

15

ROH (Ω)

14

13

12

11

-- 4 0 5 5 0

TEMPERATURE (C)

Figure 9. Source Resistance (ROH) Figure 10. Sink Resistance (ROL)

109

108

107

106

105

104

103

DT_min (ns)

102

101

100

99

-- 4 0 5 6 5

35 80

TEMPERATURE (C)

8.0

7.5

7.0

6.5

6.0

5.5

ROL (Ω)

5.0

4.5

4.0

3.5

95 110 65 80

125--10 35 80--25 20 65

125--10 50 110--25 20 95

-- 4 0 5 5 0

TEMPERATURE (C)

296

295

294

293

292

291

290

DT_nom (ns)

289

288

287

286

-- 4 0 5 6 5

TEMPERATURE (C)

50 80

125--10 35 110-- 25 20 95

125--10 35 110--25 20 95

Figure 11. T_dead_min Figure 12. T_dead_nom

1.970

1.968

1.966

1.964

DT_max (ms)

1.962

1.960

1.958

-- 4 0 5 6 5

35 80 35 80

TEMPERATURE (C)

Figure 13. T_dead_max

3.960

3.955

3.950

3.945

3.940

3.935

3.930

Vlatch (V)

3.925

3.920

3.915

3.910

125--10 50 110--25 20 95

-- 4 0 5 6 5

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8

125--10 50 110-- 25 20 95

TEMPERATURE (C)

Figure 14. Latch Level (Vlatch)

NCP1396A, NCP1396B

TYPICAL CHARACTERISTICS -- A VERSION

1.045

1.040

1.035

VBO (V)

1.030

1.025

1.020

-- 4 0 5 5 0

TEMPERATURE (C)

Figure 15. Brown--Out Reference (VBO) Figure 16. Brown--Out Hysteresis Current (IBO)

26.8

26.6

26.4

26.2

26.0

25.8

IBO (mA)

25.6

25.4

25.2

25.0

95 110 65 80

125--10 35 80--25 20 65

-- 4 0 5 5 0

TEMPERATURE (C)

125--10 35 110-- 25 20 95

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9

NCP1396A, NCP1396B

V

Y

TYPICAL CHARACTERISTICS -- B VERSION

10.65

10.60

10.55

(V)

10.50

CC(on)

10.45

10.40

10.35

-- 4 0 5 5 0

TEMPERATURE (C)

Figure 17. V

60.1

60.0

59.9

(kHz)

59.8

59.7

59.6

FREQUENC

59.5

59.4

59.3

-- 4 0 5 6 5

35 80

TEMPERATURE (C)

CC(on)

9.56

9.54

9.52

9.50

9.48

(V)

9.46

CC(min)

9.44

V

9.42

9.40

9.38

9.36

95 110 65 80

125--10 35 80--25 20 65

125--10 50 110--25 20 95

-- 4 0 5 5 0

TEMPERATURE (C)

Figure 18. V

502

501

500

499

498

497

FREQUENCY (kHz)

496

495

-- 4 0 5 6 5

TEMPERATURE (C)

CC(min)

50 80

125--10 35 110-- 25 20 95

125--10 35 110--25 20 95

Figure 19. Fsw min Figure 20. Fsw max

29

27

25

23

21

RFB (kΩ)

19

17

15

-- 4 0 5 6 5

35 80

TEMPERATURE (C)

Figure 21. Pulldown Resistor (RFB)

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1.060

1.055

1.050

1.045

1.040

VrefFaultFF (V)

1.035

1.030

1.025

125--10 50 110--25 20 95

-- 4 0 5 6 5

35 80

TEMPERATURE (C)

125--10 50 110-- 25 20 95

Figure 22. Fast Fault (VrefFaultF)

10

NCP1396A, NCP1396B

TYPICAL CHARACTERISTICS -- B VERSION

19

18

17

16

15

14

ROH (Ω)

13

12

11

10

-- 4 0 5 5 0

TEMPERATURE (C)

Figure 23. Source Resistance (ROH) Figure 24. Sink Resistance (ROL)

108

107

106

105

104

103

102

DT_min (ns)

101

100

99

98

-- 4 0 5 6 5

35 80

TEMPERATURE (C)

8.0

7.5

7.0

6.5

6.0

5.5

ROL (Ω)

5.0

4.5

4.0

3.5

95 110 65 80

125--10 35 80--25 20 65

125--10 50 110--25 20 95

-- 4 0 5 5 0

TEMPERATURE (C)

294

293

292

291

290

289

288

DT_nom (ns)

287

286

285

284

-- 4 0 5 6 5

TEMPERATURE (C)

50 80

125--10 35 110-- 25 20 95

125--10 35 110--25 20 95

Figure 25. T_dead_min Figure 26. T_dead_nom

1.970

1.968

1.966

1.964

DT_max (ms)

1.962

1.960

1.958

-- 4 0 5 6 5

35 80 35 80

TEMPERATURE (C)

Figure 27. T_dead_max

3.980

3.975

3.970

3.965

3.960

3.955

3.950

Vlatch (V)

3.945

3.940

3.935

3.930

125--10 50 110--25 20 95

-- 4 0 5 6 5

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11

125--10 50 110-- 25 20 95

TEMPERATURE (C)

Figure 28. Latch Level (Vlatch)

NCP1396A, NCP1396B

TYPICAL CHARACTERISTICS -- B VERSION

1.050

1.045

1.040

VBO (V)

1.035

1.030

1.025

-- 4 0 5 5 0

TEMPERATURE (C)

Figure 29. Brown--Out Reference (VBO) Figure 30. Brown--Out Hysteresis Current (IBO)

107

106

105

104

103

IBO (mA)

102

101

100

99

95 110 65 80

125--10 35 80--25 20 65

-- 4 0 5 5 0

TEMPERATURE (C)

125--10 35 110-- 25 20 95

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12

NCP1396A, NCP1396B

Application Information

The NCP1396A/B includes all necessaryfeatures to help
building a rugged and safe switch--mode power supply
featuring an extremely low sta ndby power. The below
bullets detail the benefits brought by implementing the
NCP1396 controller:

 Wide frequency range: A high--speed Voltage

Control Oscillator allows an output frequency
excursion from 50 kHz up to 500 kHz on Mlower and
Mupper outputs.

 Adjustable dead--time: Thanks to a single resistor

wired to ground, the user has the ability to include
some dead --time, helping to fight cross--conduction
between the upper and the lower transistor.

 Adjustable soft--start: Every time the controller starts

to operate (power on), the switching frequency is
pushed to the programmed maximum value and slowly
moves down toward the minimum frequency, until the
feedback loop closes. The soft--start sequence is
activated in the following cases: a) normal startup
b) back to operation from an off state: during hiccup
faulty mode, brown--out or temperature shutdown
(TSD). In the NCP1396A, the soft--start is not
activated back to operation from the fast fault input,
unless the feedback pin voltage is below 0.6 V. To the
opposite, in the B version, the soft--start is always
activated back from the fast fault input whatever the
feedback level is.

 Adjustable minimum and maximum frequency

excursion: In resonant applications, it is important to
stay away from the resonating peak to keep operating
the converter in the right region. Thanks to a single
external resistor, the designer can program its lowest
frequency point, obtained in lack of feedback voltage
(during the startup sequence or in short--circuit
conditions). Internally trimmed capacitors offer a 3%
precision on the selection of the minimum switching
frequency. The adjustable upper stop being less
precise to 15%.

 Low startup current: When directly powered from

the high--voltage DC rail, the device only requires
300 mA t o start --up. In case of an a uxiliary supply, the
B version offers a lower start--up threshold to cope
with a 12 V dc rail.

 Brown--Out detection: To avoid operation from a low

input voltage, it is interesting to prevent the controller
from switching if the high-- voltage rail is not within
the right boundaries. Also, when teamed with a PFC
front--end circuitry, the brown-- out detection can
ensure a clean start--up sequence with soft--start,
ensuring that the PFC is stabilized before energizing
the resonant tank. The A version features a 26.5 mA
hysteresis current for the lowest consumption and the

B version slightly increases this current to 100 mAin
order to improve the noise immunity.

 Adjustable fault timer duration: When a fault is

detected on the slow fault input or when the FB path is
broken, a timer starts to charge an external capacitor.
If the fault is removed, the timer opens the charging
path and nothing happens. When the timer reaches its
selected duration (via a capacitor on pin 3), all pulses
are stopped. The controller now wait s for the
discharge via an external resistor of pin 3 capacitor to
issue a new clean startup sequence with soft--start.

 Cumulative fault events: In the NCP1396A/B, the

timer capacitor is not reset when the fault disappears.
It actually integrates the information and cumulates
the occurrences. A resistor placed in parallel with the
capacitor will offer a simple way to adjust the
discharge rate and thus the auto--recovery retry rate.

 Fast and slow fault detection: In some application,

subject to heavy load transients, it is interesting to
give a certain time to the fault circuit, before
activating the protection. On the other hands, some
critical faults cannot accept any delay before a
corrective action is taken. For this reason, the
NCP1396A/B includes a fast fault and a slow fault
input. Upon assertion, the fast fault immediately stops
all pulses and stays in the position as long as the
driving signal is high. When released low (the fault
has gone), the controller has several choices: in the A
version, pulses are back to a level imposed by the
feedback pin without soft--start, but in the B version,
pulses are back through a regular soft--start sequence.

 Skip c ycle possibility: The absence of soft--start on

the NCP1396A fast fault input offers an easy way to
implement skip cycle when power saving features are
necessary. A simple resistive connection from the
feedback pin to the fast fault input, and skip can be
implemented.

 Broken feedback loop detection: Upon start--up or

any time during operation, if the FB signal is missing,
the timer starts to charge a capacitor. If the loop is
really broken, the FB level does not grow--up before
the timer e nds counting. The controller then stops all
pulses and waits that the timer pin voltage collapses to
1 V typically before a new attempt to re --start, via the
soft--start. If the optocoupler is permanently broken, a
hiccup takes place.

 Finally, two circuit versions, A and B: The A and B

versions differ because of the following changes:

1. The sta rtup thresholds are different, the A starts
to pulse for V
for V
however. The A is recommended for consumer

= 10.5 V. The turn off levels are the same

CC

= 13.3 V whereas the B pulses

CC

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13

NCP1396A, NCP1396B

products where the designer can use an external
startup resistor, whereas the B is more
recommended for industrial / medical
applications where a 12 V auxiliary supply
directly powers the chip.

2. The A version does not activate the soft--start
upon release of the fast fault input. This is to let
the designer implement skip cycle. To the
opposite, the B version goes back to operation
upon the fast fault pin release via a soft--start
sequence.

Vdd

Vref

Rt

Rt sets
Fmin for V(FB) = 0

Imin

Cint

Voltage-- Controlled Oscillator

The VCO section features a high--speed circuitry
allowing operation from 100 kHz up to 1 MHz. However,
as a division by two internally creates the two Q and Q
outputs, the final effective signal on output Mlower and
Mupper switches between 50 kHz and 500 kHz. The VCO
is configured in such a way that if the fee dback pin goes up,
the switching frequency also goes up. Figure 31 shows the
architecture of this oscillator.

FBinternal

+

--

0toI_Fmax

+

max
Fsw

max

+

--

DSQ

Clk

R

Q

Vdd

Vref

DT

Rdt sets
the dead--time

V

CC

Fmax

Fmax sets
the maximum Fsw

FB

Rfb
20 k

Figure 31. The Simplified VCO Architecture

Imin

Vdd

The designer needs to program the maximum switching
frequency and the minimum switching frequency. In LLC
configurations, for circuits working above the resonant
frequency, a high precision is required on the minimum
frequency, hence the 3% specification. This minimum
switching frequency is actually reached when no feedback
closes the loop. It can happen during the startup sequence,
a strong output transient loading or in a short--circuit
condition. By installing a resistor from pin 4 to GND, the
minimum frequency is set. Using the same philosophy,

IDT

AB

Vb_off

+

--

+

Vfb < Vb_off
Start fault timer

wiring a resistor from pin 2 to GND will set the maximum
frequency excursion. To improve the circuit protection
features, we have purposely createda dead zone, wherethe
feedback l oop has no action. This is typically below 1.2 V.
Figure 32 details the arrangement where the internal
voltage (that drives the VCO) varies between 0 and 2.3 V.
However, to create this swing, the feedback pin (to which
the optocoupler emitter connects), will need to swing
typically between 1.2 V and 5.3 V.

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14

NCP1396A, NCP1396B

V

CC

FB

R1

11. 3 k

R3

100 k

R2

8.7 k

D1

2.3 V

Figure 32. The OPAMP Arrangement Limits the

VCO Modulation Signal between 0.5 and 2.3 V

This techniques allows us to detect a fault on the
converter in case the FB pin cannot rise above 0.6 V (to
actually close the loop) in less than a duration imposed by
the programmable timer. Please refer to the fault sectionfor
detailed operation of this mode.

As shown on Figure 32, the inte r nal dynamics of the
VCO control voltage will be constraine d between 0.5 V
and 2.3 V, whereas the feedback loop will drive pin 6 (FB)
between 1.2 V and 5.3 V. If we take the default FB pin
excursion numbers, 1.2 V = 50 kHz, 5.3 V = 500 kHz, then
the VCO maximum slope will be:

500 k − 50 k

4.1

= 109.7 kHz∕V

Figures 33 and 34 portray the frequency evolution
depending on the feedback pin voltage level in a different
frequency clamp combination.

F

Mu&Lu

Fmax

+

--

+

Vref

0.5 V

No variations

Fmax

Rfmax

500 kHz

F

Mu&Lu

No var iations

Fmax

Fmin

Fault
area

0.6 V

1.2 V

ΔVFB = 4.1 V

5.3 V

450 kHz

ΔFsw = 300 kHz

150 kHz

VFB

Figure 34. Here a different minimum frequency was

programmed as well as a maximum frequency

excursion

Please note that theprevious small--signal VCO slope has
now been reduced to 300 k / 4.1 = 73 kHz / V on Mupper
and Mlower outputs. This offers a mean to magnify the
feedback excursion on systems where the load range does
not generate a wide switching frequency excursion. Thanks
to this option, we will see how it becomes possible to
observe the feedback level and implement skip cycle at
light loads. It is important to note that the frequency
evolution does not have a real linear relationship with the
feedback voltage. This is due to the deadtime presence
which stays constant as the switching period changes.

The selection of the three setting resistors (Fmax, Fmin
deadtime) requires the usage of the selection charts
displayed below:

650

VCC=12V

550

450

FB = 6.5 V
DT = 300 ns

ΔFsw = 450 kHz

Fmin

Fault
area

0.6 V

1.2 V

ΔVFB = 4.1 V

5.3 V

Figure 33. Maximal Default Excursion, Rt =

22 kΩ on pin 4 and Rfmax = 1.3 kΩ on pin 2

50 kHz

VFB

350

250

Fmax (kHz)

150

50

Figure 35. Maximum Switching Frequency Resistor

Selection Depending on the Adopted Minimum

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15

Fmin = 200 kHz

Fmin = 50

1.5 3.5 5.5 7.5 9.5 11.5 13.5 15.5 17.5

RFmax (kΩ)

kHz

Switching Frequency

NCP1396A, NCP1396B

500

450

400

350

300

250

Fmin (kHz)

200

150

100

1357 911

RFmin (kΩ)

VCC=12V
FB = 1 V
DT = 300 ns

Figure 36. Minimum Switching Frequency Resistor

Selection (Fmin = 100 kHz to 500 kHz)

100

90

80

70

60

50

Fmin (kHz)

40

30

20

10 15 20 25 30 35 40 45 50 55

RFmin (kΩ)

VCC=12V
FB = 1 V
DT = 300 ns

Figure 37. Minimum Switching Frequency Resistor

Selection (Fmin = 20 kHz to 100 kHz)

ORing Capability

If for any particular reason, there is a need for a
frequency vari ation linked to an event appearance (instead
of abruptly stopping pulses), then the FB pin lends itself
very well to the addition of other sweeping loops. Several
diodescan easilybe usedperform thejob in case of reaction
to a fault event or to regulate on the output current (CC
operation). Figure 39 shows how to do it.

V

CC

In2

FBIn1

20 k

VCO

Figure 39. Thanks to the FB Configuration, Loop

ORing is Easy to Implement

Dead--time Control

Dead--time control is an absolute necessity when the
half--bridge configuration comes to play. The dead-- time
technique consists in inserting a period during which both
high and low side switches are off. Of course, the
dead--time amount differs depending on the switching
frequency, hence the ability to adjust it on this controller.
The option ranges between 100 ns a nd 2 ms. Thedead--time
is actually made by controlling the oscillator discharge
current. Figure 40 portrays a simplified VCO circuit based
on Figure 31.

2000
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000

900
800
700

DT (ns)

600
500
400
300
200
100

3.5 13.5 23.5 33.5 43.5 53.5 63.5 73.5 83.5
Rdt (kΩ)

Vcc = 12 V

Figure 38. Dead-- Time Resistor Selection

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16

Vdd

Icharge:
Fsw min + Fsw max

NCP1396A, NCP1396B

DT

RDT

Vref

Idis

Ct

DSQ

Clk

+

+

--

3V--1V

Figure 40. Dead-- time Generation

Q

R

AB

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17

NCP1396A, NCP1396B

During the discharge time, the clock comparator is high
and un--validates the AND gates: both outputs are low.
When the comparator goes back to the low level, during the
timing capacitor Ct recharge time, A and B outputs are
validated. By connecting a resistor RDT to ground, it
creates a current whose image serves to discharge the Ct
capacitor: we control the dead-- time. The typical range
evolves between 100 ns (RDT = 3.5 kΩ) and 2 ms(RDT=

83.5 kΩ). Figure 43 shows the typical waveforms.

Soft--start Sequence

In resonant controllers, a soft--start is needed to avoid
suddenly applying the full current into the resonating
circuit. In this controller, a soft--start capacitor connects to
pin 1 and offers a smooth frequency variation upon
start--up: when the circuit starts to pulse, the VCO is pushed
to the maximum switching frequency imposed by pin 2.
Then, it linearly decreases its frequency toward the
minimum frequency selected by a resistor on pin 4. Of
course, practically, the feedback loop is suppose to take

20.0

10.0

--10.0

Ires1 in Amperes

--20.0

0

SS
Action

Plot1

overthe VCOlead assoonas the output voltage has reached
the target. If not, then the minimum switching frequency is
reached and a fault is detected on the feedback pin
(typically below 600 mV). Figure 41 depicts a typical
frequency evolution with soft--start.

Fsw

Fmax

If no FB
Action

Fmin

Vss

Soft-- start Duration

Figure 41. Soft-- start Behavior

Ires

177

175

173

Plot2

171

Vout in Volts

169

Figure 42. A Typical Start-- up Sequence on a LLC Converter

Target is
Reached

600 m200 m

time in seconds

Please note that the soft--start will be activated in the
following conditions:

-- A startup sequence

-- During auto-- recovery burst mode

-- A brown--out recovery

-- A temperature shutdown recovery

The fast fault input undergoes a special treatment. Since
we want to implement skip cycle through the fast fault
input on the NCP1396A, we cannot activate the soft--start
every time the feedback pin stops the operations in low
power mode. Therefore, when the fast fault pin is released,

Vout

1.00 m 1.40 m 1.80 m

no soft--start occurs to offer the best skip cycle behavior.
However, it is very possible to combine skip cycle and true
fast fault input, e.g. via ORing diodes driving pin 6. In that
case, if a signal maintains the fast fault input high long
enough to bring the feedback level down (that is to say
below 0.6 V) sinc e the output voltage starts to fall down,
then the soft-- start is activated after the release of the pin.
In the B version tailored to operate from an auxiliary 12 V
power supply, the soft--start is always activated upon the
fast fault input release, whatever the feedback condition is.

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NCP1396A, NCP1396B

4.00

3.00

2.00

Plot1

Vct in Volts

1.00

0

16.0

12.0

8.00

Plot2

4.00

Clock in Volts

0

Ct Voltage

Clock Pulses

DT

8.00

4.00

0

Plot3

--4.00

Difference in Volts

--8.00

A--B

56.2 m 65.9 m 75.7 m 85.4 m 95.1 m

DT

Figure 43. Typical Oscillator Waveforms

Brown--Out Protection

The Brown-- Out circuitry(BO) offers a way toprotect the
resonant converter from low DC input voltages. Below a
given level, the controller blocks the output pulses, above
it, it authorizes them. The internal circuitry, depicted by
Figure 44, offers a way to observe the high--voltage (HV)
rail. A resistive divider made of Rupper and Rlower, brings
a portion of the HV rail on pin 5. Be low the turn--on level,
the 26.5 mA current source IBO is off. Therefore, the
turn--on level solely depends on t he division ratio brought
by the resistive divider.

time in seconds

Figure 44. The Internal Brown-- out Configuration with

DT

Vbulk

Rupper

Rlower

Vdd

IBO

BO

an Offset Current Source

ON/OFF

+

VBO

+

--

BO

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19

450

16.0

NCP1396A, NCP1396B

351 Volts

350

12.0

250

8.0

Vcmp in Volts

Plot1 Vin in Volts

150

4.0

50

0

Vin

BO

20 m 60 m 100 m 140 m 180 m

time in seconds

Figure 45. Simulation Results for 350 / 250 ON / OFF Levels

To the contrary, when t he internal BO signal is high
(Mlower and Mupper pulse), the IBO source is acti vated
and creates a hysteresis. As a result, it becomes possible to
select the turn--on and turn--off levels via a few lines of
algebra:

IBO is off

R

V(+) = V

bulk1

×

R

lower

lower

+ R

upper

(eq. 1)

IBO is on

(eq. 2)

R

V(+) = V

bulk2

R

R

lower

lower

+ R

upper

+ IBO ×

×



R

lower

lower

× R

+ R

upper

upper

We can nowextract Rlower from equation1 and plug it into
equation 2, then solve for Rupper:

− VBO

V

bulk1

×

V

bulk1

IBO × (V

VBO

− V

bulk1

bulk2

− VBO)

(eq. 3)

(eq. 4)

R

lower

R

upper

= VBO ×

= R

lower

250 Volts

If we decide to turn--on our converter for Vbulk1 equals
350 V and turn it off for Vbulk2 equals 250 V, then for A
version (IBO_A = 26.5 m A, VBO = 1.04 V) we obtain:

Rupper = 3.77 MΩ

Rlower = 11.25 kΩ

2

The bridge power dissipation is 400

/ 3.781 MΩ =42 mW

when front-- end PFC stage delivers 400 V.

Figure 45 simulation result confirms our calculations.

Latch --off Protection



There are some situations where the converter shall be
fully turned--off and stay latched. This can ha ppen in
presence of an over--voltage (the feedback loop is drifting)
or when an over temperature is detected. Thanks to the
addition of a comparator on the BO pin, a simple external
circuit can lift up this pin above VLATCH (4 V typical) and
permanently disable pulses. The V

needs to be cycled

CC

down below 6.5 V typically to reset the controller.

CC

Q1

Vout

NTC

VbulkV

Rupper

Rlower

BO

+

VBO

+

--

+

Vlatch

IBO

+

--

20 ms

RC

To permanent
latch

Vdd

BO

Figure 46. Adding a comparator on the BO pin offers a way to latch--off the controller

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20

NCP1396A, NCP1396B

On Figure 46, Q1 is blocked and does not bother the BO
measurement as long as the NTC and the optocoupler are
not activate d. As soon as the secondary optocoupler senses
an OVP condition, or the NTC reacts to a high ambient
temperature, Q1 base is brought to ground and the BO pin
goes up, permanently latching off the cont roller.

Protection Circuitry

This resonant controller differs from competitors thanks
to its protection features. The device can react to various
inputs like:

-- Fast events input: like an over--current condition, a

need to shut down (sleep mode) or a way to force a
controlled burst mode (skip cycle at low output
power): as soon as the input level exceeds 1 V typical,

Vdd

Itimer

UVLO

Reset

+

+

--

1 = fault
0=ok

ON/OFF

Vref Fault

pulses are immediately stopped. When the input is
released, the controller performs a clean startup
sequence including a soft--start period.

-- Slow events input: this input serves as a delayed
shutdown, where an event like a transient overload
does not immediately stopped pulses but start a timer.
If the e vent duration lasts longer than what the timer
imposes, then all pulses are disabled. The voltage on
the timer capacitor (pin 3) starts to decrease until it
reaches 1 V. The decrease rate is actually depending
on the resistor the user will put in parallel with the
capacitor, giving another flexibility during design.

Figure 47 depicts the architecture of the fault circuitry.

Ctimer

+

--

+

Ctimer

Rtimer

Slow Fault

Average

Input

Current

To P r im ar y
Current Sensing
Circuitry

Reset

VtimerON

VtimerOFF

DRIVING

LOGIC

1=ok
0 = fault

Vref Fault

SS

-­+

+

1=ok
0 = fault

Figure 47. This circuit combines a slow and fast input for improved protection features

Slow Input

On this circuit, the slow input goes to a comparator.

When this input exceeds 1 V typical, the current source

V

CC

FB

FB

Fast Fault

A

B

A

B

Skip

Itimer turns on, charging the external capacitor Ctimer. If
the fault duration is long enough, when Ctimer voltage

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21

NCP1396A, NCP1396B

reaches the VtimerON level (4 V typical), then all pulses
are stopped. If the fault input signal is still present, then the
controller permanently stays off and the voltage on the
timer capacitor does not move (Itimer is on and thevoltage
is cla mped to 5 V). If the fault input signal is removed
(because pulses are off for instance), Itimer turns off and
the capacitor slowly discharges t o ground via a resistor
installed in parallel with it. As a result, the designer can
easily determine the time during which the power supply
stays locked by playing on Rtimer. Now, when the timer
capacitor voltage reaches 1 V typical (VtimerOFF), the
comparatorinstructs the internal logicto issues pulses ason
a clean soft--start sequence (soft--start is activated). Please
note that the discharge resistor can not be lower than 4 V

SMPS Stops

Fault is Gone

/ Itimer otherwise the voltage on Ctimer will not reach the
turn--off voltage of 4 V.

In both cases, when the fault is validate d, both outputs

Mlower and Mupper are internally pulled down to ground.

On Figure 46 example, a voltage proporti onal to primary
current, once averaged, gives an ima ge of the input power
in case Vin is kept constant via a PFC circuit. If the output
loading increases above a certain level, the voltage on this
pin will pass the 1 V threshold a nd start the timer. If the
overload stays there, after a few tens of milli--seconds,
switching pulses will disappear and a protective
auto--recovery cycle will take place. Adjusting the resistor
R in parallel with the timer capacitor will give the
flexibility to adjust the fault burst mode.

4V

SMPS Re--starts

Figure 48. A resistor can easily program the capacitor discharge time

V

CC

FB

Fast Fault

Figure 49. Skip cycle can be implemented via two

resistors on the FB pin to the Fast fault input

Fast Input

The fast input is not affected bya delayed action. As soon
as its voltage exceeds 1 V typical, all pulses are off and
maintained off as long as the fault is present. When the pin
is released, pulsescome backand the soft--start isactivated.

Thanks to the low activation level of 1 V, this pin can
observe the feedback pin via a resistive divided and thus
implement skip cycle operation. The resonant converter

1V

ResetatRe--start

can be designed to lose regulation in light load conditions,
forcing the FB level to increase. When it reaches the
programmed level, it triggers t he fast fault input and stops
pulses. Then Vout slowly drops, the loop reacts by
decreasing the feedback level which, in turn, unlocks the
pulses, Vout goes up again and so on: we are in skip cycle
mode.

Startup Behavior

When the VCCvoltage grows--up, the internal current
consumption is kept to Istrup, allowing to cra nk--up the
converter via a resistor connected to the bulk capacitor.
When V

reaches the V

CC

level, output Mlower goes

CC(on)

high first and then output Mupper. This sequence will
always be the same whatever triggers the pulse delivery:
fault, OFF to ON etc Pulsing the output Mlower highfirst
gives an immediate charge of the bootstrap capacitor.
Then, the re st of pulses follow, delivered at the highest
switching value, set by the resistor on pin 2. The soft--start
capacitor ensures a smooth frequencydecrease toeither the
programmed minimum value (in case of fault) or to a value
corresponding to the operating point if the feedback loop
closes first. Figure 50 shows typical signals evolution at
power on.

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22

V

CC(on)

V

CC(min)

NCP1396A, NCP1396B

Vcc from an auxiliary supply

SS

FB

A&B

Timer

0.6 V

4V

1V

A B

A B

T

SS

Slopes are similar

Fault!

A B

A B

T

SS

Figure 50. At power on, output A is first activated and the frequency slowly decreases via the soft--start capacitor

Figure 50 depicts an auto --recovery situation, where the

timer has triggeredthe endof outputpulses. Inthat case,the

level was given by an auxiliary power supply, hence

V

CC

its stability during the hiccup. A similar situation can arise
if the user selects a more traditional startup method, with
an auxiliary winding. In that case,the V

CC(min)

comparator

say, when V

pin still receives its bias current from the startup

V

CC

resistor and heads toward V
When the voltage reaches V
takes place, involving a soft--start. Figure 51 portrays this
behavior.

falls below 10 V typical. At this time, the

CC

via the VCCcapacitor.

CC(on)

, a standard sequence

CC(on)

stops the output pulses whenever it is activa ted, that is to

V

CC(on)

V

CC(min)

SS

VCCfrom a

Startup Resistor

Fault!

Fault is
Released

FB

A&B

Timer

0.6 V

4V

1V

A B

A B

T

SS

A B

A B

T

SS

Figure 51. When the VCCis too low, all pulses are stopped until VCCgoes back to the startup voltage

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23

NCP1396A, NCP1396B

As described in the data--sheet, two startup levels

V

CC(on)

are available, via two circuit versions. The
NCP1396 features sufficient hysteresis (3 V typic ally) to
allow a classical startup method with a resistor connected
to the bulk capacitor. Then, at the end of the startup
sequence, an auxiliary winding is supposed to take over the
controller supply voltage. To the opposite, for applications
where the re sonant controller is powered from a standby
power supply, the startup level is 10 V typically and allows

Fault

B

A

Pulse

Trigger

Delay

Level

Shifter

for the direct a connection from a 12 V source. Thanks to
this NCP1396B, simple ON/OFF operation is therefore
feasible.

The High--voltage Driver

The driver features a tra ditional bootstrap circuitry,
requiring an external high--voltage diode for the capacitor
refueling path. Figure 52 shows the internal arc hitecture of
the high--voltage section.

HV

Vboot

S

Q

Q

R

UVLO

Mupper

HB

V

CC

Mlower

GND

cboot

dboot

aux
V

CC

+

Figure 52. The Internal High-- voltage Section of the NCP1396

The device incorporates an upper UVLO circuitry that
makes sure enough Vgs is available for the upper side
MOSFET. The B and A outputs are delivered by the
internal logic, as Figure 47 testifies. A delay is inserted in

As stated in the maximum rating section, the floating
portion can go up to 600 VDC and makes the IC perfectly
suitable for offline applications featuring a 400 V PFC
front--end stage.

the lower rail to ensure good matching between these
propagating signals.

ORDERING INFORMATION

Device Package Shipping†

NCP1396ADR2G SOIC--16, Less Pin 13

(Pb--Free)

NCP1396BDR2G SOIC--16, Less Pin 13

(Pb--Free)

†For information on tape and reelspecifications, including part orientation and tapesizes, please refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

2500 / Tape & Reel

2500 / Tape & Reel

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24

NCP1396A, NCP1396B

a

PACKAGE DIMENSIONS

SOIC--16 NB, LESS PIN 13

CASE 751AM --01

ISSUE O

M

0.25 B

16 9

D

A B

H

18

M

SEATING

C

PLANE

15X

e

b 15X

0.25 A

A1

A

SOLDERING FOOTPRINT*

15X

0.58

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL BE

0.13 TOTAL IN EXCESS OF THE b DIMENSION AT

E

C

L

M

S

S

B

T

x45

h

_

M

MAXIMUM MATERIAL CONDITION.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSIONS.

5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

MILLIMETERS

DIM MIN MAX

A 1.35 1.75

A1 0.10 0.25

b 0.35 0. 49
C 0.19 0.25
D 9.80 10.00
E 3.80 4. 00
e 1.27 BSC
H 5.80 6.20
h 0.25 0. 50
L 0.40 1. 25

M 07

__

6.40

15X

1.12

1

16

1.27

PITCH

89

DIMENSIONS: MILLIMETERS

*For additional information on our Pb--Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Indus tries, LLC (SCILLC). SCILLC reserves the right tomake changes without furthernotice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the s uitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or us e of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specificati ons can and do vary in different applications and actual performance may vary over
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