Datasheet NCP1234AD65R2G Specification

NCP1234

Fixed Frequency Current
Mode Controller for Flyback
Converters

The NCP1234 is a new fixed−frequency current−mode controller
featuring Dynamic Self−Supply (DSS). This device is pin−to−pin
compatible with the previous NCP12xx families.

The DSS function greatly simplifies the design of the auxiliary
supply and the V
source to supply the controller during transients.

Due to frequency foldback, the controller exhibits excellent
efficiency in light load condition while still achieving very low
standby power consumption. Internal frequency jittering, ramp
compensation, and a versatile latch input make this controller an
excellent candidate for converters where components cost is the key
constraints.

It features a timer−based fault detection that ensures the detection of
overload independently of an auxiliary winding, and an adjustable
compensation to help keep the maximum power independent of the
input voltage.

Finally, due to a careful design, the precision of critical parameters
is well controlled over the entire temperature range (−40°C to
+125°C).

Features

• Fixed−Frequency Current−Mode Operation with Built−In Ramp

Compensation

• 65 kHz or 100 kHz Oscillator Frequency version

• Frequency Foldback then Skip Mode for Maximized Performance in

Light Load and Standby Conditions

• Timer−Based Overload Protection with Latched (option A) or

Auto−Recovery (option B) Operation

• High−voltage Current Source with Dynamic Self−Supply,

Simplifying the Design of the V

• Frequency Modulation for Softened EMI Signature, including during

Frequency Foldback mode

• Adjustable Overpower Compensation

• Latch−off Input for Severe Fault Conditions, Allowing Direct

Connection of an NTC for Overtemperature Protection (OTP)

• V

Operation up to 28 V, with Overvoltage Detection

CC

• ±500 mA Peak Source/Sink Current Drive Capability

• 4.0 ms Soft−Start

• Internal Thermal Shutdown

• Pin−to−Pin Compatible with the Existing NCP12xx

Series

• These Devices are Pb−Free, Halogen Free/BFR Free

and are RoHS Compliant

capacitor by activating the internal startup current

CC

Capacitor

CC

Typical Applications

• AC−DC Adapters for Notebooks, LCD, and Printers

• Offline Battery Chargers

• Consumer Electronic Power Supplies

• Auxiliary/Housekeeping Power Supplies

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SOIC−7

CASE 751U

MARKING DIAGRAM

8

34Xff

ALYWX

G

1

34Xff = Specific Device Code

X = A or B

ff = 65 or 100
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package

PIN CONNECTIONS

Latch

18

FB

2
3

CS

GND

4

(Top View)

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 32 of this data sheet.

HV

V

6

CC

DRV

5

© Semiconductor Components Industries, LLC, 2016

January , 2016 − Rev. 2

1 Publication Order Number:

NCP1234/D

NCP1234

TYPICAL APPLICATION EXAMPLE

VIN

(dc)

LATCH

CS

GND

FB

NCP1234

HV

VCC
DRV

Figure 1. Flyback Converter Application Using the NCP1234

PIN FUNCTION DESCRIPTION

Pin No Pin Name Function Pin Description

1 LATCH Latch−Off Input Pull the pin up or down to latch−off the controller. An internal current source

2 FB Feedback An optocoupler collector to ground controls the output regulation.
3 CS Current Sense This Input senses the Primary Current for current−mode operation, and Offers

4 GND IC Ground
5 DRV Drive output Drives external MOSFET
6 V

CC

VCC input This supply pin accepts up to 28 Vdc, with overvoltage detection

allows the direct connection of an NTC for over temperature detection

an overpower compensation adjustment.

VOUT

8 HV High−voltage pin Connects to the bulk capacitor or the rectified AC line to perform the functions

of Start−up Current Source and Dynamic Self−Supply

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2

I

NTC

NCP1234

SIMPLIFIED INTERNAL BLOCK SCHEMATIC

V

DD

I

NTC

+

−

+

V

OVP

blanking

t

Latch(OVP)

HV

HV

Latch

FB

CS

1 kW

V

FB(ref)

20 kW

HV sample

V

clamp

I

OPC

(V

V

V to I
= 0.5m x

− 125)

HV

FB(OPC)

+

−

blanking

t

LEB

blanking

t

BCS

−

+

+

V

OTP

Soft−start
end

blanking

t

Latch(OTP)

S

Q

Latch

R

TSD

UVLO

VDD

IC Start

Reset
UVLO
V

DD

Start

TSD

HV currentTSD

V

CC

management

Dual HV
start−up
current source

Reset

V

−

+

+

V

skip

/ 5

slope

comp.

PWM

+

−

Soft−start

+

−

+

Soft−start ramp

End

t

SSTART

Start

Reset

IC Start
IC Stop

Soft−start end

Sawtooth

Stop

Oscillator

Jitter

Foldback

Clamp

S

Q

R

+

−

+

I

V

ILIM

LIMIT

IC stop

CC

DRV

GND

I

LIMIT

+

−

S

Fault Flag

Q

R

+

V

CS(stop)

Protection

Mode
release

For
Autorecovery
protection
mode only

Latch
TSD

UVLO

timer

PWM

timer

t

fault

Fault

t

autorec

Reset

Figure 2. Simplified Internal Block Schematic

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3

NCP1234

MAXIMUM RATINGS

Rating Symbol Value Unit

Supply Pin (pin 6) (Note 2)

Voltage range
Current range

High Voltage Pin (pin 8) (Note 2)

Voltage range
Current range

Driver Pin (pin 5) (Note 2)

Voltage range
Current range

All other pins (Note 2)

Voltage range

Current range

Thermal Resistance SOIC−7

Junction−to−Air, low conductivity PCB (Note 3)
Junction−to−Air, medium conductivity PCB (Note 4)
Junction−to−Air, high conductivity PCB (Note 5)

Temperature Range

Operating Junction Temperature
Storage Temperature Range

ESD Capability (Note 1)

Human Body Model (All pins except HV)
Machine Model

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.

1. This device series contains ESD protection and exceeds the following tests:
Human Body Model 2000 V per JEDEC standard JESD22, Method A114E
Machine Model Method 200 V per JEDEC standard JESD22, Method A115A

2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78

3. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 50 mm
for a JEDEC 51−1 conductivity test PCB. Test conditions were under natural convection or zero air flow.

4. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 100 mm
for a JEDEC 51−2 conductivity test PCB. Test conditions were under natural convection or zero air flow.

5. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 650 mm

2

of 2 oz copper traces and heat spreading area. As specified

2

of 2 oz copper traces and heat spreading area. As specified

2

of 2 oz copper traces and heat spreading area. As specified

for a JEDEC 51−3 conductivity test PCB. Test conditions were under natural convection or zero air flow.

V

CCMAX

I

CCMAX

V

HVMAX

I

HVMAX

V

DRVMAX

I

DRVMAX

V

MAX

I

MAX

R

θ

J−A

T

JMAX

T

STRGMAX

–0.3 to 28

±30

–0.3 to 500

±20

–0.3 to 20

±1000

–0.3 to 10

±10

162
147

115

−40 to +150

−60 to +150

2000

200

V

mA

V

mA

V

mA

V

mA

°C/W

°C

V

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4

NCP1234

ELECTRICAL CHARACTERISTICS (For typical values T

V

= 11 V unless otherwise noted)

CC

= 25°C, for min/max values TJ = −40°C to +125°C, VHV = 125 V,

J

Characteristics Test Condition Symbol Min Typ Max Unit

HIGH VOLTAGE CURRENT SOURCE

Minimum voltage for current
source operation

Current flowing out of VCC pin VCC = 0 V

V

CC

= V

CC(on)

− 0.5 V

Off−state leakage current VHV = 500 V I

V

HV(min)

I

start1

I

start2

start(off)

SUPPLY

Turn−on threshold level, V
going up

CC

V

CC(on)

HV current source stop threshold
HV current source restart

threshold
Turn−off threshold V
Overvoltage threshold V
Blanking duration on V

V

detection

CC(ovp)

CC(off)

and

VCC decreasing level at which
the internal logic resets

VCC level for I
transition

Internal current consumption
(Note 6)

START1

to I

START2

DRV open, VFB = 3 V, 65 kHz
DRV open, VFB = 3 V, 100 kHz
C

= 1 nF, VFB = 3 V, 65 kHz

drv

= 1 nF, VFB = 3 V, 100 kHz

C

drv

Off mode (skip or before start−up)
Fault mode (fault or latch)

V

CC(min)

CC(off)

CC(ovp)

t

VCC(blank)

V

CC(reset)

V

CC(inhibit)

I

CC1

I

CC1

I

CC2

I

CC2

I

CC3

I

CC4

OSCILLATOR

Oscillator frequency

Maximum duty cycle D
Frequency jittering amplitude, in

percentage of F

OSC

Frequency jittering modulation
frequency

f

A

F

OSC

MAX

jitter

jitter

OUTPUT DRIVER

Rise time, 10% to 90 % of V
Fall time, 90% to 10 % of V

CC

CC

VCC = V
VCC = V

Current capability VCC = V

DRV high, V
DRV low, V

Clamping voltage (maximum
gate voltage)

High−state voltage drop

VCC = V

= 33 kW, C

R

DRV

VCC = V
DRV high

+ 0.2 V, C

CC(min)

+ 0.2 V, C

CC(min)

+ 0.2 V, C

CC(min)

= 0 V

DRV

= V

DRV

CC

– 0.2 V, DRV high,

CCmax

CC(min)

load

+ 0.2 V, R

DRV
DRV
DRV

= 220 pF

DRV

= 1 nF t
= 1 nF t
= 1 nF

I

DRV(source)

I

DRV(sink)

V

DRV(clamp)

= 33 kW,

V

DRV(drop)

rise

fall

6. internal supply current only, current in FB pin not included (current flowing in GND pin only).

− 30 40 V

0.2
3

0.5
6

9

0.8

− 25 50

11.0 12.0 13.0 V

9.5 10.5 11.5 V

8.5 9.5 10.5 V
25 26.5 28 V

7 10 13

3.6 5.0 6.0 V

0.4 1.0 1.6 V

1.2

1.3

1.9

2.2

0.67

0.4

60
92

1.8

1.9

2.5

2.9

0.9

0.7

65

100

2.2

2.3

3.2

3.6

1.13

1.0

70

108
75 80 85 %
±4 ±6 ±8 %

85 125 165 Hz

− 40 70 ns

− 40 70 ns

−

−

500
500

−

−

11 13.5 16 V

− − 1 V

mA

mA

ms

mA

kHz

mA

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5

NCP1234

ELECTRICAL CHARACTERISTICS (For typical values T

V

= 11 V unless otherwise noted)

CC

Characteristics

Test Condition Symbol Min Typ Max Unit

= 25°C, for min/max values TJ = −40°C to +125°C, VHV = 125 V,

J

FEEDBACK

Internal pull−up resistor

TJ = 25°C R

VFB to internal current setpoint
division ratio

Internal pull−up voltage on the
FB pin

CURRENT SENSE

Input Bias Current
Maximum internal current

VCS = 0.7 V I
VFB > 3.5 V V

setpoint
Propagation delay from V

detection to DRV off

Ilimit

VCS = V

ILIM

Leading Edge Blanking Duration
for V

ILIM

Threshold for immediate fault
protection activation

Leading Edge Blanking Duration
for V

CS(stop)

Slope of the compensation ramp S

Soft−start duration From 1st pulse to VCS = V

ILIM

OVERPOWER COMPENSATION

to I

V

HV

conversion ratio K

OPC

Current flowing out of CS pin VHV = 125 V

V

= 162 V

HV

VHV = 325 V
VHV = 365 V

FB voltage above which I
applied

FB voltage below which is no
I

applied

OPC

OPC

is

VHV = 365 V V

VHV = 365 V V

Watchdog timer for dc operation t
HV sampling level V

OVERCURRENT PROTECTION

Fault timer duration

From CS reaching V

to DRV stop t

ILIMIT

Autorecovery mode latch−off
time duration

FREQUENCY FOLDBACK

Feedback voltage threshold
below which frequency foldback
starts

Feedback voltage threshold
below which frequency foldback
is complete

Minimum switching frequency VFB = V

+ 0.2 f

skip(in)

SKIP−CYCLE MODE

Feedback voltage thresholds for
skip mode

VFB going down
V

going up

FB

FB(up)

K

FB

V

FB(ref)

bias

ILIM

t

delay

t

LEB

V

CS(stop)

t

BCS

comp(65kHz)

S

comp(100kHz)

t

SSTART

OPC

I

OPC(125)

I

OPC(162)

I

OPC(325)

I

OPC(365)

FB(OPCF)

FB(OPCE)

WD(OPC)

HVsample

fault

t

autorec

V

FB(foldS)

V

FB(foldE)

OSC(min)

V

skip(in)

V

skip(out)

15 20 25

4.7 5 5.3 −

4.3 5 5.7 V

− 0.02 −

0.66 0.7 0.74 V

− 80 110 ns

190 250 310 ns

0.95 1.05 1.15 V

90 120 150 ns

−

−32.5

−

−50

−

mV /

−

2.8 4.0 5.2 ms

− 0.54 −

−

−

−

105

0

20

110

130

150

mA / V

−

−

−

2.12 2.35 2.58 V

− 2.15 − V

− 32 − ms

− 92 − V

98 128 168 ms

0.85 1.00 1.35 s

1.8 2.0 2.2 V

1.22 1.35 1.48 V

22 27 32 kHz

0.63

0.72

0.7

0.80

0.77

0.88

kW

mA

ms

mA

V

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6

NCP1234

ELECTRICAL CHARACTERISTICS (For typical values T

V

= 11 V unless otherwise noted)

CC

Characteristics UnitMaxTypMinSymbolTest Condition

LATCH−OFF INPUT

V

High threshold
Low threshold V
Current source for direct NTC

connection

During normal operation
During soft−start

Blanking duration on high latch
detection

Blanking duration on low latch
detection

Clamping voltage I

TEMPERATURE SHUTDOWN

Temperature shutdown
Temperature shutdown

hysteresis

going up V

Latch

going down V

Latch

V

= 0 V

Latch

65 kHz version
100 kHz version

= 0 mA

Latch

I

= 1 mA

Latch

TJ going up T
TJ going down T

= 25°C, for min/max values TJ = −40°C to +125°C, VHV = 125 V,

J

OVP
OTP

I

NTC

I

NTC(SSTART)

t

Latch(OVP)

t

Latch(OTP)

V

clamp0(Latch)

V

clamp1(Latch)

TSD

TSD(HYS)

2.35 2.5 2.65 V

0.76 0.8 0.84 V

65

130

35
25

95

190

50
35

105

210

70
45

− 350 −

1.0

2.0

1.2

2.4

1.4

3.0

135 150 165 °C

20 30 40 °C

mA

ms

ms

V

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7

NCP1234

40.00

V

(V)

35

5

V

(V)

5

t

(ns)

delay

LEB

5

TYPICAL PERFORMANCE CHARACTERISTICS

38.00

36.00

34.00

32.00

30.00

HV(min)

28.00

26.00

24.00

22.00

20.00

−50 −25 0 25 50 75 100 125
TEMPERATURE (°C)

Figure 3. Minimum Current Source Operation

V

HV(min)

0.75

0.74

0.73

0.72

0.71

0.70

ILIM

0.69

0.68

0.67

0.66

0.65

−50 −25 0 25 50 75 100 125
TEMPERATURE (°C)

Figure 5. Maximum Internal Current Setpoint

V

ILIM

30

25

20

(V)

15

start(off)

I

10

5

0

−50 −25 0 25 50 75 100 12
TEMPERATURE (°C)

Figure 4. Off−State Leakage Current I

1.15

1.13

1.11

1.09

1.07

(V)

1.05

1.03

CS(stop)

V

1.01

0.99

0.97

0.95

−50 −25 0 25 50 75 100 12

TEMPERATURE (°C)

Figure 6. Threshold for Immediate Fault

Protection Activation V

CS(stop)

start(off)

110

100

90

80

70

delay

60

50

40

−50 −25 0 25 50 75 100 125
TEMPERATURE (°C)

Figure 7. Propagation Delay t

300
290
280
270
260

(ns)

250

LEB

t

240
230
220
210
200

−50 −25 0 25 50 75 100 12

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8

TEMPERATURE (°C)

Figure 8. Leading Edge Blanking Duration t

NCP1234

TYPICAL PERFORMANCE CHARACTERISTICS

24
23
22
21
20

(kW)

19

FB(up)

R

18
17
16
15

−50 −25 0 25 50 75 100 125
TEMPERATURE (°C)

Figure 9. FB Pin Internal Pull−up Resistor

R

FB(up)

70
69
68
67
66
65

(kHz)

64

OSC

f

63
62
61
60

−50 −25 0 25 50 75 100 125
TEMPERATURE (°C)

Figure 11. Oscillator Frequency f

OSC

5.30

5.20

5.10

5.00

(V)

4.90

FB(ref)

V

4.80

4.70

4.60

−50 −25 0 25 50 75 100 125
TEMPERATURE (°C)

Figure 10. FB Pin Open Voltage V

85
84
83
82
81

(%)

80

MAX

79

D

78
77
76
75

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

FB(ref)

Figure 12. Maximum Duty Cycle D

MAX

2.20

2.15

2.10

2.05

(V)

2.00

FB(foldS)

1.95

V

1.90

1.85

1.80

−50 −25 0 25 50 75 100 125
TEMPERATURE (°C)

Figure 13. FB Pin Voltage Below Which

Frequency Foldback Starts V

FB(foldS)

1.50

1.45

1.40

(V)

1.35

FB(foldE)

V

1.30

1.25

1.20

−50 −25 0 25 50 75 100 125

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9

TEMPERATURE (°C)

Figure 14. FB Pin Voltage Below Which

Frequency Foldback is Complete V

FB(foldE)

NCP1234

0.77

V

(V)

0.88

5

f

(kHz)

5

V

(V)

5

TYPICAL PERFORMANCE CHARACTERISTICS

0.75

0.73

0.71

0.69

skip(in)

0.67

0.65

0.63

−50 −25 0 25 50 75 100 125
TEMPERATURE (°C)

Figure 15. FB Pin Skip−in Level V

30
29
28
27
26
25
24

OSC(min)

23
22
21
20

−50 −25 0 25 50 75 100 125
TEMPERATURE (°C)

skip(in)

Figure 17. Minimum Switching Frequency

f

OSC(min)

2.60

2.55

2.50

2.45

2.40

2.35

2.30

FB(OPCF)

2.25

2.20

2.15

2.10

−50 −25 0 25 50 75 100 125
TEMPERATURE (°C)

Figure 19. FB Pin Level V

FB(OPCF)

Above

Which is the Overpower Compensation

Applied

0.86

0.84

0.82

(V)

0.80

skip(out)

0.78

V

0.76

0.74

0.72

−50 −25 0 25 50 75 100 12
TEMPERATURE (°C)

Figure 16. FB Pin Skip−Out Level V

150
145
140
135

(mA)

130
125

OPC(365)

I

120

115
110

−50 −25 0 25 50 75 100 12

TEMPERATURE (°C)

Figure 18. Maximum Overpower

Compensating Current I

OPC(365)

Flowing Out

of CS Pin

2.40

2.35

2.30

2.25

2.20

(V)

2.15

2.10

FB(OPCE)

V

2.05

2.00

1.95

1.90

−50 −25 0 25 50 75 100 12
TEMPERATURE (°C)

Figure 20. FB Pin Level V

FB(OPCE)

Which is No Overpower Compensation

Applied

skip(out)

Below

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10

NCP1234

2.65

V

(V)

0.85

5

V

(V)

5

I

(

A)

5

TYPICAL PERFORMANCE CHARACTERISTICS

2.60

2.55

2.50

OVP

2.45

2.40

2.35

−50 −25 0 25 50 75 100 125
TEMPERATURE (°C)

Figure 21. Latch Pin High Threshold V

1.34

1.32

1.30

1.28

1.26

clamp0

1.24

OVP

0.84

0.83

0.82

0.81

(V)

0.80

OTP

0.79

V

0.78

0.77

0.76

0.75

−50 −25 0 25 50 75 100 12
TEMPERATURE (°C)

Figure 22. Latch Pin Low Threshold V

2.80

2.70

2.60

2.50

(V)

2.40

clamp1

2.30

V

OTP

1.22

1.20

1.18

−50 −25 0 25 50 75 100 125
TEMPERATURE (°C)

Figure 23. Latch Pin Open Voltage V

110
105
100

95

m

90

NTC

85
80
75
70

−50 −25 0 25 50 75 100 125
TEMPERATURE (°C)

Figure 25. Current I

Sourced from the

NTC

Latch Pin, Allowing Direct NTC Connection

clamp0

2.20

2.10

2.00

−50 −25 0 25 50 75 100 12

Figure 24. Latch Pin Voltage V

TEMPERATURE (°C)

clamp1

Pin is Sinking 1 mA)

220
210
200
190

(mA)

180
170

NTC(SSTART)

I

160
150
140

−50 −25 0 25 50 75 100 12
TEMPERATURE (°C)

Figure 26. Current I

NTC(SSTART)

Sourced from

the Latch Pin, During Soft−Start

(Latch−off

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11

NCP1234

APPLICATION INFORMATION

Introduction

The NCP1234 includes all necessary features to build a safe
and efficient power supply based on a fixed−frequency
flyback converter. It is particularly well suited for
applications where low part count is a key parameter,
without sacrificing safety.

• Current−Mode Operation with slope compensation:

The primary peak current is permanently controlled by
the FB voltage, ensuring maximum safety: the DRV
turn−off event is dictated by the peak current setpoint.
It also ensures that the frequency response of the
system stays a first order if in DCM, which eases the
design of the FB loop. The controller can be also used
in CCM applications with a wide input voltage range
thanks to its fixed ramp compensation that prevents the
appearance of sub−harmonic oscillations in most
applications.

• Fixed−Frequency Oscillator with Jittering: The

NCP1234 is available in different frequency options to
fit any application. The internal oscillator features a
low−frequency jittering that helps passing the EMI
limits by spreading out the energy content of frequency
peaks in quasi−peak and average mode of
measurement.

• Latched Timer−Based Overload Protection: The

overload protection depends only on the FB signal,
making it able to work with any transformer, even with
very poor coupling or high leakage inductance. The
protection is fully latched on the A version (the power
supply has to be stopped then restarted in order to
resume operation, even if the overload condition
disapears), and autorecovery on the B version. The
timer duration is fixed. The controller also enters the
same protection mode if the voltage on the CS pin
reaches 1.5 times the maximum internal setpoint
(allows to detect winding short-circuits).

• High Voltage Start−Up Current Source: Thanks to

ON Semiconductor’s Very High Voltage technology,
the NCP1234 can directly be connected to the high
input voltage. The start-up current source ensures a
clean start-up while ensuring low losses when it is off,
and the Dynamic Self-Supply (DSS) restarts the
start-up current source to supply the controller if the

supply transiently drops.

V

CC

• Adjustable Overpower Compensation: The high

input voltage sensed on the HV pin is converted into a
current to build on the current sense voltage an offset
proportional to the input voltage. By choosing the value
of the resistor in series with the CS pin, the amount of
compensation can be adjusted to the application.

• Frequency foldback then skip mode for light load

operation: In order to ensure a high efficiency under all
load conditions, the NCP1234 implements a frequency

foldback for light load condition and a skip mode for
extremely low load condition. The switching frequency
is decreased down to 27 kHz to reduce switching
losses.

• Extended VCC range: The NCP1234 accepts a supply

voltage as high as 28 V, with an overvoltage threshold
V
off.

(typically 26.5 V) that latches the controller

CC(ovp)

• Clamped Driver Stage: Despite the high maximum

supply voltage, the voltage on DRV pin is safely
clamped below 16 V, allowing the use of any standard
MOSFET, and reducing the current consumption of the
controller.

• Dual Latch−off Input: The NCP1234 can be latched

off by 2 ways: The voltage increase applied to its Latch
pin (typically an overvoltage) or by a decrease this
voltage. Thanks to the internal precise pull−up current
source a NTC can be directly connected to the latch pin.
This NTC will provide an overtemperature protection
by decreasing its resistance and consequently the
voltage at Latch pin,

• Soft−Start: At every start−up the peak current is

gradually increased during 4.0 ms to minimize the
stress on power components.

• Temperature Shutdown: The NCP1234 is internally

protected against self−overheating: if the die
temperature is too high, the controller shuts all
circuitries down (including the HV start−up current
source), allowing the silicon to cool down before
attempting to restart. This ensures a safe behavior in
case of failure.

Typical Operation

• Start−up: The HV start−up current source ensures the

charging of the V
threshold V
enough (above V
start. The controller then delivers pulses, starting with a
soft−start period t
linearly increases before the current−mode control takes
over. During the soft−start period, the low level latch is
ignored, and the latch current is double, to ensure a fast
pre−charge of the Latch pin decoupling capacitor.

CC(on)

capacitor up to the start−up

CC

, until the input voltage is high

HV(start)

) to allow the switching to

during which the peak current

SSTART

• Normal operation: As long as the feedback voltage is

within the regulation range and V
above V
(with jittering) in current−mode control. The peak
current (sensed on the CS pin) is set by the voltage on
the FB pin. Fixed ramp compensation is applied
internally to prevent sub−harmonic oscillations from
occurring.

, the NCP1234 runs at a fixed frequency

CC(min)

is maintained

CC

• Light load operation: When the FB voltage decreases

below V

FB(foldS)

, typically corresponding to a load of

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12

NCP1234

33% of the maximum load (for a DCM design), the
switching frequency starts to decrease down to
f

OSC(min)

. By lowering the switching losses, this feature
helps to improve the efficiency in light load conditions.
The frequency jittering is enabled in light load
operation as well.

• No load operation: When the FB voltage decreases

below V
of the maximum load, the controller enters skip mode.
By completely stopping the switching while the
feedback voltage is below V
further reduced. This allows minimizing the power
dissipation under extremely low load conditions. As the
skip mode is entered at very light loads, for which the
peak current is very small, there is no risk of audible
noise. V
V

CC(min)

, typically corresponding to a load of 2%

skip(in)

, the losses are

skip(out)

can be maintained between V

CC

CC(on)

and

by the DSS, if the auxiliary winding does not

provide sufficient level of V

voltage under this

CC

condition.

• Overload: The NCP1234 features timer−based

overload detection, solely dependent on the feedback
information: as soon as the internal peak current
setpoint hits the V

clamp, an internal timer starts to

ILIM

count. When the timer elapses, the controller stops and
enter the protection mode, autorecovery for the B
version (the controller initiates a new start−up after

elapses), or latched for the A version (the latch

t

autorec

is released only if V

is reset).

CC

• Latch−off: When the Latch input is pulled up (typically

by an over−voltage condition), or pulled down
(typically by an over−temperature condition, using the
provided current source with an NTC), the controller
latches off. The latch is released when the V

is reset.

CC

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13

NCP1234

DETAILED DESCRIPTION

High−Voltage Current Source

The NCP1234 HV pin can be connected either to the
rectified bulk voltage, or to the ac line through a rectifier.

Start−up

HV

However, the overpower compensation will work correctly
only if the HV pin is connected to the bulk voltage.

VCC

Istart

Control

+

VCC(on)

+

VCC(min)

+

VCC(off )

+

VCC(reset)

+

+

+

+

−

−

−

−

IC Start

blanking

tUVLO(blank)

TSD

R

Q

S

UVLO

Reset

Figure 27. HV Start−up Current Source Functional Schematic

At start−up, the current source turns on when the voltage
on the HV pin is higher than V
V

CC

V

CC(min)

reaches V

, until VCC is supplied by an internal source. The

, then turns on again when VCC reaches

CC(on)

controller actually starts the next time V

Even though the DSS is able to maintain the V
between V

CC(on)

and V

by turning the HV start−up

CC(min)

, and turns off when

HV(min)

CC

reaches V

CC

CC(on)

voltage

current source on and off, it can only be used in light load

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condition, otherwise the power dissipation on the die would
be too much. As a result, an auxiliary voltage source is
needed to supply V

during normal operation.

CC

The DSS is useful to keep the controller alive when no

.

switching pulses are delivered, e.g. in latch condition, or to
prevent the controller from stopping during load transients
when the V

14

might drop.

CC

V

HV(min)

V

NCP1234

HV

V

CC

V

CC(on)

V

CC(min)

HV

current

source =

I

start1

V

CC(inhibit)

DRV

Figure 28. Start−up Timing Diagram

For safety reasons, the start−up current is lowered when
V

is below V

CC

case the V

CC(inhibit)

pin is shorted to GND (in case of VCC capacitor

CC

failure, or external pull−down on V
controller).

There are only two conditions for which the current source
doesn’t turn on when V
HV pin is too low (below V
condition (TSD) has been detected. In all other conditions,
the HV current source will always turn on and off to maintain
V

between V

CC

CC(min)

When the application is turned off, the input capacitor
quickly discharges, and the output starts to fall out of

, to reduce the power dissipation in

to disable the

CC

reaches V

CC

HV(min)

and V

), or a thermal shutdown

.

CC(on)

CC(min)

: the voltage on

time

HV

current

source =

I

start2

time

time

regulation. At the same time, V
is no voltage anymore on the HV pin, the DSS isn’t able to
turn on. As a result, V
V

threshold, that turns the controller off, and resets the

CC(off)

drops even more and reach the

CC

internal fault timer, to prevent any unwanted latch−off and
allow a fast restart in case of a short OFF/ON sequence.

As soon as the application is turned back on, the HV
start−up current source starts to charge the V
Note that the threshold at which V
influence on the ability of the controller to restart. The
switching then turns on when V
additional delay or “hiccup”.The case of a fast OFF/ON
sequence is described at Figure 29.

drops, but because there

CC

capacitor.

CC

discharges has no

CC

reaches V

CC

CC(on)

, without

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15

V

HV(min)

V

CC(on)

V

CC(min)

V

CC(off)

NCP1234

The board is

V

HV

V

CC

unplugged

time

Output

DRV

Fault timer

(internal)

Controller

stops at

V

CC(off)

Loss of

regulation when

V

is too low

HV

Fault timer

reset by

V

CC(off)

VCC charges

up when V

high enough

Switching

restarts at

V

CC(on)

is

HV

time

time

time

Figure 29. Fast Application Off − On Sequence

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16

time

NCP1234

Oscillator with Maximum Duty Cycle and Frequency
Jittering

The NCP1234 includes an oscillator that sets the
switching frequency with an accuracy of ±7%. Two
frequency options can be ordered: 65 kHz and 100 kHz. The
maximum duty cycle of the DRV pin is 80%, with an
accuracy of ±7%.

In order to improve the EMI signature, the switching
frequency jitters ±6% around its nominal value, with a
triangle−wave shape and at a frequency of 125 Hz. This
frequency jittering is active even when the frequency is
decreased to improve the EMI in light load condition.

f

OSC

f

+ 6

OSC

Nominal f

OSC

f

− 6

OSC

Figure 30. Frequency Jittering

Time

8%

(125 Hz)

Clamped Driver

The supply voltage for the NCP1234 can be as high as
28 V , but most of the MOSFETs that will be connected to the
DRV pin cannot accept more than 20 V on their gate. The
driver pin is therefore clamped safely below 16 V. This
driver has a typical current capability of ±500 mA.

VCC

Clamp

DRV signal

Figure 31. Clamped Driver

DRV

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17

NCP1234

CURRENT−MODE CONTROL WITH OVERPOWER COMPENSATION AND SOFT−START

Current sensing

NCP1234 is a current−mode controller, which means that
the FB voltage sets the peak current flowing in the
inductance and the MOSFET. This is done through a PWM
comparator: the current is sensed across a resistor and the
resulting voltage is applied to the CS pin. It is applied to one

V

FB(ref)

PWM

+

−

Soft−start

+

−

Soft−start ramp
t

SSTART

Start

Reset

+

V

IC Start

IC Stop

+

−

ILIM

FB

CS

R

FB(up)

blanking

t

LEB

K

FB

input of the PWM comparator through a 250 ns LEB block.
On the other input the FB voltage divided by 5 sets the
threshold: when the voltage ramp reaches this threshold, the
output driver is turned off.

The maximum value for the current sense is 0.7 V, and it

is set by a dedicated comparator.

Jitter

Oscillator

S

Q

R

IC stop

DRV Stage

blanking

t

BCS

−

+

+

V

CS(stop)

Fault

Figure 32. Current Sense Block Schematic

Each time the controller is starting, i.e. the controller was
off and starts – or restarts – when V

reaches V

CC

CC(on)

, a
soft−start is applied: the current sense setpoint is linearly
increased from 0 (the minimum level can be higher than 0
because of the LEB and propagation delay) until it reaches
V

(after a duration of t

ILIM

), or until the FB loop

SSTART

Protection

Mode

UVLO

Latch
TSD

imposes a setpoint lower than the one imposed by the
soft−start (the 2 comparators outputs are OR’ed). The
soft−start ramp signal is generated by the D/A converter in
the NCP1234, that’s why there are observable 15 discrete
steps instead the truly linearly increasing current setpoint
ramp.

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18

V

FB

V

FB(fault)

Soft-start ramp

V

ILIM

NCP1234

Time

VFB takes

over soft-start

CS Setpoint

V

ILIMI

Figure 33. Soft−Start

Under some conditions, like a winding short−circuit for
instance, not all the energy stored during the on time is
transferred to the output during the off time, even if the on
time duration is at its minimum (imposed by the propagation
delay of the detector added to the LEB duration). As a result,
the current sense voltage keeps on increasing above V
because the controller is blind during the LEB blanking
time. Dangerously high current can grow in the system if
nothing is done to stop the controller. That’s what the
additional comparator, that senses when the current sense
voltage on CS pin reaches V

CS(stop)

(= 1.5 x V
as soon as this comparator toggles, the controller
immediately enters the protection mode (latched or
autorecovery according to the chosen option).

ILIM

ILIM

), does:

t

SSTART

Time

Time

Overpower compensation

The power delivered by a flyback power supply is
proportional to the square of the peak current in the
discontinuous conduction mode:

OUT

1

+

@ h @ Lp@ FSW@ I

2

p

,

P

Unfortunately, due to the inherent propagation delay of
the logic, the actual peak current is higher at high input
voltage than at low input voltage, leading to a significant
difference in the maximum output power delivered by the
power supply.

2

(eq. 1)

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19

NCP1234

I

P

I

LIMIT

High

Line

Low
Line

t

delay

Figure 34. Line Compensation for True Overpower Protection

t

delay

IP to be

compensated

time

To compensate this and have an accurate overpower
protection, an offset proportional to the input voltage is
added on the CS signal by turning on an internal current
source: by adding an external resistor in series between the
sense resistor and the CS pin, a voltage offset is created
across it by the current. The compensation can be adjusted
by changing the value of the resistor.

But this offset is unwanted to appear when the current
sense signal is small, i.e. in light load conditions, where it

HV

V

HVstop

A/D 3 bit

Converter

+

Peak Detector

FB

V

FB(OPC)

would be in the same order of magnitude. Therefore the
compensation current is only added when the FB voltage is
higher than V

FB(OPCE)

.

However, because the HV pin can be connected to an ac
voltage, there is needed an additional circuitry to read or at
least closely estimate the actual voltage on the bulk
capacitor.

(32 ms)

Watch

Dog

3 bit

Register

To C S
Block

T

blanking

LEB

I Generator

I ctrl

CS

Figure 35. Schematic Overpower Compensation Circuit

A 3 bit A/D converter with the peak detector senses the ac
input, and its output is periodically sampled and reset, in
order to follow closely the input voltage variations. The
sample and reset events are given by the V

HVsample

comparator used for sampling detection for the AC line

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input. If only the DC high voltage input is used, no reset
signal is generated by the V

HVsample

condition and the 32 ms
watch dog is used to generate the sampling events for
sampling the DC input high voltage line.

20

NCP1234

I

OPC

V

HV

V

V

FB(OPCE)

V

FB(OPCF)

Figure 36. Overpower Compensation Current Relation to Feedback Voltage and Input Voltage

VHV

V

HVsample

FB

Peak

detector

I

OPC

Sample

Reset

Sample

Reset

Sample

Reset

Reset

Sample

time

t

wd

Reset

time

Reset

time

Figure 37. Overpower Compensation Current if the HV Pin is Connected to AC Voltage

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21

V

V

HV(stop)

Peak

detector

I

OPC

HV

t

wd

Sample

NCP1234

t

wd

Sample

t

wd

Sample

time

Reset

time

Reset

Figure 38. Overpower Compensation if the HV Pin is Connected to DC Voltage

Feedback with Slope Compensation

The ratio from the FB voltage to the current sense setpoint

is 5, meaning that the FB voltage corresponding to V

FB

ILIM

20 kW

is

V

FB(ref)

t

HV

3.5 V. There is a pull−up resistor of 20 kW from FB pin to an
internal reference.

K

FB

+

−

PWM

time

CS

blanking

t

LEB

Figure 39. FB Circuitry

In order to allow the NCP1234 to operate in CCM with a
duty cycle above 50%, a fixed slope compensation is
internally applied to the current−mode control. The slope

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appearing on the internal voltage setpoint for the PWM
comparator is −32.5 mV/ms typical for the 65 kHz version,
and −50 mV/ms for the 100 kHz version.

22

NCP1234

Overcurrent protection with Fault timer

When an overcurrent occurs on the output of the power
supply, the FB loop asks for more power than the controller
can deliver, and the CS setpoint reaches V
event occurs, an internal t

timer is started: once the timer

fault

ILIMIT

. When this

times out, DRV pulses are stopped and the controller is either

PWM

+

−
R

Q

S

+

−

+

FB

CS

/ 5

blanking

tLEB

VILIM

Figure 40. Timer−Based Overcurrent Protection

latched off (latched protection, version A), or it enters an
autorecovery mode (version B). The timer is reset when the
CS setpoint goes back below V

before the timer elapses.

ILIM

To provide maximum output power at the low input line
voltages the fault timer is not started if the driver signal is
reset by the max duty cycle.

timer

tfault

Protection

Mode

release

timer

Autorecovery

t autorec

protection
mode only

Reset DRV

Reset

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23

NCP1234

In autorecovery mode, the controller tries to restart after t

the system starts a new burst cycle.

Output Load

Overcurrent

applied

Max Load

Fault Flag

Fault
timer
starts

V

CC

. If the fault has gone, the supply resumes operation; if not,

autorec

Fault

disappears

time

time

V

CC(on)

V

CC(min)

DRV

Fault timer

t

fault

Controller

stops

Restart

At

V

CC(on)

(new burst
cycle if Fault
still present)

time

time

t

fault

Figure 41. Autorecovery Timer−Based Protection Mode

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24

t

autorec

time

NCP1234

In the latched version, the controller can restart only if a

V

reset occurs, which in a real application can only

CC

Output Load

Overcurrent

applied

Max Load

Fault Flag

Fault
timer

starts

V

CC

happen if the power supply is unplugged from the mains
line.

No restart

when fault

disappears

time

time

V

CC(on)

V

CC(min)

DRV

Fault timer

t

fault

time

Controller

latches off

time

t

fault

Figure 42. Latched Timer−Based Overcurrent Protection

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25

time

NCP1234

LOW LOAD OPERATION

Frequency Foldback

In order to improve the efficiency in light load conditions,
the frequency of the internal oscillator is linearly reduced
from its nominal value down to f

OSC(min)

. This frequency

foldback starts when the voltage on FB pin goes below

f

OSC

Nominal f

OSC

Skip

f

OSC(min)

V

Skip Cycle Mode

skip(in)

V

FB(foldE)

Figure 43. Frequency Foldback when the FB Voltage Decreases

V

V

FB(foldS)

, and is complete before VFB reaches V
whatever the nominal switching frequency option is. The
current−mode control is still active while the oscillator
frequency decreases. Note that the frequency foldback is
disabled if the controller runs at its maximum duty cycle.

FB

FB(foldS)

skip(in)

,

−

+

+

V

skip

FB

CS

K

FB

blanking

t

LEB

+

−

Figure 44. Skip Cycle Schematic

When the FB voltage reaches V

while decreasing,

skip(in)

skip mode is activated: the driver stops, and the internal
consumption of the controller is decreased. While V

FB

is

below V
soon as V

, the controller remains in this state; but as

skip(out)

crosses the skip out threshold, the DRV pin

FB

starts to pulse again.

S

R

DRV stage

Q

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26

V

FB(fold)

V

skip(out)

V

skip(in)

NCP1234

V

FB

DRV

Latch−off Input

Latch

Enters

skip

INTC

1 kW

VDD

Exits

skip

Enters

skip

Figure 45. Skip Cycle Timing Diagram

+

−

I

NTC

+

+

VOVP

−

+

VOTP

blanking

tLatch(OVP)

blanking

tLatch(OTP)

Exits

skip

S

Q

R

Time

Time

Latch

Vclamp

Soft−start

end

Figure 46. Latch Detection Schematic

The Latch pin is dedicated to the latch−off function: it
includes two levels of detection that define a working
window, between a high latch and a low latch: within these
two thresholds, the controller is allowed to run; but as soon
as either the low or the high threshold is crossed, the
controller is latched off. The lower threshold is intended to
be used with an NTC thermistor, thanks to an internal current
source I

NTC

.

An active clamp prevents the voltage from reaching the
high threshold if it is only pulled up by the I

current. T o

NTC

reach the high threshold, the pull−up current has to be higher
than the pull−down capability of the clamp (typically

1.5 mA at V

OVP

).

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Reset

To avoid any false triggering, spikes shorter than 50 ms
(for the h i g h latch and 65 kHz version) or 350 ms (for the lo w
latch) are blanked and only longer signals can actually latch
the controller.

Reset occurs when V

is cycled down to a reset voltage,

CC

which in a real application can only happen if the power
supply is unplugged from the AC line.

Upon start−up, the internal references take some time
before being at their nominal values; so one of the
comparators could toggle even if it should not. Therefore the
internal logic does not take the latch signal into account
before the controller is ready to start: once V
V

27

, the latch pin High latch state is taken into account

CC(on)

CC

reaches

NCP1234

and the DRV switching starts only if it is allowed; whereas
the Low latch (typically sensing an overtemperature) is
taken into account only after the soft−start is finished. In
addition, the NTC current is doubled to I

NTC(SSTART)

during
the soft−start period, to speed up the charging of the Latch
pin capacitor. The maximum value of Latch pin capacitor is
given by the following formula (The standard start−up
condition is considered and the NTC current is neglected) :

V

CC

V

CC(on)

V

CC(min)

C

LATCHmax

Start-up

initiated by

V

CC(on)

t

SSTARTmin

+

2.8 @ 10

+

@ I

NTC(SSTART)min

V

clamp0min

−3

@ 130 @ 10

1.0

(eq. 2)

−6

F + 364 nF

Internal Latch Signal

DRV

Latch signal

high during

pre-start phase

Switching
allowed (no
latch event)

Figure 47. Latch−off Function Timing Diagram

Noise spike

ignored

(t

blanking)

Latch

time

time

Latch-off

time

Temperature Shutdown

The die includes a temperature shutdown protection with
a trip point guaranteed above 135°C and below 165°C, and
a typical hysteresis of 30°C. When the temperature rises
above the high threshold, the controller stops switching

www.onsemi.com

instantaneously, and the HV current source is turned off.
Internal logic state is reset. When the temperature falls
below the low threshold, the HV start−up current source is
enabled, and a regular start−up sequence takes place.

28

HV Start−up Current Source

TSD

Stop

No TSD

NCP1234

STATE DIAGRAMS

I

start1

TSD

TSD

TSD

VCC < V

CC(inhibit)

VCC < V

V

CC

CC(min)

> V

CC(inhibit)

I

start2

VCC > V

CC(on)

Off

Figure 48. HV Start−up Current Source State Diagram

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29

Controller Operation (Latched Version: A Option)

• TSD

Stopped

NCP1234

V

CC>VCC(on)

• High Latch

• VCC>V

CC(ovp)

Soft−start

• V

CC<VCC(off )

• TSD

Soft−start ends

Latch

• VCC reset

• High Latch

• Low Latch

• VCC>V

CC(ovp)

With Fault=

• VCC<V

• TSD

CC(off )

•

t

fault

•

V

CS>VCS(stop)

Skip

Skip out

• VCC>V

• High Latch

• Low Latch

expires

Skip in

Running

CC(ovp)

• Fault

• VCC<V

• TSD

CC(off )

Figure 49. Controller Operation State Diagram (Latched Protection)

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30

NCP1234

s

Controller Operation (Autorecovery Version: B Option)

V

CC>VCC(on)

• High Latch

• V

CC>VCC(ovp)

Soft−start

•

V

CC<VCC(off)

• TSD

Soft−start end

Latch

• t

autorec

• TSD

• VCC reset

counting

Stopped

• High Latch

• Low Latch

• V

CC>VCC(ovp)

•

V

CC<VCC(off)

• TSD
Skip

Skip out

• V

• High Latch

• Low Latch

Skip in

Running

CC>VCC(ovp)

• Fault

•

V

CC<VCC(off)

• TSD

•

t

expires

With Fault=

Figure 50. Controller Operation State Diagram (Autorecovery Protection)

www.onsemi.com

fault

•

V

CS>VCS(stop)

31

NCP1234

Table 1. ORDERING INFORMATION

Part No. Overload Protection Switching Frequency Package Shipping

NCP1234AD65R2G Latched 65 kHz SOIC−7

(Pb−Free)

†

2500 / Tape & Reel

NCP1234BD65R2G Autorecovery 65 kHz SOIC−7

(Pb−Free)

NCP1234AD100R2G Latched 100 kHz SOIC−7

(Pb−Free)

NCP1234BD100R2G Autorecovery 100 kHz SOIC−7

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

2500 / Tape & Reel

2500 / Tape & Reel

2500 / Tape & Reel

www.onsemi.com

32

NCP1234

P

al

PACKAGE DIMENSIONS

SOIC−7

CASE 751U

ISSUE E

−T−

−A−

58

S

1

4

−B−

0.25 (0.010)

M

M

B

G

C

SEATING
PLANE

H

D

7 PL

0.25 (0.010) T

M

B

SAS

R

X 45

_

M

K

SOLDERING FOOTPRINT*

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B ARE DATUMS AND T
IS A DATUM SURFACE.

4. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.

5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

MILLIMETERS

DIMAMIN MAX MIN MAX

4.80 5.00 0.189 0.197

B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020

J

G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010

J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0 8 0 8

____

N 0.25 0.50 0.010 0.020

S 5.80 6.20 0.228 0.244

INCHES

1.52

0.060

7.0

0.275

4.0

0.155

0.6

0.024

1.270

0.050

SCALE 6:1

ǒ

inches

mm

Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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