Page 1
NCP1216, NCP1216A
PWM Current-Mode
Controller for High-Power
Universal Off-Line Supplies
Housed in a SOIC−8 or PDIP−7 package, the NCP1216 represents
an enhanced version of NCP1200 based controllers. Due to its high
drive capability, NCP1216 drives large gate−charge MOSFETs, which
together with internal ramp compensation and built−in frequency
jittering, ease the design of modern AC−DC adapters.
With an internal structure operating at different fixed frequencies,
the controller supplies itself from the high−voltage rail, avoiding the
need of an auxiliary winding. This feature naturally eases the designer
task in some particular applications, e.g. battery chargers or TV sets.
Current−mode control also provides an excellent input audio
susceptibility and inherent pulse−by−pulse control. Internal ramp
compensation easily prevents sub−harmonic oscillations from taking
place in continuous conduction mode designs.
When the current setpoint falls below a given value, e.g. the output
power demand diminishes, the IC automatically enters the so−called
skip cycle mode and provides excellent efficiency at light loads.
Because this occurs at a user adjustable low peak current, no acoustic
noise takes place.
The NCP1216 features an efficient protective circuitry, which in
presence of an over current condition disables the output pulses while
the device enters a safe burst mode, trying to restart. Once the default
has gone, the device auto−recovers.
Features
• No Auxiliary Winding Operation
• Current−Mode Control with Adjustable Skip−Cycle Capability
• Internal Ramp Compensation
• Limited Duty Cycle to 50% (NCP1216A Only)
• Internal 1.0 ms Soft−Start (NCP1216A Only)
• Built−In Frequency Jittering for Better EMI Signature
• Auto−Recovery Internal Output Short−Circuit Protection
• Extremely Low No−Load Standby Power
• 500 mA Peak Current Capability
• Fixed Frequency Versions at 65 kHz, 100 kHz, 133 kHz
• Internal Temperature Shutdown
• Direct Optocoupler Connection
• SPICE Models Available for TRANsient and AC Analysis
• Pin−to−Pin Compatible with NCP1200 Series
• These are Pb−Free and Halide−Free Devices
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MARKING
DIAGRAMS
8
8
1
XXXXXX = Specific Device Code
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the ordering
information section on page 16 of this data sheet.
SOIC−8
D SUFFIX
CASE 751
PDIP−7
P SUFFIX
CASE 626B
PIN CONNECTIONS
Adj
1
FB
2
CS
3
Gnd
4
DEVICE MARKING AND
1
XXXXXXXXX
1
HV
8
NC
7
V
6
CC
Drv
5
XXXXX
ALYW
G
YYWWG
AWL
Typical Applications
• High Power AC−DC Converters for TVs, Set−Top Boxes, etc.
• Offline Adapters for Notebooks
• Telecom DC−DC Converters
• All Power Supplies
© Semiconductor Components Industries, LLC, 2016
May, 2016 − Rev. 16
1 Publication Order Number:
NCP1216/D
Page 2
Universal Input
EMI
Filter
NCP1216, NCP1216A
*See Application Section
NCP1216
Fosc = 35kHz
1
+
Adj
2
FB
CS
3
45
GND
Figure 1. Typical Application Example
HV
Vcc
Drv
R
8
7
6
comp
+
+
R
sense
PIN FUNCTION DESCRIPTION
Pin No. Pin Name Function Pin Description
1 Adj Adjust the Skipping Peak Current This pin lets you adjust the level at which the cycle skipping process
2 FB Sets the Peak Current Setpoint By connecting an Optocoupler to this pin, the peak current setpoint is
3 CS Current Sense Input This pin senses the primary current and routes it to the internal com-
4 GND IC Ground −
5 Drv Driving Pulses The driver’s output to an external MOSFET.
6 V
CC
Supplies the IC
7 NC − This un−connected pin ensures adequate creepage distance.
8 HV Generates the VCC from the Line Connected to the high−voltage rail, this pin injects a constant current
takes place. Shorting this pin to ground, permanently disables the skip
cycle feature.
adjusted accordingly to the output power demand.
parator via an L.E.B. By inserting a resistor in series with the pin, you
control the amount of ramp compensation you need.
This pin is connected to an external bulk capacitor of typically 22 mF.
into the V
bulk capacitor.
CC
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2
Page 3
Adj
NCP1216, NCP1216A
HV Current Source
HV1
8
Skip Cycle Comparator
+
−
Clock Jittering
Internal V
CC
UVLO High and Low
Internal Regulator
7
NC
FB
96 k
2
1.1 V
25 k
Current
Sense
GND
3
220 ns
L.E.B
19 k
Ramp
4
20 k
Pull−up Resistor
+
V
−
5 V
ref
Compensation
57 k
25 k
65 kHz
100 kHz
133kHz
+
−
1 V
Set
1 ms SS*
Overload?
Q Flip−Flop
= 75%
D
Cmax
Reset
Reset
Q
$500 mA
6
V
CC
5
Drv
Fault Duration
* Available for ”A” version only.
Figure 2. Internal Circuit Architecture
MAXIMUM RATINGS
Rating Symbol Value Unit
Power Supply Voltage, VCC Pin V
CC
Maximum Voltage on Low Power Pins (except Pin 8 and Pin 6) −0.3 to 10 V
Maximum Voltage on Pin 8 (HV), Pin 6 (VCC) Decoupled to Ground with 10 mF
Maximum Voltage on Pin 8 (HV), Pin 6 (VCC) Grounded 450 V
Minimum Operating Voltage on Pin 8 (HV) 28 V
Maximum Current into all Pins except VCC (Pin 6) and HV (Pin 8) when 10 V ESD Diodes are Activated
Thermal Resistance Junction−to−Air, PDIP−7 Version
Thermal Resistance Junction−to−Air, SOIC−8 Version
Maximum Junction Temperature T
R
q
R
q
JMAX
J−A
J−A
Temperature Shutdown TSD 155 °C
Hysteresis in Shutdown 30 °C
Storage Temperature Range −60 to +150 °C
ESD Capability, HBM Model (All Pins except VCC and HV) 2.0 kV
ESD Capability, Machine Model 200 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series contains ESD protection rated using the following tests:
Human Body Model (HBM) 2000 V per JEDEC Standard JESD22, Method A114E.
Machine Model (MM) 200 V per JEDEC Standard JESD22, Method A115A.
16 V
500 V
5.0 mA
100
°C/W
178
150 °C
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Page 4
NCP1216, NCP1216A
ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Maximum TJ = 150°C, VCC = 11 V unless otherwise noted.)
Characteristic Pin Symbol Min Typ Max Unit
DYNAMIC SELF−SUPPLY
Increasing Level at which the Current Source Turns Off 6 VCC
V
CC
OFF
VCC Decreasing Level at which the Current Source Turns On 6 VCC
VCC Decreasing Level at which the Latchoff Phase Ends 6 VCC
Internal IC Consumption, Latchoff Phase, VCC = 6.0 V NCP1216
6 I
NCP1216A
Internal IC Consumption, No Output Load on Pin 5, F
Internal IC Consumption, No Output Load on Pin 5, F
Internal IC Consumption, No Output Load on Pin 5, F
Internal IC Consumption, 1.0 nF Output Load on Pin 5, F
Internal IC Consumption, 1.0 nF Output Load on Pin 5, F
= 65 kHz
SW
0°C ≤ T
−40°C ≤ T
= 100 kHz
SW
0°C ≤ T
−40°C ≤ T
= 133 kHz
SW
0°C ≤ T
−40°C ≤ TJ ≤ +125°C
= 65 kHz
SW
0°C ≤ T
−40°C ≤ TJ ≤ +125°C
= 100 kHz
SW
0°C ≤ TJ ≤ +125°C
≤ +125°C
J
≤ +125°C
J
≤ +125°C
J
≤ +125°C
J
≤ +125°C
J
≤ +125°C
J
6 I
6 I
6 I
6 I
6 I
latch
CC3
CC1
CC1
CC1
CC2
CC2
−40°C ≤ TJ ≤ +125°C
Internal IC Consumption, 1.0 nF Output Load on Pin 5, F
= 133 kHz
SW
0°C ≤ T
−40°C ≤ TJ ≤ +125°C
≤ +125°C
J
6 I
CC2
INTERNAL STARTUP CURRENT SOURCE (TJ > 0°C)
High−voltage Current Source, V
= 10 V 8 IC1 4.9
CC
High−voltage Current Source, VCC = 0 V 8 IC2 9.0 mA
DRIVE OUTPUT
Output Voltage Rise−time @ C
Output Voltage Fall−time @ CL = 1.0 nF, 10−90% of a 12 V Output Signal 5 T
Source Resistance 5 R
Sink Resistance 5 R
= 1.0 nF, 10−90% of a 12 V Output Signal 5 T
L
r
f
OH
OL
CURRENT COMPARATOR (Pin 5 Unloaded)
Input Bias Current @ 1.0 V Input Level on Pin 3
Maximum Internal Current Setpoint 3 I
Default Internal Current Setpoint for Skip Cycle Operation 3 I
Propagation Delay from Current Detection to Gate OFF State 3 T
Leading Edge Blanking Duration 3 T
3 I
IB
Limit
Lskip
DEL
LEB
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
VCC
1.
2. Minimum value for T
and VCCON min−max always ensure an hysteresis of 2.0 V.
OFF
= 125°C.
J
11.2 12.2 13.4
ON
9.2 10.0 11.0
5.6 V
250
320
990 1110
1025 1180
1060 1200
1.7 2.0
2.1 2.4
2.4 2.9
8.0 11 mA
(Note 2)
60 ns
20 ns
15 20 35
5.0 10 18
0.02
0.93 1.08 1.14 V
330 mV
80 130 ns
220 ns
(Note 1)
V
V
(Note 1)
mA
mA
1245
mA
1285
mA
1290
mA
2.0
mA
2.55
mA
3.0
W
W
mA
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NCP1216, NCP1216A
ELECTRICAL CHARACTERISTICS (continued)
(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Maximum TJ = 150°C, VCC = 11 V unless otherwise noted.)
Characteristic
INTERNAL OSCILLATOR (VCC = 11 V, Pin 5 Loaded by 1.0 kW)
Oscillation Frequency, 65 kHz Version
0°C ≤ T
−40°C ≤ TJ ≤ +125°C
≤ +125°C
J
Oscillation Frequency, 100 kHz Version
0°C ≤ T
−40°C ≤ T
≤ +125°C
J
≤ +125°C
J
Oscillation Frequency, 133 kHz Version
Built−in Frequency Jittering in Percentage of f
0°C ≤ T
−40°C ≤ T
OSC
≤ +125°C
J
≤ +125°C
J
Maximum Duty−Cycle NCP1216
NCP1216A
FEEDBACK SECTION (VCC = 11 V, Pin 5 Loaded by 1.0 kW)
Internal Pullup Resistor
Pin 2 (FB) to Internal Current Setpoint Division Ratio − I
SKIP CYCLE GENERATION
Default Skip Mode Level
Pin 1 Internal Output Impedance 1 Z
INTERNAL RAMP COMPENSATION
Internal Ramp Level @ 25°C (Note 3)
Internal Ramp Resistance to CS Pin 3 R
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. A 1.0 MW resistor is connected to the ground for the measurement.
Pin Symbol Min Typ Max Unit
D
2 R
1 V
3 V
f
OSC
f
OSC
f
OSC
f
jitter
max
ratio
ramp
ramp
up
skip
out
58.5
57
90
86
120
110
65
65
100
100
133
133
71.5
110
120
146
160
±4.0 %
69
42
75
46.5
20
3.3
0.9 1.1 1.26 V
25
2.6 2.9 3.2 V
19
75
81
50
kHz
kHz
kHz
%
kW
kW
kW
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Page 6
5
5
60
NCP1216, NCP1216A
TYPICAL CHARACTERISTICS
14.0
50
40
30
(mA)
20
10
HV PIN LEAKAGE CURRENT @ 500 V
0
−50
−25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 3. High Voltage Pin Leakage Current vs.
Temperature
12.0
11.5
11.0
(V)
10.5
ON
VCC
10.0
9.5
13.5
13.0
(V)
12.5
OFF
VCC
12.0
11.5
(mA)
CC1
I
11.0
1400
1200
1000
800
600
400
200
−25
−50 0 25 50 75 100 12
TEMPERATURE (°C)
Figure 4. VCC
65 kHz
vs. Temperature
OFF
133 kHz
100 kHz
9.0
−50 0 25 50 75 100 125
−25 −25
TEMPERATURE (°C)
Figure 5. VCCON vs. Temperature
2.80
2.60
2.40
2.20
2.00
(mA)
1.80
CC2
I
1.60
1.40
1.20
1.00
−50 0 25 50 75 100 125
−25 −50
Figure 7. I
133 kHz
100 kHz
65 kHz
TEMPERATURE (°C)
vs. Temperature
CC2
0
−50 0 25 50 75 100 12
TEMPERATURE (°C)
150
130
110
(kHz)
90
OSC
F
70
50
Figure 6. I
−25 0 25 50 75 100 125
(@ V
CC1
TEMPERATURE (°C)
= 11 V) vs. Temperature
CC
133 kHz
100 kHz
65 kHz
Figure 8. Switching Frequency vs.
Temperature
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Page 7
NCP1216, NCP1216A
5
5.90
5.80
5.70
(V)
5.60
latch
VCC
5.50
5.40
5.30
30
25
20
−25 0 25 50 75 100 125
−50 −50
TEMPERATURE (°C)
Figure 9. VCC
Source
vs. Temperature Figure 10. I
latch
(mA)
CC3
I
400
350
300
250
200
150
100
50
1.13
1.08
NCP1216A
NCP1216
0
−25 0 25 50 75 100 125
TEMPERATURE (°C)
vs. Temperature
CC3
15
10
DRIVER RESISTANCE (W)
5
0
−25 0 25 50 75 100 125
−50 −50
Sink
TEMPERATURE (°C)
Figure 11. Drive Sink and Source Resistance
vs. Temperature
1.20
1.15
(V)
1.10
skip
V
1.05
1.03
0.98
CURRENT SENSE LIMIT (V)
0.93
−25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 12. Current Sense Limit vs. Temperature
75.0
74.5
74.0
73.5
73.0
DUTY CYCLE (%)
72.5
1.00
−25 0 25 50 75 100 125
−50 −50
TEMPERATURE (°C)
Figure 13. V
vs. Temperature
skip
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7
72.0
−25 0 25 50 75 100 12
TEMPERATURE (°C)
Figure 14. NCP1216 Max Duty−Cycle vs.
Temperature
Page 8
NCP1216, NCP1216A
5
49.0
48.5
48.0
47.5
47.0
46.5
DUTY CYCLE (%)
46.0
45.5
45.0
−50
−25 0 25 50 75 100 125
Figure 15. NCP1216A Max Duty−Cycle vs.
TEMPERATURE (°C)
Temperature
14
12
(V)
ramp
V
3.10
3.05
3.00
2.95
2.90
2.85
2.80
2.75
2.70
−50
−25 0 25 50 75 100 12
TEMPERATURE (°C)
Figure 16. V
vs. Temperature
ramp
10
8
IC1 (mA)
6
4
2
−50
−25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 17. High Voltage Current Source
(@ V
= 10 V) vs. Temperature
CC
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NCP1216, NCP1216A
APPLICATION INFORMATION
Introduction
The NCP1216 implements a standard current mode
architecture where the switch−off event is dictated by the
peak current setpoint. This component represents the ideal
candidate where low part count is the key parameter,
particularly in low−cost AC−DC adapters, TV power
supplies etc. Due to its high−performance High−Voltage
technology, the NCP1216 incorporates all the necessary
components normally needed in UC384X based supplies:
timing components, feedback devices, low−pass filter and
self−supply. This later point emphasizes the fact that ON
Semiconductor’s NCP1216 does NOT need an auxiliary
winding to operate: the product is naturally supplied from
the high−voltage rail and delivers a V
to the IC. This
CC
system is called the Dynamic Self−Supply (DSS):
Dynamic Self−Supply (DSS): Due to its Very High
Voltage Integrated Circuit (VHVIC) technology,
ON Semiconductor’s NCP1216 allows for a direct pin
connection to the high−voltage DC rail. A dynamic current
source charges up a capacitor and thus provides a fully
independent V
level to the NCP1216. As a result, there is
CC
no need for an auxiliary winding whose management is
always a problem in variable output voltage designs (e.g.
battery chargers).
Adjustable Skip Cycle Level: By offering the ability to tailor
the level at which the skip cycle takes place, the designer can
make sure that the skip operation only occurs at low peak
current. This point guarantees a noise−free operation with
cheap transformers. Skip cycle offers a proven mean to
reduce the standby power in no or light loads situations.
Internal Frequency Dithering for Improved EMI
Signature: By modulating the internal switching frequency
with the DSS V
ripple, natural energy spread appears and
CC
softens the controller’s EMI signature.
Wide Switching − Frequency Offered with Different
Options (65 kHz − 100 kHz − 133 kHz): Depending on the
application, the designer can pick up the right device to help
reducing magnetics or improve the EMI signature before
reaching the 150 kHz starting point.
Ramp Compensation: By inserting a resistor between the
Current Sense (CS) pin and the actual sense resistor, it
becomes possible to inject a given amount of ramp
compensation since the internal sawtooth clock is routed to
the CS pin. Sub−harmonic oscillations in Continuous
Conduction Mode (CCM) can thus be compensated via a
single resistor.
Over Current Protection (OCP): By continuously
monitoring the FB line activity, NCP1216 enters burst mode
as soon as the power supply undergoes an overload. The
device enters a safe low power operation, which prevents
from any lethal thermal runaway. As soon as the default
disappears, the power supply resumes operation. Unlike
other controllers, overload detection is performed
independently of any auxiliary winding level. In presence of
a bad coupling between both power and auxiliary windings,
the short circuit detection can be severely affected. The DSS
naturally shields you against these troubles.
Wide Duty−
a large duty−cycle excursion. The NCP1216 can go up to 75%
typically. For Continuous Conduction Mode (CCM)
applications, the internal ramp compensation lets you fight
against sub−harmonic oscillations.
Cycle Operation: Wide mains operation requires
Low Standby Power: If SMPS naturally exhibit a good
efficiency at nominal load, they begin to be less efficient
when the output power demand diminishes. By skipping
unnecessary switching cycles, the NCP1216 drastically
reduces the power wasted during light load conditions. In
no−load conditions, the NPC1216 allows the total standby
power to easily reach next International Energy Agency
(IEA) recommendations.
No Acoustic Noise While Operating: Instead of skipping
cycles at high peak currents, the NCP1216 waits until the
peak current demand falls below a user−adjustable 1/3 of the
maximum limit. As a result, cycle skipping can take place
without having a singing transformer, one can thus select
cheap magnetic components free of noise problems.
External MOSFET Connection: By leaving the external
MOSFET external to the IC, you can select avalanche proof
devices, which in certain cases (e.g. low output powers), let
you work without an active clamping network. Also, by
controlling the MOSFET gate signal flow; you have an
option to slow down the device commutation, therefore
reducing the amount of ElectroMagnetic Interference
(EMI).
SPICE Model: A dedicated model to run transient
cycle−by−cycle simulations is available but also an
averaged version to help you closing the loop. Ready−to−use
templates can be downloaded in OrCAD’s PSpice and
INTUSOFT’s IsSpice from ON Semiconductor web site, in
the NCP1216 related section.
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NCP1216, NCP1216A
Dynamic Self−Supply
The DSS principle is based on the charge/discharge of the
V
bulk capacitor from a low level up to a higher level. We
CC
can easily describe the current source operation with a bunch
of simple logical equations:
POWER−ON: If V
< VCC
CC
then the Current Source
OFF
is ON, no output pulses
decreasing > VCCON then the Current Source is
If V
CC
OFF, output is pulsing
If V
increasing < VCC
CC
then the Current Source is
OFF
ON, output is pulsing
Typical values are: VCC
= 12.2 V, VCCON = 10 V
OFF
To better understand the operational principle, Figure 18
offers the necessary light:
V
= 2.2 V
ripple
ON, I = 8 mA
VCC
= 12.2 V
OFF
VCCON = 10 V
OFF, I = 0 mA
Application note AND8069/D details tricks to widen the
NCP1216 driving implementation, in particular for large Q
MOSFETs. This document can be downloaded at
www.onsemi.com/pub/Collateral/AND8069−D.PDF.
Ramp Compensation
Ramp compensation is a known mean to cure
sub−harmonic oscillations. These oscillations take place at
half the switching frequency and occur only during
Continuous Conduction Mode (CCM) with a duty−cycle
greater than 50%. To lower the current loop gain, one usually
injects between 50% and 100% of the inductor down−slope.
Figure 19 depicts how internally the ramp is generated:
DC
= 75°C
max
+
L.E.B
−
19 k
CS
R
2.9V
comp
0V
R
sense
g
Output Pulse
10
Figure 18. The Charge/Discharge Cycle Over a
30 50 70 90
10 mF V
Capacitor
CC
The DSS behavior actually depends on the internal IC
consumption and the MOSFET’s gate charge Q
select a 600 V 10 A MOSFET featuring a 30 nC Q
. If we
g
, then we
g
can compute the resulting average consumption supported
by the DSS which is:
I
[ Fsw Qg) I
total
CC1
.
(eq. 1)
The total IC heat dissipation incurred by the DSS only is
given by:
I
total
V
pin8
.
(eq. 2)
Suppose that we select the NCP1216P065 with the above
MOSFET, the total current is
(30 n 65 k) ) 900 m + 2.9 mA.
(eq. 3)
Supplied from a 350 VDC rail (250 VAC), the heat
dissipated by the circuit would then be:
350 V 2.9 mA + 1W
(eq. 4)
As you can see, it exists a tradeoff where the dissipation
capability of the NCP1216 fixes the maximum Q
that the
g
circuit can drive, keeping its dissipation below a given
target. Please see the “Power Dissipation” section for a
complete design example and discover how a resistor can
help to heal the NCP1216 heat equation.
From Set−point
Figure 19. Inserting a Resistor in Series with the
Current Sense Information brings Ramp
Compensation
In the NCP1216, the ramp features a swing of 2.9 V with
a Duty cycle max at 75%. Over a 65 kHz frequency, it
corresponds to a
2.9
65 kHz + 251 mVńms ramp.
0.75
(eq. 5)
In our FLYBACK design, let’s suppose that our primary
inductance L
is 350 mH, delivering 12 V with a Np : Ns
p
ratio of 1:0.1. The OFF time primary current slope is thus
given by:
V
) V
out
L
p
when projected over an R
N
p
f
+ 371 mAńmsor37mVńms
N
s
of 0.1 W, for instance. If we
sense
(eq. 6)
select 75% of the down−slope as the required amount of
ramp compensation, then we shall inject 27 mV/ms. Our
internal compensation being of 251 mV/ms, the divider ratio
(divratio) between R
of algebra to determine R
19 k divratio
1 * divratio
Frequency Jittering
and the 19 kW is 0.107. A few lines
comp
:
comp
+ 2.37 kW
(eq. 7)
Frequency jittering is a method used to soften the EMI
signature by spreading the energy in the vicinity of the main
switching component. NCP1216 offers a $4% deviation of
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NCP1216, NCP1216A
the nominal switching frequency whose sweep is
synchronized with the V
ripple. For instance, with a 2.2 V
CC
peak−to−peak ripple, the NCP1216P065 frequency will
equal 65 kHz in the middle of the ripple and will increase as
rises or decrease as VCC ramps down. Figure 20
V
CC
portrays the behavior we have adopted:
VCC
VCC Ripple
62 kHz
VCC
ON
Figure 20. VCC Ripple is Used to Introduce a
Frequency Jittering on the Internal Oscillator
Skipping Cycle Mode
OFF
65 kHz
Sawtooth
68 kHz
The NCP1216 automatically skips switching cycles when
the output power demand drops below a given level. This is
accomplished by monitoring the FB pin. In normal
operation, pin 2 imposes a peak current accordingly to the
load value. If the load demand decreases, the internal loop
asks for less peak current. When this setpoint reaches a
determined level, the IC prevents the current from
decreasing further down and starts to blank the output
pulses: the IC enters the so−called skip cycle mode, also
named controlled burst operation. The power transfer now
depends upon the width of the pulse bunches (Figure 22).
Suppose we have the following component values:
L
, primary inductance = 350 mH
p
, switching frequency = 65 kHz
F
sw
I
skip = 600 mA (or 333 mV / R
p
sense
)
The theoretical power transfer is therefore:
1
Lp I
2
2
Fsw+ 4W.
p
(eq. 8)
If this IC enters skip cycle mode with a bunch length of
10 ms over a recurrent period of 100 ms, then the total power
transfer is:
4 0.1 + 400 mW.
(eq. 9)
To better understand how this skip cycle mode takes place,
a look at the operation mode versus the FB level
immediately gives the necessary insight:
FB
4.2 V, FB Pin Open
3.2 V, Upper
Normal Current Mode Operation
Skip Cycle Operation
= 333 mV / R
I
pMIN
sense
Figure 21.
Dynamic Range
1 V
When FB is above the skip cycle threshold (1.0 V by
default), the peak current cannot exceed 1.0 V/R
sense
. When
the IC enters the skip cycle mode, the peak current cannot go
below V
/ 3.3. The user still has the flexibility to alter this
pin1
1.0 V by either shunting pin 1 to ground through a resistor
or raising it through a resistor up to the desired level.
Grounding pin 1 permanently invalidates the skip cycle
operation.
Power P1
Power
P2
Power
P3
Figure 22. Output Pulses at Various Power Levels
(X = 5 ms/div) P1 < P2 < P3
www.onsemi.com
11
Page 12
NCP1216, NCP1216A
300
200
100
0
Figure 23. The Skip Cycle Takes Place at Low Peak
Currents which Guarantees Noise Free Operation
Non−Latching Shutdown
Max Peak
Current
Skip Cycle
Current Limit
315.4U 882.7U 1.450M 2.017M 2.585M
In some cases, it might be desirable to shut off the part
temporarily and authorize its restart once the default has
disappeared. This option can easily be accomplished
through a single NPN bipolar transistor wired between FB
and ground. By pulling FB below the Adj pin 1 level, the
output pulses are disabled as long as FB is pulled below
pin 1. As soon as FB is relaxed, the IC resumes its operation.
Figure 24 depicts the application example:
due to the DSS operation. In our example, at
T
ambient
= 50°C, I
is measured to be 2.9 mA with a
CC2
10 A / 600 V MOSFET. As a result, the NCP1216 will
dissipate from a 250 VAC network,
350 V 2.9 mA@TA+ 50 C + 1W
°
(eq. 11)
The PDIP−7 package offers a junction−to−ambient thermal
resistance R
of 100°C/W. Adding some copper area
J−A
q
around the PCB footprint will help decreasing this number:
12 mm x 12 mm to drop R
down to 75°C/W with 35 m
J−A
q
copper thickness (1 oz.) or 6.5 mm x 6.5 mm with 70 m
copper thickness (2 oz.). For a SOIC−8, the original
178°C/W will drop to 100°C/W with the same amount of
copper. With this later PDIP−7 number, we can compute the
maximum power dissipation that the package accepts at an
ambient of 50°C:
P
max
+
Jmax
R
qJ * A
Amax
+ 1W
(eq. 12)
T
* T
which barely matches our previous budget. Several
solutions exist to help improving the situation:
1. Insert a Resistor in Series with Pin 8: This resistor will
take a part of the heat normally dissipated by the NCP1216.
Calculations of this resistor imply that V
below 30 V in the lowest mains conditions. Therefore, R
does not drop
pin8
drop
can be selected with:
R
drop
v
V
bulkmin
* 50 V
8mA
(eq. 13)
1
2
3
ON/OFF
Figure 24. Another Way of Shutting Down the IC
without a Definitive Latchoff State
Q1
4
8
7
6
5
A full latching shutdown, including overtemperature
protection, is described in application note AND8069/D.
Power Dissipation
The NCP1216 is directly supplied from the DC rail
through the internal DSS circuitry. The current flowing
through the DSS is therefore the direct image of the
NCP1216 current consumption. The total power dissipation
can be evaluated using:
(V
HVDC
* 11 V) I
CC2
(eq. 10)
which is, as we saw, directly related to the MOSFET Qg. If
we operate the device on a 90−250 VAC rail, the maximum
rectified voltage can go up to 350 VDC. However, as the
characterization curves show, the current consumption
drops at a higher junction temperature, which quickly occurs
In our case, V
minimum is 120 VDC, which leads to a
bulk
dropping resistor of 8.7 kW. With the above example in
mind, the DSS will exhibit a duty−cycle of:
2.9 mAń8mA+ 36%
(eq. 14)
By inserting the 8.7 kW resistor, we drop
8.7 kW *8 mA+ 69.6 V
(eq. 15)
during the DSS activation. The power dissipated by the
NCP1216 is therefore:
P
instant
*DSS
duty * cycle
(350 * 69) * 8 m * 0.36 + 800 mW
+
(eq. 16)
We can pass the limit and the resistor will dissipate
1W* 800 mW + 200 mW
(eq. 17)
or
p
drop
+
69
8.7 k
*0.36
(eq. 18)
2
2. Select a MOSFET with a Lower Qg: Certain MOSFETs
exhibit different total gate charges depending on the
technology they use. Careful selection of this component
can help to significantly decrease the dissipated heat.
www.onsemi.com
12
Page 13
NCP1216, NCP1216A
3. Implement Figure 3, from AN8069/D, Solution: This is
another possible option to keep the DSS functionality (good
short−circuit protection and EMI jittering) while driving any
types of MOSFETs. This solution is recommended when the
designer plans to use SOIC−8 controllers.
4. Connect an Auxiliary Winding: If the mains conditions
are such that you simply can’t match the maximum power
dissipation, then you need to connect an auxiliary winding
to permanently disconnect the startup source.
Overload Operation
In applications where the output current is purposely not
controlled (e.g. wall adapters delivering raw DC level), it is
interesting to implement a true short−circuit protection. A
short−circuit actually forces the output voltage to be at a low
level, preventing a bias current to circulate in the
Optocoupler LED. As a result, the FB pin level is pulled up
to 4.2 V, as internally imposed by the IC. The peak current
setpoint goes to the maximum and the supply delivers a
rather high power with all the associated effects. Please note
that this can also happen in case of feedback loss, e.g. a
broken Optocoupler. To account for this situation, NCP1216
hosts a dedicated overload detection circuitry. Once
activated, this circuitry imposes to deliver pulses in a burst
manner with a low duty−cycle. The system auto−recovers
when the fault condition disappears.
During the startup phase, the peak current is pushed to the
maximum until the output voltage reaches its target and the
feedback loop takes over. This period of time depends on
normal output load conditions and the maximum peak
current allowed by the system. The time−out used by this IC
works with the V
V
decreases from the VCC
CC
decoupling capacitor: as soon as the
CC
level (typically 12.2 V) the
OFF
device internally watches for an overload current situation.
If this condition is still present when the VCC
level is
ON
reached, the controller stops the driving pulses, prevents the
self−supply current source to restart and puts all the circuitry
in standby, consuming as little as 350 mA typical (I
CC3
parameter). As a result, the VCC level slowly discharges
toward 0 V. When this level crosses 5.6 V typical, the
controller enters a new startup phase by turning the current
source on: V
output pulses at the VCC
condition has been removed before VCC
rises toward 12.2 V and again delivers
CC
crossing point. If the fault
OFF
approaches,
ON
then the IC continues its normal operation. Otherwise, a new
fault cycle takes place. Figure 25 shows the evolution of the
signals in presence of a fault.
VCC
VCC
VCC
OFF
ON
latch
= 10 V
= 12.2 V
= 5.6 V
12.2 V
10 V
5.6 V
Fault Flag
V
CC
Drv
Internal
Startup Phase
Regulation
Occurs Here
Driver
Pulses
Latchoff
Phase
Time
Driver
Pulses
Time
Fault is
Relaxed
Time
Fault Occurs Here
Figure 25.
If the fault is relaxed during the VCC natural fall down
sequence, the IC automatically resumes.
If the fault still persists when V
reached VCCON, then the
CC
controller cuts everything off until recovery.
www.onsemi.com
Calculating the VCC Capacitor
As the above section describes, the fall down sequence
depends upon the V
line to go from 12.2 V to 10 V. The required time
V
CC
13
level: how long does it take for the
CC
Page 14
NCP1216, NCP1216A
depends on the startup sequence of your system, i.e. when
you first apply the power to the IC. The corresponding
transient fault duration due to the output capacitor charging
must be less than the time needed to discharge from 12.2 V
to 10 V, otherwise the supply will not properly start. The test
consists in either simulating or measuring in the lab how
much time the system takes to reach the regulation at full
load. Let’s suppose that this time corresponds to 6ms.
Therefore a V
fall time of 10 ms could be well
CC
appropriated in order to not trigger the overload detection
circuitry. If the corresponding IC consumption, including
the MOSFET drive, establishes at 2.9 mA, we can calculate
the required capacitor using the following formula:
Dt +
DV·C
i
(eq. 19)
with DV = 2.2 V. Then for a wanted Dt of 30 ms, C equals
39.5 mF or a 68 mF for a standard value (including ±20%
dispersions). When an overload condition occurs, the IC
blocks its internal circuitry and its consumption drops to
350 mA typical. This happens at V
stuck until V
reaches 5.6 V: we are in latchoff phase.
CC
= 10 V and it remains
CC
Again, using the selected 68 mF and 350 mA current
consumption, this latchoff phase lasts: 780 ms.
Protecting the Controller Against Negative Spikes
As with any controller built upon a CMOS technology, it
is the designer’s duty to avoid the presence of negative
spikes on sensitive pins. Negative signals have the bad habit
to forward bias the controller substrate and induce erratic
behaviors. Sometimes, the injection can be so strong that
internal parasitic SCRs are triggered, engendering
irremediable damages to the IC if a low impedance path is
offered between V
and GND. If the current sense pin is
CC
often the seat of such spurious signals, the high−voltage pin
can also be the source of problems in certain circumstances.
During the turn−off sequence, e.g. when the user unplugs the
power supply, the controller is still fed by its V
capacitor
CC
and keeps activating the MOSFET ON and OFF with a peak
current limited by R
coefficient Q of the resonating network formed by L
C
is low (e.g. the MOSFET R
bulk
. Unfortunately, if the quality
sense
dson
+ R
are small),
sense
and
p
conditions are met to make the circuit resonate and thus
negatively bias the controller. Since we are talking about ms
pulses, the amount of injected charge, (Q = I * t),
immediately latches the controller that brutally discharges
its V
capacitor. If this VCC capacitor is of sufficient value,
CC
its stored energy damages the controller. Figure 26 depicts
a typical negative shot occurring on the HV pin where the
brutal V
discharge testifies for latchup.
CC
0
Figure 26. A Negative Spike Takes Place on the Bulk Capacitor at the Switch−off Sequence
V
CC
5 V/DIV
10 ms/DIV
Simple and inexpensive cures exist to prevent from
internal parasitic SCR activation. One of them consists in
inserting a resistor in series with the high−voltage pin to
keep the negative current to the lowest when the bulk
becomes negative (Figure 27). Please note that the negative
spike is clamped to (−2 * V
) due to the diode bridge. Also,
f
the power dissipation of this resistor is extremely small since
it only heats up during the startup sequence.
V
latch
1 V/DIV
Another option (Figure 28) consists in wiring a diode
from V
VCC
to the bulk capacitor to force VCC to reach
CC
sooner and thus stops the switching activity before
ON
the bulk capacitor gets deeply discharged. For security
reasons, two diodes can be connected in series.
www.onsemi.com
14
Page 15
NCP1216, NCP1216A
R
bulk
+
C
bulk
1
2
3
45
8
7
6
> 4.7 k
+
CV
CC
Figure 27. Figure 28.
A simple resistor in series avoids any latchup in the controller
or one diode forces V
to reach V
CC
CCON
+
C
bulk
sooner.
1
2
3
45
8
7
6
D3
1N4007
+
CV
CC
Soft−Start − NCP1216A only
The NCP1216A features an internal 1.0 ms soft−start
activated during the power on sequence (PON). As soon as
VCC reaches V
, the peak current is gradually
CCOFF
increased from nearly zero up to the maximum clamping
level (e.g. 1.0 V). This situation lasts during 1ms and further
to that time period, the peak current limit is blocked to
1.0 V until the supply enters regulation. The soft−start is also
activated during the over current burst (OCP) sequence.
Every restart attempt is followed by a soft−start activation.
Generally speaking, the soft−start will be activated when
V
ramps up either from zero (fresh power−on sequence)
CC
or 5.6 V, the latchoff voltage occurring during OCP.
Figure 29 portrays the soft−start behavior. The time scales
are purposely shifted to offer a better zoom portion.
Figure 29. Soft−start is activated during a startup sequence or an OCP condition
www.onsemi.com
15
Page 16
NCP1216, NCP1216A
ORDERING INFORMATION
Device Version Marking Package Shipping
NCP1216D65R2G 65 kHz 16D06 SOIC−8
(Pb−Free)
NCP1216D100R2G 100 kHz 16D10 SOIC−8
(Pb−Free)
NCP1216D133R2G 133 kHz 16D13 SOIC−8
(Pb−Free)
NCP1216P65G 65 kHz P1216P065 PDIP−7
(Pb−Free)
NCP1216P100G 100 kHz P1216P100 PDIP−7
(Pb−Free)
NCP1216P133G 133 kHz P1216P133 PDIP−7
(Pb−Free)
NCP1216AD65R2G 65 kHz 16A06 SOIC−8
(Pb−Free)
NCP1216AD100R2G 100 kHz 16A10 SOIC−8
(Pb−Free)
NCP1216AD133R2G 133 kHz 16A13 SOIC−8
(Pb−Free)
NCP1216AP65G 65 kHz 1216AP06 PDIP−7
(Pb−Free)
NCP1216AP100G 100 kHz P1216AP10 PDIP−7
(Pb−Free)
NCP1216AP133G 133 kHz P1216AP13 PDIP−7
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
50 Units / Rail
50 Units / Rail
50 Units/ Rail
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
50 Units / Rail
50 Units / Rail
50 Units / Rail
†
www.onsemi.com
16
Page 17
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−7 (PDIP−8 LESS PIN 7)
SCALE 1:1
NOTE 8
A1
D1
D
14
TOP VIEW
e/2
e
SIDE VIEW
STYLE 1:
PIN 1. AC IN
2. DC + IN
3. DC − IN
4. AC IN
5. GROUND
6. OUTPUT
7. NOT USED
8. V
CC
A
58
H
E1
b2
B
A2
A
NOTE 3
L
SEATING
PLANE
C
8X
b
M
0.010 CA
MBM
CASE 626B
ISSUE D
E
END VIEW
WITH LEADS CONSTRAINED
NOTE 5
M
eB
END VIEW
NOTE 6
DATE 22 APR 2015
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
c
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
INCHES
DIM MIN MAX
A −−−− 0.210
A1 0.015 −−−−
A2 0.115 0.195 2.92 4.95
b 0.014 0.022
b2
0.060 TYP 1.52 TYP
C 0.008 0.014
D 0.355 0.400
D1 0.005 −−−−
E 0.300 0.325
E1 0.240 0.280 6.10 7.11
e 0.100 BSC
eB −−−− 0.430 −−− 10.92
L 0.115 0.150 2.92 3.81
M −−−− 10
MILLIMETERS
MIN MAX
−−− 5.33
0.38 −−−
0.35 0.56
0.20 0.36
9.02 10.16
0.13 −−−
7.62 8.26
2.54 BSC
−−− 10
°°
GENERIC
MARKING DIAGRAM*
XXXXXXXXX
XXXX = Specific Device Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
AWL
YYWWG
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
98AON12198D
PDIP−7 (PDIP−8 LESS PIN 7)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
www.onsemi.com
Page 18
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
8
1
SCALE 1:1
B
−Y−
−Z−
−X−
A
58
1
4
G
H
D
0.25 (0.010) Z
M
SOLDERING FOOTPRINT*
7.0
0.275
S
Y
0.25 (0.010)
C
SXS
SEATING
PLANE
0.10 (0.004)
1.52
0.060
4.0
0.155
M
M
Y
N
SOIC−8 NB
CASE 751−07
ISSUE AK
K
X 45
_
M
8
XXXXX
ALYWX
1
IC
XXXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
8
XXXXX
ALYWX
1
(Pb−Free)
J
G
IC
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
MILLIMETERS
DIMAMIN MAX MIN MAX
4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0 8 0 8
____
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
GENERIC
MARKING DIAGRAM*
8
XXXXXX
AYWW
1
Discrete
XXXXXX = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
DATE 16 FEB 2011
INCHES
8
XXXXXX
AYWW
G
1
Discrete
(Pb−Free)
0.6
0.024
1.270
0.050
SCALE 6:1
ǒ
inches
mm
Ǔ
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
www.onsemi.com
Page 19
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
SOIC−8 NB
CASE 751−07
ISSUE AK
STYLE 3:
STYLE 7:
STYLE 11:
STYLE 15:
STYLE 19:
STYLE 23:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
DATE 16 FEB 2011
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
DOCUMENT NUMBER:
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