Datasheet NCP1015AP065G, NCP1015AP100G Specification

NCP1015

Self-Supplied Monolithic
Switcher for Low Standby­Power Offline SMPS

The NCP1015 integrates a fixed−frequency current−mode
controller and a 700 V voltage MOSFET. Housed in a PDIP−7 or
SOT−223 package, the NCP1015 offers everything needed to build a
rugged and low−cost power supply, including soft−start, frequency
jittering, short−circuit protection, skip−cycle, a maximum peak
current set−point and a Dynamic Self−Supply (no need for an auxiliary
winding).

Unlike other monolithic solutions, the NCP1015 is quiet by nature:
during nominal load operation, the part switches at one of the available
frequencies (65−100 kHz). When the current set−point falls below a
given value, e.g. the output power demand diminishes, the IC
automatically enters the so−called skip cycle mode and provides
excellent efficiency at light loads. Because this occurs at typically 0.25
of the maximum peak value, no acoustic noise takes place. As a result,
standby power is reduced to the minimum without acoustic noise
generation.

Short−circuit detection takes place when the feedback signal fades
away e.g. un−true short−circuit or is broken optocoupler cases. Finally
soft−start and frequency jittering further ease the designer task to
quickly develop low−cost and robust offline power supplies.

For improved standby performance, the connection of an auxiliary
winding stops the DSS operation and helps to consume less than
100 mW at high line.

Features

• Built−in 700 V MOSFET with typical R

• Large Creepage Distance between High−voltage Pins

• Current−mode Fixed Frequency Operation: 65 kHz − 100 kHz

• Skip−cycle Operation at Low Peak Currents Only: No Acoustic Noise!

• Dynamic Self−Supply, No Need for an Auxiliary Winding

• Internal 1 ms Soft−start

• Auto−recovery Internal Output Short−circuit Protection

• Frequency Jittering for Better EMI Signature

• Below 100 mW Standby Power if Auxiliary Winding is Used

• Internal Temperature Shutdown

• Direct Optocoupler Connection

• SPICE Models Available for TRANsient and AC Analysis

• This is a Pb−Free Device

DS(on)

of 11 W

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DIAGRAMS

PDIP−7

8

1

1

yy = 06 (65 kHz), 10 (100 kHz)
y = A (65 kHz), B (100 kHz)
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G or G = Pb−Free Package

(*Note: Microdot may be in either location)

CASE 626A

AP SUFFIX

SOT−223

4

CASE 318E

ST SUFFIX

PIN CONNECTIONS

PDIP−7

V

1

CC

NC

2

GND

3

FB

4

(Top View)

SOT−223

V

1

CC

FB

2

1

1

8

7

5

MARKING

P1015APyy

AWL

YYWWG

4

AYW

1015y G

G

GND

GND

DRAIN

4

GND

Typical Applications

• Low Power ac−dc Adapters for Chargers

• Auxiliary Power Supplies (USB, Appliances, TVs, etc.)

© Semiconductor Components Industries, LLC, 2011

March, 2011 − Rev. 3

DRAIN

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 20 of this data sheet.

1 Publication Order Number:

3

(Top View)

NCP1015/D

Indicative Maximum Output Power from NCP1015

R

− I

DS(on)

11 W − 450 mA DSS

11 W − 450 mA Auxiliary Winding

1. Informative values only, with: T

100−250 Vac

p

= 50°C, circuit mounted on minimum copper area as recommended.

amb

+

NCP1015

+

230 Vac 100 − 250 Vac

14 W 6.0 W

19 W 8.0 W

18

27

3

45

V

out

+

Figure 1. Typical Application Example

PIN FUNCTION DESCRIPTION

Pin No.

SOT−223 PDIP−7

1 1 V

− 2 NC − −

− 3 GND The IC Ground −

2 4 FB Feedback Signal Input By connecting an optocoupler to this pin, the peak current

3 5 DRAIN Drain Connection The internal drain MOSFET connection.

− − − − −

− 7 GND The IC Ground −

4 8 GND The IC Ground −

Pin Name Function Description

CC

Powers the Internal Circuitry This pin is connected to an external capacitor of typically

10 mF. The natural ripple superimposed on the V
participates to the frequency jittering. For improved
standby performance, an auxiliary VCC can be connected
to Pin 1. The VCC also includes an active shunt which
serves as an opto fail−safe protection.

setpoint is adjusted accordingly to the output power
demand.

GND

CC

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2

NCP1015

V

CC

1

V

CC

Startup Source

UVLO

Management

Drain

High when VCC t 3 V

250 ns

L.E.B.

R

sense

8

GND

NC

2

4 V

EMI Jittering

65 kHz

100 kHz

Set

Clock

Reset

Flip−Flop

D

= 65%

max

7

Q

GND

Driver

Reset

V

18 k

CC

Error flag armed?

3

GND

−

+

−

+

0.5 V

+

-

Drain

5

FB

Overload?

Startup Sequence

Soft−Start

Overload

4

DRAIN

Figure 2. Simplified Internal Circuit Architecture

MAXIMUM RATINGS

Symbol Rating Value Unit

V

CC

Vds Drain voltage −0.3 to 700 V

Ids

pk

I_V

CC

R

q

JL

R

q

JA

R

q

JL

R

q

JA

TJ

MAX

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.

Power Supply voltage on all pins, except pin 5 (drain) −0.3 to 10 V

Drain peak current during transformer saturation 1 A

Maximum current into pin 1 15 mA

Thermal Characteristics

°C/W

P Suffix, Case 626A

Junction−to−Lead

9.0

Junction−to−Air, 2.0 oz (70 mm) Printed Circuit Copper Clad

0.36 Sq. Inch (2.32 Sq. Cm)

1.0 Sq. Inch (6.45 Sq. Cm)

77
60

ST Suffix, Plastic Package Case 318E

Junction−to−Lead

14

Junction−to−Air, 2.0 oz (70 mm) Printed Circuit Copper Clad

0.36 Sq. Inch (2.32 Sq. Cm)

1.0 Sq. Inch (6.45 Sq. Cm)

74
55

Maximum Junction Temperature 150 °C

Storage Temperature Range −60 to +150 °C

ESD Capability, Human Body Model (HBM) (All pins except HV) 2 kV

ESD Capability, Machine Model (MM) 200 V

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3

NCP1015

ELECTRICAL CHARACTERISTICS (For typical values T

Symbol

Rating Pin Min Typ Max Unit

=25°C, for min/max values TJ=−40°Cto125°C, VCC=8V unless otherwise noted)

J

SUPPLY SECTION AND VCC MANAGEMENT

V

CC(off)

V

CC(on)

V

CCLATCH

DV

VCC increasing level at which the current source turns−off 1 7.9 8.5 9.1 V

VCC decreasing level at which the current source turns−on 1 6.9 7.5 8.1 V

Decreasing level at which the Latch−off phase Ends 1 4.4 4.7 5.1 V

Hysteresis between V

CC

CC(off)

1 − 1.0 −

ICC1 Internal IC consumption, MOSFET switching at 65 kHz 1 − 0.92 1.1 mA

ICC1 Internal IC consumption, MOSFET switching at 100 kHz 1 − 0.95 1.15 mA

V

clamp

Active zener voltage positive offset to V

CC(off)

1 140 200 300 mV

POWER SWITCH CIRCUIT

R

DS(on)

V

I

DS(off)

t
t

dsb

on

off

Power Switch Circuit on−state resistance (Id = 50 mA)
T

= 25°C

J

T

= 125°C

J

Power Switch Circuit & Startup breakdown voltage
(I

= 100 mA, TJ = 25°C)

DS(off)

Power Switch & Startup breakdown voltage off−state leakage current
T

= −40°C (Vds = 650 V)

J

T

= 25°C (Vds = 700 V)

J

T

= 125°C (Vds = 700 V)

J

Switching characteristics (RL = 50 W, Vds set for Ids = 0.7 x Ids

lim

)
Turn−on time (90% − 10%)
Turn−off time (10% − 90%)

5
5

−

−

11

−

19
24

5 700 − − V

5
5
5

5
5

−

−

−

−

−

70
50
30

20
10

120

−

−

−

−

INTERNAL START−UP CURRENT SOURCE

IC1

High−voltage current source, VCC = 8 V 0°C < TJ < 125°C

−40°C < T

< 125°C

J

1 5.0

5.0

8.0

8.0

10
11

IC2 High−voltage current source, VCC = 0 1 − 10 − mA

CURRENT COMPARATOR TJ = 255C (Note 2)

I

peak

I

Lskip

t

t

DEL

LEB

Maximum internal current set−point 5 405 450 495 mA

Default internal current set−point for skip cycle operation,
percentage Ipeak

max

− − 25 − %

Propagation delay from current detection to drain OFF state − − 125 − ns

Leading Edge Blanking Duration − − 250 − ns

INTERNAL OSCILLATOR

f

OSC

f

OSC

f

dither

D

max

Oscillation frequency, 65 kHz version, TJ = 25°C (Note 2) 59 65 71 kHz

Oscillation frequency, 100 kHz version, TJ = 25°C (Note 2) 90 100 110 kHz

Frequency dithering compared to switching frequency (with active DSS) − ±3.3 − %

Maximum Duty−cycle 62 67 72 %

FEEDBACK SECTION

R

up

t

ss

Internal pull−up resistor 4 − 18 −

Internal soft−start (guaranteed by design) − − 1.0 − ms

SKIP CYCLE GENERATION

V

skip

Default skip mode level on FB pin 4 0.5 V

TEMPERATURE MANAGEMENT

TSD

Temperature shutdown 150 °C

Hysteresis in shutdown 50 °C

2. See characterization curves for temperature evolution

W

mA

ns

mA

kW

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4

NCP1015

TYPICAL CHARACTERISTICS

−2

−3

−4

−5

−6

−7

IC1 ( mA)

−8

−9

−10

−11

−12

−20 0 20 40 60 100 120

−40 80

TEMPERATURE (°C)

Figure 3. IC1 @ VCC = 8.0 V, FB = 1.5 V

vs. Temperature

0.40

0.38

0.36

0.34

0.32

0.30

0.28

ICC2 (mA)

0.26

0.24

0.22

0.20

−40 0 20 40 60 80 120

−20 100

TEMPERATURE (°C)

Figure 5. ICC2 @ VCC = 6.0 V, FB = Open

vs. Temperature

1.5

1.4

1.3

1.2

1.1

1.0

0.9

ICC1 (mA)

0.8

0.7

0.6

0.5

−20 0 20 40 60 100 120

−40 80

TEMPERATURE (°C)

Figure 4. ICC1 @ VCC = 8.0 V, FB = 1.5 V

vs. Temperature

9.0

8.9

8.8

8.7

8.6

8.5

VCC−OFF ( V )

8.4

8.3

8.2

−40 0 20 40 60 100 120

−20 80

TEMPERATURE (°C)

Figure 6. VCC OFF, FB = 1.5 V vs. Temperature

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5

NCP1015

TYPICAL CHARACTERISTICS

8.0

7.9

7.8

7.7

7.6

7.5

7.4

VCC−ON ( V)

7.3

7.2

7.1

7.0

−40 80 80−20

−20 0 20 40 60 100 120

TEMPERATURE (°C)

Figure 7. VCC ON, FB = 3.5 V vs. Temperature

600

550

500

69

68

67

DUTY CYCLE (%)

66

−40 0 20 40 60 100 120

TEMPERATURE (°C)

Figure 8. Duty Cycle vs. Temperature

450

Ipeak (mA)

400

350

−40 0 20 40 60 100 120

−20 80

TEMPERATURE (°C)

Figure 9. Ipeak−RR, VCC = 8.0 V, FB = 3.5 V

vs. Temperature

110

100

90

(kHz)

80

OSC

f

70

60

50

−20 0 20 40 60 100 120

−40 80 60−20

100 kHz

(W)

R

65 kHz

TEMPERATURE (°C)

Figure 10. Frequency vs. Temperature

25

20

15

DSon

10

5

0

−40 0 20 40 80 100 120
TEMPERATURE (°C)

Figure 11. ON Resistance vs. Temperature

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6

NCP1015

APPLICATION INFORMATION

Introduction

The NCP1015 offers a complete current−mode control
solution (actually an enhanced NCP1200 controller section)
together with a high−voltage power MOSFET in a
monolithic structure. The component integrates everything
needed to build a rugged and low−cost Switch−Mode Power
Supply (SMPS) featuring low standby power. The quick
selection table details the differences in operating
frequency.

• No need for an auxiliary winding: ON Semiconductor

Very High Voltage Integrated Circuit technology lets
you supply the IC directly from the high−voltage dc
rail. We call it Dynamic Self−Supply (DSS). This
solution simplifies the transformer design and ensures a
better control of the SMPS in difficult output
conditions, e.g. constant current operations. However,
for improved standby performance, an auxiliary
winding can be connected to the V

pin to disable the

CC

DSS operation.

• Short−circuit protection: by permanently monitoring

the feedback line activity, the IC is able to detect the
presence short−circuit, immediately reducing the output
power for a total system protection. Once the short has
disappeared, the controller resumes and goes back to
normal operation.

• Low standby−power: If SMPS naturally exhibit a good

efficiency at nominal load, they begin to be less
efficient when the output power demand diminishes. By
skipping un−needed switching cycles, the NCP1015
drastically reduces the power wasted during light load
conditions. An auxiliary winding can further help
decreasing the standby power to extremely low levels
by invalidating the DSS operation. Typical
measurements show results below 80 mW @ 230 Vac
for a typical 7 W universal power supply.

• No acoustic noise while operating: Instead of skipping

cycles at high peak currents, the NCP1015 waits until
the peak current demand falls below a fixed 0.25 of the
maximum limit. As a result, cycle skipping can take
place without having a singing transformer. You can
thus select cheap magnetic components free of noise
problems.

• SPICE model: a dedicated model to run transient

cycle−by−cycle simulations is available but also an

averaged version to help you closing the loop.
Ready−to−use templates can be downloaded in
OrCAD’s PSpice, and INTUSOFT’s IsSpice4 from ON
Semiconductor web site, NCP1015 related section.

Dynamic Self−Supply

When the power supply is first powered from the mains
outlet, the internal current source (typically 8 mA) is biased
and charges up the V
the voltage on this V

capacitor from the drain pin. Once

CC

capacitor reaches the V

CC

CC(off)

level
(typically 8.5 V), the current source turns off and pulses are
delivered by the output stage: the circuit is awake and
activates the power MOSFET. Figure 12 details the internal
circuitry:

Vref OFF = 8.5 V
Vref ON = 7.5 V
Vref

= 4.7 V

Latch

+

-

Internal Supply

+
Vref

Figure 12. The Current Source Regulates V

V

CC(off)

+200 mV

(8.7 V Typ.)

by Introducing a Ripple

Drain

Startup Source

V

CC

+

CV

CC

CC

Being loaded by the circuit consumption, the voltage on
the V
detects that V
internal current source to bring V

capacitor goes down. When the DSS controller

CC

has reached 7.5 V (V

CC

CC

), it activates the

CC(on)

toward 8.5 V and stops
again: a cycle takes place whose low frequency depends on
the V
takes place on the V
(V

capacitor and the IC consumption. A 1 V ripple

CC

pin whose average value equals

CC

CC(off)

+ V

) / 2. Figure 13 shows a typical operation

CC(on)

of the DSS.

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7

NCP1015

8.00

Vcc

6.00

4.00

Device

2.00

0

internally
pulses

Startup period

8.5V

Figure 13. The Charge/Discharge Cycle over a 10 mF VCC Capacitor

As one can see, the VCC capacitor shall be dimensioned to
offer an adequate startup time, i.e. ensure regulation is
reached before V

crosses 7.5 V (otherwise the part enters

CC

the fault condition mode). If we know that DV = 1 V and
ICC1 is 1.2 mA (for instance we selected a 11 W device
switching at 65 kHz), then the V

capacitor can be

CC

calculated using:

ICC1 @ t

C w

DV

startup

(eq. 1)

Let’s suppose that the SMPS needs 10 ms to startup, then
we will calculate C to offer a 15 ms period. As a result, C
should be greater than 18 mF thus the selection of a 33 mF /
16 V capacitor is appropriate.

Short Circuit Protection

The internal protection circuitry involves a patented
arrangement that permanently monitors the assertion of an
internal error flag. This error flag is, in fact, a signal that
instructs the controller that the internal maximum peak
current limit is reached. This naturally occurs during the
startup period (V

is not stabilized to the target value) or

out

when the optocoupler LED is no longer biased, e.g in a
short−circuit condition or when the feedback network is
broken. When the DSS normally operates, the logic checks
for the presence of the error flag every time V
V

. If the error flag is low (peak limit not active) then

CC(on)

crosses

CC

the IC works normally. If the error signal is active, then the
NCP1015 immediately stops the output pulses, reduces its
internal current consumption and does not allow the startup
source to activate: V

drops toward ground until it reaches

CC

7.5V

the so−called latch−off level, where the current source
activates again to attempt a new re−start. If the error has
gone, the IC automatically resumes its operation. If the
default is still there, the IC pulses during 8.5 V down to 7.5 V
and enters a new latch−off phase. The resulting burst
operation guarantees a low average power dissipation and
lets the SMPS sustain a permanent short−circuit. Figure 14
presents the corresponding diagram:

Current Sense

Information

V

CC

V

CC(on)

Flag

+

−

Latch

Reset

FB

4 V

Division

Max

Ip

Clamp

Active?

Figure 14. Simplified NCP1015 Short−Circuit

Detection Circuitry

The protection burst duty−cycle can easily be computed

through the various timing events as portrayed by Figure 15:

To

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8

NCP1015

Ts w

1 V Ripple

Tstart

TLatch

Latch−off

Level

Figure 15. NCP1015 Facing a Fault Condition (Vin = 150 Vdc)

The rising slope from the latch−off level up to 8.5 V is
expressed by:

P

+ Vin@ ICC1

DSS

start

DV1 @ C

+

IC1

t

The time during which the IC actually pulses is given by:

DV2 @ C

tsw+

ICC1

Finally, the latch−off time can be derived using the same
formula topology:

latch

DV3 @ C

+

ICC2

t

From these three definitions, the burst duty−cycle D can
be computed:

t

start

ǒ

sw

) tsw) t

DV2

DV2

DV1

)

ICC1

IC1

latch

)

DV3

ICC2

(eq. 2)

Ǔ

(eq. 3)

D +

D +

ICC1 @

t

Feeding the equation with values extracted from the
parameter section gives a typical duty−cycle D of 13%,
precluding any lethal thermal runaway while in a fault
condition.

DSS Internal Dissipation

The Dynamic Self−Supplied pulls the energy out from the
drain pin. In the Flyback−based converters, this drain level
can easily go above 600 V peak and thus increase the stress
on the DSS startup source. However, the drain voltage
evolves with time and its period is small compared to that of
the DSS. As a result, the averaged dissipation, excluding
capacitive losses, can be derived by:

P

+ ICC1 @t V

DSS

DS(t)

u

(eq. 4)

Figure 16 shows a typical drain−ground wave−shape

where leakage effects have been removed:

Vds(t)

toff

Vr

Vin

ton

Ts w

dt

Figure 16. A Typical Drain−ground Waveshape

where Leakage Effects are Not Accounted for

By looking at Figure 16 the average result can easily be

derived by additive square area calculation:

t

off

t V

u+ Vin@ (1 * D) ) Vr@

DS(t)

(eq. 5)

t

sw

By developing Equation 5 we obtain:

t V

DS(t)

t

can be expressed by:

off

u+ Vin* Vin@

t

+ Ip@

off

t

on

t

sw

L

p

V

r

) Vr@

t

off

(eq. 6)

t

sw

(eq. 7)

ton can be evaluated by:

L

ton+ Ip@

p

V

in

(eq. 8)

t

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9

NCP1015

Plugging Equation 7 and Equation 8 into Equation 6 leads
to <V

> = Vin and thus:

ds(t)

P

DSS

+ Vin@ ICC1

(eq. 9)

The worse case occurs at high line, when Vin equals
370 Vdc. With ICC1 = 1.2 mA (65 kHz version), we can
expect a DSS dissipation around 440 mW. If you select a
higher switching frequency version, the ICC1 increases and
it is likely that the DSS consumption exceeds 500 mW. In
that case, we recommend adding an auxiliary winding in
order to offer more dissipation room to the power MOSFET.

Please read application note AND8125/D “Evaluating the
power capability of the NCP101X members” to help
selecting the right part / configuration for your application.

Lowering the Standby Power with an Auxiliary
Winding

The DSS operation can bother the designer when a) its
dissipation is too high b) extremely low standby power is a
must. In both cases, one can connect an auxiliary winding to
disable the self−supply. The current source then ensures the
startup sequence only and stays in the off state as long as
V

does not drop below V

CC

that the insertion of a resistor (R
dc level and the V

pin is mandatory a) not to damage the

CC

or 7.5 V. Figure 17 shows

CC(on)

) between the auxiliary

limit

internal 8.7 V zener diode during an overshoot for instance
(absolute maximum current is 15 mA) b) to implement the
fail−safe optocoupler protection as offered by the active
clamp. Please note that there cannot be bad interaction
between the clamping voltage of the internal zener and
V
of V

since this clamping voltage is actually built on top

CC(off)

with a fixed amount of offset (200 mV typical).

CC(off)

Self−supplying controllers in extremely low standby
applications often puzzles the designer. Actually, if a SMPS
operated at nominal load can deliver an auxiliary voltage of
an arbitrary 16 V (V
10 V (V

) when entering standby. This is because the

stby

), this voltage can drop to below

nom

recurrence of the switching pulses expands so much that the
low frequency re−fueling rate of the V

capacitor is not

CC

enough to keep a proper auxiliary voltage. Figure 18 shows
a typical scope shot of a SMPS entering deep standby
(output un−loaded). So care must be taken when calculating
R

1) to not excess the maximum pin current in normal

limit

operation but 2) not to drop too much voltage over R

limit

when entering standby. Otherwise the DSS could reactivate
and the standby performance would degrade. We are thus
able to bound R

between two equations:

limit

lim

v

V

* V

stby

ICC1

CC(on)

(eq. 10)

V

* V

nom

clamp

I

trip

v R

Where:

V

is the auxiliary voltage at nominal load

nom

V

is the auxiliary voltage when standby is entered

stdby

is the current corresponding to the nominal operation.

I

trip

It thus must be selected to avoid false tripping in overshoot
conditions.

ICC1 is the controller consumption. This number slightly
decreases compared to ICC1 from the spec since the part in
standby does almost not switch.

V

is the level above which V

CC(on)

must be maintained

aux

to keep the DSS in the OFF mode. It is good to shoot around
8 V in order to offer an adequate design margin, e.g. to not
re−activate the startup source (which is not a problem in
itself if low standby power does not matter)

Since R
keep V
select a V

shall not bother the controller in standby, e.g.

limit

to around 8 V (as selected above), we purposely

aux

well above this value. As explained before,

nom

experience shows that a 40% decrease can be seen on
auxiliary windings from nominal operation down to standby
mode. Let’s select a nominal auxiliary winding of 20 V to
offer sufficient margin regarding 8 V when in standby (R

limit

also drops voltage in standby). Plugging the values in
Equation 10 gives the limits within which R

limit

shall be

selected:

20 * 8.7

6.3 m

that is to say: 1.8 kW < R

v R

limit

12 * 8

v

limit

1.1 m

< 3.6 kW.

(eq. 11)

If we are designing a power supply delivering 12 V, then
the ratio auxiliary/power must be: 12 / 20 = 0.6. The I
current has to not exceed 6.4 mA. This will occur when V

CC

aux

grows−up to: 8.7 V + 1.8 k x (6.4 m + 1.1 m) = 22.2 V for
the first boundary or 8.7 V + 3.6 k x (6.4 m +1.1 m) = 35.7 V
for second boundary. On the power output, it will
respectively give 22.6 x 0.6 = 13.3 V and 35.7 x 0.6 = 21.4 V.
As one can see, tweaking the R

value will allow the

limit

selection of a given overvoltage output level. Theoretically
predicting the auxiliary drop from nominal to standby is an
almost impossible exercise since many parameters are
involved, including the converter time constants. Fine
tuning of R
experiments on a breadboard to check V

thus requires a few iterations and

limit

variations but

aux

also output voltage excursion in fault. Once properly
adjusted, the fail−safe protection will preclude any lethal
voltage runaways in case a problem would occur in the
feedback loop.

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10

NCP1015

V

CC(off)

V

CC(on)

= 8.5 V

= 7.5 V

+

+

-

+

+

−

Drain

Startup Source

V

CC

+ +

Ground

Rlimit

CVCC CAux

D1

Laux

Figure 17. A Detailed View of the NCP1015 with Properly Connected Auxiliary Winding

u30 ms

Figure 18. The Burst Frequency becomes So Low that it is Difficult to

Keep an Adequate Level on the Auxiliary V

Lowering the Standby Power with Skip−cycle

Skip cycle offers an efficient way to reduce the standby
power by skipping unwanted cycles at light loads. However,
the recurrent frequency in skip often enters the audible range
and a high peak current obviously generates acoustic noise
in the transformer. The noise takes its origins in the
resonance of the transformer mechanical structure which is

CC

excited by the skipping pulses. A possible solution,
successfully implemented in the NCP1200 series, also
authorizes skip cycle but only when the power demand as
dropped below a given level. At this time, the peak current
is reduced and no noise can be heard. Figure 19 shows the
peak current evolution of the NCP1015 entering standby:

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11

NCP1015

100%

Peak current
at nominal power

Skip−cycle
current limit

25%

Figure 19. Low Peak Current Skip−Cycle Guarantees Noise−Free Operation

Full power operation involves the nominal switching
frequency and thus avoids any noise when running.

Experiments carried on a 5 W universal mains board
unveiled a standby power of 300 mW @ 230 Vac with the
DSS activated and dropped to less than 100 mW when an
auxiliary winding is connected.

Frequency Jittering for Improved EMI Signature

By sweeping the switching frequency around its nominal
value, it spreads the energy content on adjacent frequencies
rather than keeping it centered in one single ray. This offers

VCC Ripple

VCC

65 kHz

OFF

the benefit to artificially reduce the measurement noise on
a standard EMI receiver and pass the tests more easily. The
EMI sweep is implemented by routing the V

CC

ripple
(induced by the DSS activity) to the internal oscillator. As a
result, the switching frequency moves up and down to the
DSS rhythm. Typical deviation is

±4% of the nominal

frequency. With a 1 V peak−to−peak ripple, the frequency
will equal 65 kHz in the middle of the ripple and will
increase as V

rises or decrease as VCC ramps down.

CC

Figure 20 shows the behavior we have adopted:

67.6 kHz

62.4 kHz

VCC

ON

Figure 20. The VCC Ripple Causes the Frequency Jittering on the Internal Oscillator Saw−tooth

(65 kHz version)

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12

Internal Sawtooth

NCP1015

Soft−Start

The NCP1015 features an internal 1 ms soft−start
activated during the power on sequence (P
V

reaches V

CC

, the peak current is gradually

CC(off)

). As soon as

ON

increased from nearly zero up to the maximum internal
clamping level (e.g. 350 mA). This situation lasts 1 ms and
further to that time period, the peak current limit is blocked
to the maximum until the supply enters regulation. The

V

CC

0 V (Fresh PON)

or

4.7 V (Overload)

Current

Sense

soft−start is also activated during the over current burst
(OCP) sequence. Every re−start attempt is followed by a
soft−start activation. Generally speaking, the soft−start will
be activated when V

ramps up either from zero (fresh

CC

power−on sequence) or 4.5 V, the latch−off voltage
occurring during OCP. Figure 21 shows the soft−start
behavior. The time scales are purposely shifted to offer a
better zoom portion.

8.5 V

Max Ip

Figure 21. Soft−Start is Activated During a Start−up Sequence or an OCP Condition

Non−latching Shutdown

In some cases, it might be desirable to shut off the part
temporarily and authorize its re−start once the default has
disappeared. This option can easily be accomplished
through a single NPN bipolar transistor wired between FB

ON/OFF

Figure 22. A Non−latching Shutdown where Pulses are Stopped as long as the NPN is Biased

1.0 ms

and ground. By pulling FB below the internal skip level
(V

), the output pulses are disabled. As soon as FB is

skip

relaxed, the IC resumes its operation. Figure 22 shows the
application example:

18

27

3

45

+

CV

CC

Transformer

Full Latching Shutdown

Other applications require a full latching shutdown, e.g.
when an abnormal situation is detected (over temp or
overvoltage). This feature can easily be implemented
through two external transistors wired as a discrete SCR.

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When the OVP level exceeds the zener breakdown voltage,
the NPN biases the PNP and fires the equivalent SCR,
permanently bringing down the FB pin. The switching
pulses are disabled until the user un−plugs the power supply.

13

NCP1015

Rhold

DSS

12 k

BAT54

+ P

MOSFET

Clamping Elements

OVP

10 k

0.1 mF

10 k

Figure 23. Two Bipolar Transistors Ensures a Total Latch−off of the SMPS in Presence of an OVP

R

ensures that the SCR stays on when fired. The bias

hold

current flowing through R
the V

ramp up (8.5 V) and down (7.5 V) when the SCR

CC

should be small enough to let

hold

is fired. The NPN base can also receive a signal from a
temperature sensor. Typical bipolar can be MMBT2222 and
MMBT2907 for the discrete latch. The NST3946 features
two bipolar NPN + PNP in the same package and could also
be used.

Power Dissipation and Heatsinking

The power dissipation of NCP1015 consists of the
dissipation DSS current−source (when active) and the
dissipation of MOSFET. Thus P

tot

= P
When the PDIP7 package is surrounded by copper, it
becomes possible to drop its thermal resistance
junction−to−ambient, R

down to 75°C/W and thus

JA

q

dissipate more power. The maximum power the device can
thus evacuate is:

18

27

3

45

+

CV

CC

P

+

max

T

J(max)

Transformer

* T

AMB(max)

R

qJA

which gives around 1 W for an ambient of 50°C. The losses
inherent to the MOSFET R

can be evaluated using the

DS(on)

following formula:

1

P

+

mos

2

@ I

@ D @ R

p

3

DS(on)

where Ip is the worse case peak current (at the lowest line
input), D is the converter operating duty−cycle and R
the MOSFET resistance for TJ = 100°C. This formula is only
valid for Discontinuous Conduction Mode (DCM)

.

operation where the turn−on losses are null (the primary
current is zero when you re−start the MOSFET). Figure 24
gives a possible layout to help dropping the thermal
resistance. When measured on a 35 mm (1 oz.) copper
thickness PCB, we obtained a thermal resistance of 75°C/W:

(eq. 12)

(eq. 13)

DS(on)

DC

Figure 24. A Possible PCB Arrangement to Reduce the Thermal Resistance Junction−to−Ambient

Design Procedure

The design of a SMPS around a monolithic device does
not differ from that of a standard circuit using a controller
and a MOSFET. However, one needs to be aware of certain
characteristics specific of monolithic devices:

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To Secondary Diode

1. In any case, the lateral MOSFET body−diode shall
never be forward biased, either during start−up
(because of a large leakage inductance) or in
normal operation as shown by Figure 25.

14

NCP1015

ǒ

Ǔ

350

250

150

50.0

> 0 !!

−50.0

1.004M 1.011M 1.018M 1.025M 1.032M

Figure 25. The Drain−Source Wave Shall Always be Positive . . .

As a result, the Flyback voltage which is reflected on
the drain at the switch opening cannot be larger than
the input voltage. When selecting components, you
thus must adopt a turn ratio which adheres to the
following equation:

N @ (V

) Vf) t V

out

IN(min)

For instance, if you operate from a 120 V dc rail and
you deliver 12 V, we can select a reflected voltage of
100 VDC maximum: 120 − 100 > 0. Therefore, the
turn ratio Np : Ns must be smaller than 100 / (12 +

1) = 7.7 or Np : Ns < 7.7. We will see later on how
it affects the calculation.

2. Current−mode architecture is, by definition,
sensitive to subharmonic oscillations.
Subharmonic oscillations only occur when the
SMPS is operating in Continuous Conduction
Mode (CCM) together with a duty−cycle greater
than 50%. As a result, we recommend operating
the device in DCM only, whatever duty−cycle it
implies (max. = 65%).

3. Lateral Mosfets have a poorly doped body−diode
which naturally limits their ability to sustain the
avalanche. A traditional RCD clamping network
shall thus be installed to protect the MOSFET. In
some low power applications, a simple capacitor
can also be used since:

V

DRAIN(max)

+ Vin) N @ (V

) Vf) ) Ip@

out

Ǹ

where Lf is the leakage inductance, C
capacitance at the drain node (which is increased by
the capacitor you will wire between drain and
source), N the Np : Ns turn ratio, V
voltage, V
finally, I

the secondary diode forward drop and

f

the maximum peak current. Worse case

p

out

occurs when the SMPS is very close to regulation,

(eq. 14)

L

f

(eq. 15)

C

tot

the total

tot

the output

e.g. the V

target is almost reached and Ip is still

out

pushed to the maximum.

Taking into account all previous remarks, it becomes
possible to calculate the maximum power that can be
transferred at low line:

When the switch closes, V
inductance L

until the current reaches the level imposed by

p

is applied across the primary

in

the feedback loop. The duration of this event is called the ON
time and can be defined by:

Lp@ I

ton+

p

V

in

(eq. 16)

At the switch opening, the primary energy is transferred
to the secondary and the flyback voltage appears across L
reseting the transformer core with a slope of:

the t

time is thus:

off

N @ (V

t

+

off

N @ (V

) Vf)

out

L

p

Lp@ I

out

p

) Vf)

@ t

off

(eq. 17)

If one wants to keep DCM only, but still need to pass the
maximum power, we will not allow a dead−time after the
core is reset, but rather immediately re−start. The switching
time t

tsw+ t

can be expressed by:

sw

) ton+ Lp@ Ip@

off

1

)

V

in

N @ (V

1

out

) Vf)

(eq. 18)

The Flyback transfer formula dictates that:

P

out

1

+

h

@ Lp@ I

2

2

@ f

p

sw

(eq. 19)

which, by extracting Ip and plugging into Equation 19 leads to:

tsw+ L

p

Ǹ

out

h @ fsw@ L

1

ǒ

@

)

V

p

in

N @ (V

1

out

) Vf)

Ǔ

(eq. 20)

2 @ P

Extracting Lp from Equation 20 gives:

,

p

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15

NCP1015

(Vin@ Vr)2@ h

@ (V

out

with Vr = N . (V

If L

critical gives the inductance value above which

p

L

+ Vf) and h the efficiency.

out

Pcritical

+

2 @ f

sw

@ [P

DCM operation is lost, there is another expression we can
write to connect L

, the primary peak current bounded by the

p

NCP1015 and the maximum duty−cycle that needs to stay
below 50%:

L

P(max)

P

max

+ t

+

sw

max

2

@ V

@ V

I

P(max)

IN(min)

IN(min)

2

@ V

@ t

r

sw

2

@ h @

(eq. 22)

(2L

P(max)

D

From Equation 22 we obtain the operating duty−cycle D:

Ip@ L

Vin@ t

sw

p

(eq. 24)

D +

This lets us calculate the RMS current circulating in the

MOSFET:

+ Ip@

Ǹ

3

(eq. 25)

I

D(rms)

D

From this equation, we obtain the average dissipation in

the MOSFET:

1

P

+

avg

2

@ I

@ D @ R

p

3

DS(on)

(eq. 26)

to which switching losses shall be added.

If we stick to Equation 23, compute Lp and follow the
above calculations, we will discover that a power supply
built with the NCP1015 and operating from a 100 Vac line
minimum will not be able to deliver more than 7 W
continuous, regardless of the selected switching frequency
(however the transformer core size will go down as f

sw

is
increased). This number grows up significantly when
operated from single European mains (18 W).

For more different flyback converters then are the below

examples we recommend use following support:

1) Application note AND8125/D “Evaluating the power

capability of the NCP101X members”

2) Application note AND8134/D “Designing Converters

with the NCP101X members.”

3) Application note AND8142/D “A 6W/12W Universal

mains adapter with NCP101X series”.

4) The PSpice or Orcad simulation models

Example 1.: A 12 V 7.0 W SMPS Operating on a Large
Mains with NCP1015:

Vin = 100 Vac ÷ 250 Vac or 140 Vdc ÷ 350 Vdc once
rectified, assuming a low bulk ripple

Efficiency = 80%

V

= 12 V, I

out

= 65 kHz

f

sw

I

= 450 mA − 10% = 405 mA

P(max)

= 580 mA

out

2

) 2 @ Vr@ Vin) V

r

where V

IN(min)

(eq. 21)

2

)]

in

corresponds to the lowest bulk voltage,
hence the longest ton duration or largest duty−cycle. I
is the available peak current from the considered part, e.g.
450 mA typical for the NCP1015 (however, the minimum
value of this parameter shall be considered for reliable
evaluation). Combining Equations 21 and 22 gives the
maximum theoretical power you can pass respecting the
peak current capability of the NCP1015, the maximum
duty−cycle and the discontinuous mode operation:

f

P(max)

sw

VrV

IN(min)

) V

IN(min)

2

V

) 4L

r

2

)

(eq. 23)

Applying the above equations leads to :

Selected maximum reflected voltage = 120 V

with V

L

I

p

D

I

DRAIN(rms)

P

P

= 12 V, secondary drop = 0.5 V ³ Np : Ns = 1 : 0.1

out

critical = 3.9 mH

p

= 250 mA

= 0.39

max

= 90 mA

MOSFET

DSS

= 202 mW at R

= 1.2 mA x 350 V = 420 mW, if DSS is used

= 25 W (TJ > 100°C)

DS(on)

Secondary diode voltage stress = (350 x 0.1) + 12 = 47 V
(e.g. a MBRS360T3, 3 A / 60 V would fit)

Example 2.: A 12 V 16 W SMPS Operating on Narrow
European Mains with NCP1015:

Vin = 230 Vac ± 15%, or 276 Vdc ÷ 370 Vdc

Efficiency = 80%

= 12 V, I

V

out

= 65 kHz

f

sw

I

= 450 mA − 10% = 405 mA

P(max)

= 1.25 A

out

Applying the equations leads to :

Selected maximum reflected voltage = 250 V

with V

L

I

p

D

I

DRAIN(rms)

P

P

= 12 V, secondary drop = 0.5 V ³ Np : Ns = 1:0.05

out

= 7,2 mH

p

= 0.27 mA

= 0.41

max

= 100 mA

MOSFET

DSS

= 250 mW at R

= 1.2 mA x 370 V = 444 mW, if DSS is used below an

= 25 W (TJ > 100°C)

DS(on)

ambient of 50°C.

Secondary diode voltage stress = (370 x 0.05) + 12 = 30.5 V
(e.g. a MBRS340T3, 3 A / 40 V)

P(max)

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16

NCP1015

Please note that these calculations assume a flat DC rail
whereas a 10 ms ripple naturally affects the final voltage
available on the transformer end. Once the Bulk capacitor
has been selected, one should check that the resulting ripple
(min V

?) is still compatible with the above calculations.

bulk

As an example, to benefit from the largest operating range,
a 7 W board was built with a 47 mF bulk capacitor which
ensured discontinuous operation even in the ripple
minimum waves.

CVcc

HV

1

8

7

2

3

6

45

NCP1015

A

C

Figure 26. Different Options to Clamp the Leakage Spike

HV

Rclamp

CVcc

MOSFET Protection

As in any Flyback design, it is important to limit the drain
excursion to a safe value, e.g. below the MOSFET BVdss
which is 700 V. Figures 26A, B, and C present possible
implementations:

HV

1

2

3

45

NCP1015

B

Cclamp

D

8

7

6

CVc
c

Dz

1

2

3

45

NCP1015

C

D

8

7

6

Figure 26A: The simple capacitor limits the voltage
according to Equation 15. This option is only valid for low
power applications, e.g. below 5 W, otherwise chances exist
to destroy the MOSFET. After evaluating the leakage
inductance, you can compute C with Equation 15. Typical
values are between 100 pF and up to 470 pF. Large
capacitors increase capacitive losses.

Figure 26B: The most standard circuitry called the RCD
network. You calculate R

clamp

and C

clamp

using the

following formulas:

R

+

clamp

V

is usually selected 50−80 V above the reflected

clamp

value N x (V

2 @ V

@ (V

clamp

C

+

clamp

+ Vf). The diode needs to be a fast one and

out

clamp

L

leak

V

ripple

* (V

2

@ I

p

V

clamp

@ fsw@ R

) Vfsec) @ N)

out

@ f

sw

clamp

(eq. 27)

(eq. 28)

a MUR160 represents a good choice. One major drawback
of the RCD network lies in its dependency upon the peak

current. Worse case occurs when I
and V

is close to reach the steady−state value.

out

and Vin are maximum

p

Figure 26C: This option is probably the most expensive of
all three but it offers the best protection degree. If you need
a very precise clamping level, you must implement a zener
diode or a TVS. There are little technology differences
behind a standard zener diode and a TVS. However, the die
area is far bigger for a transient suppressor than that of zener.
A 5 W zener diode like the 1N5388B will accept 180 W peak
power if it lasts less than 8.3 ms. If the peak current in the
worse case (e.g. when the PWM circuit maximum current
limit works) multiplied by the nominal zener voltage
exceeds these 180 W, then the diode will be destroyed when
the supply experiences overloads. A transient suppressor
like the P6KE200 still dissipates 5 W of continuous power
but is able to accept surges up to 600 W @ 1 ms. Select the
zener or TVS clamping level between 40 to 80 volts above
the reflected output voltage when the supply is heavily
loaded.

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17

NCP1015

Typical Application Examples

A 6.5 W NCP1015−based Flyback converter. (For

evaluation a universal NCP1012 demo−board can be used)

Figure 27 shows a converter originally built with a
NCP1012 which can be easily used for evaluation of
NCP1015 device delivering 6.5 W from a universal volts

D1 D2
1N4007 1N4007

E1
10 m/400 V

E2
10 m/63 V

47 R

J1

CEE7.5/2

R1

1
2

2

D3 D4
1N4007 1N4007

Figure 27. A NCP1012−based Flyback Converter Delivering 6.5 W

input range. The board uses the Dynamic Self−Supply and
a simplified zener−type feedback. This configuration was
selected for cost reasons and a more precise circuitry can be
used, e.g. based on a TL431:

D6

8
7

6
5

B150

E3

470 m/25 V

ZD1

11 V

R3

100 R

2
1

CZM5/2

R4
180 R

R2
150 k

1

2
3
7

IC1

NCP1012

V

CC

GND
GND
GND

C1
2n2/Y

DRAIN

GND

FB

D5

U160

5

4

4

8

TR1

1

4

PC817

2n2/Y

IC2

C2

J2

The converter built according to Figure 28 layouts, gave
the following results:

Figure 28. The NCP1012−based PCB Layout and its Associated Component Placement

• Efficiency at V

• Efficiency at V

= 100 Vac and P

in

= 230 Vac and P

in

= 6.5 W = 75.7%

out

= 6.5 W = 76.5%

out

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18

NCP1015

A 7.0 W NCP1015−based Flyback Converter Featuring Low Standby Power

Figure 29 shows another typical application showing a
NCP1015−65 kHz operating in a 7 W converter up to 70°C
of ambient temperature. We can grow−up the output power
since an auxiliary winding is used, the DSS is disabled, and

Vbulk

1N4148
D4

C10

+

33 mF/25 V

R4 22

T1

Aux

C8
10 nF
400 V

thus offering more room for the MOSFET. In this
application, the feedback is made via a TLV431 whose low
bias current (100 mA min) helps to lower the no−load
standby power.

R7
100 k/
1 W

D2
MBRS360T3

T1

+ +

C6 C8

470 mF/16 V

L2

22 mH

12 V @

0.5 A

+

100 mF/16 V
C7

GND

C2

47 mF/

450 V

R2

3.3 k

NCP1015

+

+

100 mF/10 V
C3

1 8

V

GND

CC

NC

2

3

4

C9
1 nF

NC

FB

NC

DRAIN

D3

MUR160

7

5

IC1
SFH6156−2

C5

2.2 nF

Y1 Type

R3
1 k

C4

100 nF

IC2
TLV431

R5
39 k

R6

4.3 k

Figure 29. A Typical Converter Delivering 5 W from a Universal Mains

Measurements have been taken from a demonstration
board implementing Figure 12 12’s sketch and the following
results were achieved, with either the auxiliary winding in
place or through the Dynamic Self−Supply:

V

= 230 Vac, auxiliary winding, P

in

V

= 100 Vac, auxiliary winding, P

in

= 230 Vac, Dynamic Self−Supply, P

V

in

= 0, Pin = 60 mW

out

= 0, Pin = 42 mW

out

= 0, Pin =

out

300 mW

V

= 100 Vac, Dynamic Self−Supply, P

in

= 0, Pin =

out

130 mW

P

= 7 W, h = 81% @ 230 Vac, with aux winding

out

= 7 W, h = 81.3% @ 100 Vac, with aux winding

P

out

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For a quick evaluation of Figure 29 application example,

the following transformers are available from Coilcraft:

A9619−C, L

= 3 mH, Np : Ns = 1: 0.1, 7 W application on

p

universal mains, including auxiliary winding, NCP1015−
65 kHz

A0032−A, L

= 6 mH, Np : Ns = 1: 0.055, 10 W application

p

on European mains, DSS operation only, NCP1015−65 kHz

Coilcraft
1102 Silver Lake Road
CARY, IL 60013
Email: [e-mail]
Tel. : 847−639−6400
Fax.: 847−639−1469

19

NCP1015

ORDERING INFORMATION

Frequency

Device Order Number

NCP1015AP065G 65 PDIP−7

NCP1015AP100G 100 PDIP−7

NCP1015ST65T3G 65 SOT−223

NCP1015ST100T3G 100 SOT−223

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

(kHz)

Package Type Shipping

(Pb−Free)

(Pb−Free)

(Pb−Free)

(Pb−Free)

50 Units / Rail

4000 / Tape & Reel

†

R

DSon

(W)

11 450

11 450

11 450

11 450

Ipk (mA)

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20

NOTE 3

−T−

SEATING
PLANE

H

58

B

14

F

A

C

N

D

G

0.13 (0.005) B

NCP1015

PACKAGE DIMENSIONS

PDIP−7

AP SUFFIX

CASE 626A−01

ISSUE O

L

K

M

M

A

T

M

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).

4. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.

M

J

5. DIMENSIONS A AND B ARE DATUMS.

DIM MIN MAX MIN MAX

A 9.40 10.16 0.370 0.400
B 6.10 6.60 0.240 0.260
C 3.94 4.45 0.155 0.175
D 0.38 0.51 0.015 0.020

F 1.02 1.78 0.040 0.070
G 2.54 BSC 0.100 BSC
H 0.76 1.27 0.030 0.050

J 0.20 0.30 0.008 0.012
K 2.92 3.43 0.115 0.135

L 7.62 BSC 0.300 BSC
M --- 10 --- 10
N 0.76 1.01 0.030 0.040

INCHESMILLIMETERS

__

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21

b1

NCP1015

PACKAGE DIMENSIONS

SOT−223

ST SUFFIX

CASE 318E−04

ISSUE L

D

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

0.08 (0003)

e1

H

E

A1

4

123

e

E

b

q

A

SOLDERING FOOTPRINT*

3.8

0.15

2.0

0.079

2.3

0.091

L1

2.3

0.091

DIMAMIN NOM MAX MIN

A1 0.02 0.06 0.10 0.001

b 0.60 0.75 0.89 0.024

b1 2.90 3.06 3.20 0.115

c 0.24 0.29 0.35 0.009
D 6.30 6.50 6.70 0.249
E 3.30 3.50 3.70 0.130

e 2.20 2.30 2.40 0.087

e1
L1 1.50 1.75 2.00 0.060

H

C

E

q

MILLIMETERS

1.50 1.63 1.75 0.060

0.85 0.94 1.05 0.033

6.70 7.00 7.30 0.264
0° 10° 0° 10°

− −

INCHES

NOM MAX

0.064 0.068

0.002 0.004

0.030 0.035

0.121 0.126

0.012 0.014

0.256 0.263

0.138 0.145

0.091 0.094

0.037 0.041

0.069 0.078

0.276 0.287

6.3

0.248

2.0

0.079

mm

ǒ

1.5

0.059

SCALE 6:1

inches

Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

SENSEFET is a trademark of Semiconductor Components Industries, LLC (SCILLC).

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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NCP1015/D

22