Datasheet NC7SP17 Datasheet (Fairchild)

®

NC7SP17

NC7SP17 — TinyLogic

February 2011

TinyLogic® ULP Single Buffer with Schmitt Trigger Input

Features

 0.9V to 3.6V V  3.6V Over-Voltage Tolerant I/Os at V

0.9V to 3.6V

 Propagation Delay (t

 4.0ns Typical for 3.0V to 3.6V V  5.0ns Typical for 2.3V to 2.7V V  6.0ns Typical for 1.65V to 1.95V V  7.0ns Typical for 1.40V to 1.60V V  11.0ns Typical for 1.10V to 1.30V V  27.0ns Typical for 0.90V V

Supply Operation

CC

):

PD

CC

from

CC

 Power-Off High-Impedance Inputs and Outputs  Static Drive (I

 ± 2.6mA at 3.00V V  ± 2.1mA at 2.30V V  ± 1.5mA at 1.65V V  ± 1.0mA at 1.40V V  ± 0.5mA at 1.10V V  ± 20µA at 0.9V V

OH/IOL

):

CC

 Quiet Series™ Noise / EMI Reduction Circuitry  Ultra Small MicroPak™ Packages  Ultra Low Dynamic Power

Description

The NC7SP17 is a single buffer with Schmitt trigger input from Fairchild’s Ultra Low Power (ULP) series of TinyLogic®. Ideal for applications where battery life is critical, this product is designed for ultra low power consumption within the V

3.6V V

The internal circuit is composed of a minimum of inverter stages, including the output buffer, to enable ultra low static and dynamic power.

The NC7SP17, for lower drive requirements, is uniquely designed for optimized power and speed and is fabricated with an advanced CMOS technology to achieve best-in-class speed of operation, while maintaining extremely low CMOS power dissipation.

CC

.

operating range of 0.9V to

CC

ULP Single Buffer with Schmitt Trigger Input

Ordering Information

Part Number Top Mark Package Packing Method

NC7SP17P5X P17 5-Lead SC70, EIAJ SC-88a, 1.25mm Wide 3000 Units on Tape & Reel

NC7SP17L6X K4 6-Lead MicroPak™, 1.00mm Wide 5000 Units on Tape & Reel

NC7SP17FHX K4 6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch 5000 Units on Tape & Reel

®

A

Connection Diagrams

Notes:

1. TinyLogic ULP and ULP-A with up to 50% less power

2. Battery Life=(V

3. Assumes ideal 3.6V Lithium Ion battery with current

Figure 1. Battery Life vs. V

IEEE/IEC

consumption can extend battery life significantly.

24hrs/day; where, P

2

x V

x f.

CC

battery

x I

x 0.9) / (P

battery

=(ICC x VCC) + (CPD + CL)

device

) /

rating of 900mAH and derated 90% and device frequency at 10MHz, with C

Supply Voltage

CC

=15pF load.

L

NC7SP17 — TinyLogic

ULP Single Buffer with Schmitt Trigger Input

Pin Configurations

1

NC

2

A

3 4

GND

Figure 3. SC70 (Top View) Figure 4. MicroPak™ (Top Through View)

Function Table

Y=A

1

Y

Figure 2. Logic Symbol

5

V

CC

Y

Input Output

A Y

L L

H H

NC

GND

1

2

A

3

6

V

CC

5

NC

4

Y

L = Low Logic Level H = High Logic Level

Pin Definitions

Pin # SC70 Pin # MicroPak Name Description

1 1, 5 NC No Connect

2 2 A Input

3 3 GND Ground

4 4 Y Output

5 6 VCC Supply Voltage

®

NC7SP17 — TinyLogic

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

VCC Supply Voltage -0.5 4.6 V

VIN DC Input Voltage -0.5 4.6 V

V

DC Output Voltage

OUT

HIGH or LOW State

VCC=0V -0.5 4.6 V

IIK DC Input Diode Current at VIN < 0V -50 mA

V

< 0V -50

IOK DC Output Diode Current

OUT

V

> VCC +50

OUT

IOH / IOL DC Output Source/Sink Current ±50 mA

ICC or Ground DC VCC or Ground Current per Supply Pin ±50 mA

T

Storage Temperature Range -65 +150 °C

STG

TJ Junction Temperature Under Bias +150 °C

TL Junction Lead Temperature (Soldering, 10 Seconds) +260 °C

SC70-5 150

PD Power Dissipation at +85°C

MicroPak2™-6 120

ESD

Human Body Model JEDEC: JESD22-A114 4000

Charged Device Model JEDEC: JESD22-C101 2000

Note:

4. The IO maximum rating must be observed.

(4)

-0.5 VCC to +0.5 V

ULP Single Buffer with Schmitt Trigger Input

mA

mW MicroPak™-6 130

V

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Conditions Min. Typ. Max. Unit

VCC Supply Voltage 0.9 3.6 V

VIN Input Voltage

V

Output Voltage

OUT

IOH / IOL Output Current in IOH / IOL

TA Free Air Operating Temperature -40 +85 °C

t / V

JA

Minimum Input Edge Rate V

Thermal Resistance

Note:

5. Unused inputs must be held HIGH or LOW. They may not float.

(5)

0 3.6 V

HIGH or LOW State 0 V

VCC=0V 0 3.6

V

=3.0V to 3.6V ±2.6

CC

V

VCC=2.3V to 2.7V ±2.1

VCC=1.65V to 1.95V ±1.5

mA

VCC=1.40V to 1.60V ±1.0

VCC=1.10V to 1.30V ±0.5

VCC=0.9V 20.0 µA

=0.8V to 2.0V, VCC=3.0V 10 ns/V

IN

SC70-5 425

MicroPak™-6 500

°C/W

MicroPak2™-6 560

®

DC Electrical Characteristics

Symbol Parameter Conditions VCC (V)

0.90 0.30 0.60 0.30 0.60

1.10 0.40 1.00 0.40 1.00

VP Positive Threshold Voltage

VN Negative Threshold Voltage

VH Hysteresis Voltage

HIGH Level Output

VOH

Voltage

LOW Level Output

VOL

Voltage

IIN Input Leakage Current

Power Off Leakage

I

OFF

Current

Quiescent Supply

ICC

Current

=–20µA

I

OH

IOH=–0.5mA

IOH=–1mA

IOH=–1.5mA

IOH=–2.1mA

IOH=–2.6mA

=20µA

I

OL

IOL=0.5mA

IOL=1mA

IOL=1.5mA

IOL=2.1mA

IOL=2.6mA

0  V

 3.6V

IN

, VO)

0  (V

IN

 3.6V

or GND 0.90 to 3.60 0.9 0.9 µA

V

IN=VCC

1.40 0.50 1.20 0.50 1.20

1.65 0.70 1.50 0.70 1.50

2.30 1.00 1.90 1.00 1.90

3.00 1.50 2.60 1.50 2.60

0.90 0.10 0.60 0.10 0.60

1.10 0.15 0.70 0.15 0.70

1.40 0.20 0.80 0.20 0.80

1.65 0.25 0.90 0.25 0.90

2.30 0.40 1.15 0.40 1.15

3.00 0.6 1.50 0.60 1.50

0.90 0.07 0.50 0.07 0.50

1.10 0.08 0.60 0.08 0.60

1.40 0.09 0.80 0.09 0.80

1.65 0.10 1.00 0.10 1.00

2.30 0.25 1.10 0.25 1.10

3.00 0.60 1.80 0.60 1.80

0.90 V

1.10  VCC  1.30

1.40  VCC  1.60

1.65  VCC  1.95

2.30  VCC  2.70

3.00  VCC  3.60

1.10  V

1.40  V

1.65  V

2.30  V

3.00  V

 1.30

CC

 1.60

CC

 1.95

CC

 2.70

CC

 3.60

CC

0.90 0.1 0.1

1.10  VCC  1.30

1.40  VCC  1.60

1.65  VCC  1.95

2.30  VCC  2.70

3.00  VCC  3.60

1.10  V

1.40  V

1.65  V

2.30  V

3.00  V

 1.30

CC

 1.60

CC

 1.95

CC

 2.70

CC

 3.60

CC

0.90 to 3.60 ±0.1 ±0.5 µA

0 0.5 0.5 µA

=+25°C TA=–40°C to +85°C

T

A

Min. Max. Min. Max.

– 0.1 VCC – 0.1

CC

– 0.1 VCC – 0.1

V

CC

– 0.1 VCC – 0.1

V

CC

– 0.1 VCC – 0.1

V

CC

– 0.1 VCC – 0.1

V

CC

– 0.1 VCC – 0.1

V

CC

0.75 x V

0.70 x VCC

CC

1.07 0.99

1.24 1.22

1.95 1.87

2.61 2.55

0.1 0.1

0.30 x V

CC

0.30 x V

CC

0.31 0.37

0.31 0.35

0.31 0.33

NC7SP17 — TinyLogic

Units

V

ULP Single Buffer with Schmitt Trigger Input

V

®

AC Electrical Characteristics

Symbol Parameter Conditions VCC

0.90 27.0

1.10 ≤ VCC ≤ 1.30 3.5 11.0 21.8 3.0 34.3

1.40 ≤ VCC ≤ 1.60 2.5 7.0 14.8 2.0 15.0

1.65 ≤ VCC ≤ 1.95 2.0 6.0 12.0 1.5 12.2

2.30 ≤ VCC ≤ 2.70 1.5 5.0 9.4 1.0 9.9

3.00 ≤ VCC ≤ 3.60 1.0 4.0 8.3 1.0 9.0

0.90 30.0

1.10 ≤ VCC ≤ 1.30 4.0 11.0 22.8 3.5 37.3

1.40 ≤ VCC ≤ 1.60 3.0 8.0 15.5 2.5 16.5

1.65 ≤ VCC ≤ 1.95 2.5 6.0 12.6 2.0 13.6

2.30 ≤ VCC ≤ 2.70 2.0 5.0 9.9 1.5 10.8

3.00 ≤ VCC ≤ 3.60 1.5 4.0 8.7 1.0 9.5

0.90 32.0

1.10 ≤ VCC ≤ 1.30 5.0 13.0 25.9 4.0 46.3

1.40 ≤ VCC ≤ 1.60 4.0 9.0 17.8 3.5 18.2

1.65 ≤ VCC ≤ 1.95 3.0 7.0 14.4 2.0 15.9

2.30 ≤ VCC ≤ 2.70 2.0 6.0 11.3 1.5 12.8

3.00 ≤ VCC ≤ 3.60 1.5 5.0 9.2 1.0 10.7

0 2

0.90 to 3.60 8

t

, t

Propagation Delay

PHL

PLH

CIN Input Capacitance

Power Dissipation

CPD

Capacitance

=10pF,

C

L

=1M

R

L

CL=15pF,

=1M

R

L

CL=30pF,

=1M

R

L

=0V or VCC,

V

IN

f=10MHz

=25°C TA=-40 to 85°C

T

A

Min. Typ. Max. Min. Max.

NC7SP17 — TinyLogic

Units Figure

ULP Single Buffer with Schmitt Trigger Input

Figure

ns

5

Figure

6

pF

Figure 5. AC Test Circuit Figure 6. AC Waveforms for Inverting and

Non-Inverting Functions

Symbol VCC

3.3V ± 0.3V 2.5V ± 0.2V 1.8V ± 0.15V 1.5V ± 0.1V 1.2V ± 0.1V 0.9V

Vmi 1.5V VCC / 2 VCC / 2 VCC / 2 VCC / 2 VCC / 2

Vmo 1.5V VCC / 2 VCC / 2 VCC / 2 VCC / 2 VCC / 2

®

Physical Dimensions

NC7SP17 — TinyLogic

ULP Single Buffer with Schmitt Trigger Input

Figure 7. 5-Lead, SC70, EIAJ SC-88a, 1.25mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’ s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

.

Tape and Reel Specification

Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:

http://www.fairchildsemi.com/products/analog/pdf/sc70-5_tr.pdf

Package Designator Tape Section Cavity Number Cavity Status Cover Type Status

Leader (Start End) 125 (Typical) Empty Sealed

P5X

Carrier 3000 Filled Sealed

Trailer (Hub End) 75 (Typical) Empty Sealed

.

®

Physical Dimensions

2X

0.05

C

1.45 2X

NC7SP17 — TinyLogic

B

0.05

C

(1)

(0.254)

PIN 1 IDENTIFIER

5

0.05

DETAIL A

(0.05)

Notes:

1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD

2. DIMENSIONS ARE IN MILLIMETERS

3. DRAWING CONFORMS TO ASME Y14.5M-1994

4. FILENAME AND REVISION: MAC06AREV4

5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY OTHER LINE IN THE MARK CODE LAYOUT.

0.55MAX

C

6X

TOP VIEW

C

1.0

0.5

BOTTOM VIEW

1.00

A

0.05

0.00

0.05

0.25 6X

0.15

0.10 CBA

0.05

0.35 5X

0.25

0.40 5X

0.30

(0.13)

4X

C

5X

(0.52)

1X

PIN 1

C

0.075 X 45

CHAMFER

(0.49)

RECOMMENED LAND PATTERN

(0.30)

6X

0.10 6X

0.00

0.40

0.30

DETAIL A PIN 1 TERMINAL

(0.75)

0.45

0.35

Figure 8. 6-Lead, MicroPak™, 1.0mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’ s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

.

ULP Single Buffer with Schmitt Trigger Input

Tape and Reel Specification

Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:

http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf

Package Designator Tape Section Cavity Number Cavity Status Cover Type Status

Leader (Start End) 125 (Typical) Empty Sealed

L6X

Carrier 5000 Filled Sealed

Trailer (Hub End) 75 (Typical) Empty Sealed

.

®

Physical Dimensions

0.05 C

2X

1.00

NC7SP17 — TinyLogic

0.89

B

A

5X 0.40

0.35

PIN 1 MIN 250uM

TOP VIEW

C

SIDE VIEW

(0.08) 4X

DETAIL A

0.35

5X

0.25

NOTES:

A. COMPLIES TO JEDEC MO-252 STANDARD

B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 D. LANDPATTERN RECOMMENDATION IS BASED ON FSC

DESIGN. E. DRAWING FILENAME AND REVISION: MGF06AREV3

123

6

0.35

BOTTOM VIEW

54

0.55MAX

0.60

(0.08)

4X

0.09

0.19

1.00

2X

0.05

6X

0.10 CBA .05 C

0.05

C

1X 0.45

C

RECOMMENDED LAND PATTERN FOR SPACE CONSTRAINED PCB

5X

0.52

0.57

1X

ALTERNATIVE LAND PATTERN FOR UNIVERSAL APPLICATION

(0.05) 6X

0.075X45°

CHAMFER

DETAIL A PIN 1 LEAD SCALE: 2X

6X 0.19

0.90

0.35

0.20

6X

0.66

0.73

0.40

0.30

Figure 9. 6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’ s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

.

ULP Single Buffer with Schmitt Trigger Input

Tape and Reel Specification

Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:

http://www.fairchildsemi.com/packaging/MicroPAK2_6L_tr.pdf.

Package Designator Tape Section Cavity Number Cavity Status Cover Type Status

Leader (Start End) 125 (Typical) Empty Sealed

FHX

Carrier 5000 Filled Sealed

Trailer (Hub End) 75 (Typical) Empty Sealed

®

NC7SP17 — TinyLogic

ULP Single Buffer with Schmitt Trigger Input