Datasheet N74F8960F, N74F8961N, N74F8961F, N74F8961A, N74F8960N Datasheet (Philips)

Philips Semiconductors FAST Products Product specification

74F8960/74F8961

Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)

1

December 19, 1990 853-1120 01322

FEATURES

•Octal latched transceiver

•Drives heavily loaded backplanes with

equivalent load impedances down to 10Ω

•High drive (100mA) open collector drivers

on B port

•Reduced voltage swing (1 volt) produces

less noise and reduces power consumption

•High speed operation enhances

performance of backplane buses and
facilitates incident wave switching

•Compatible with IEEE futurebus standards

•Built-in precision band-gap reference

provides accurate receiver thresholds and
improved noise immunity

•Controlled output ramp and multiple GND

pins minimize ground bounce

•Glitch-free power up/down operation

DESCRIPTION

The 74F8960 and 74F8961 are octal
bidirectional latched transceivers and are
intended to provide the electrical interface to
a high performance wired–OR bus. The B
port inverting drivers are low–capacitance
open collector with controlled ramp and are
designed to sink 100mA from 2 volts. The B
port inverting receivers have a 100 mV
threshold region and a 4ns glitch filter.

The B port interfaces to ‘Backplane
Transceiver Logic’ (BTL). BTL features a
reduced (1V to 2V) voltage swing for lower
power consumption and a series diode on
the drivers to reduce capacitive loading.

Incident switching is employed, therefore BTL
propagation delays are short. Although the

voltage swing is much less for BTL, so is its
receiver threshold region, therefore noise
margins are excellent.

BTL offers low power consumption, low
ground bounce, EMI and crosstalk, low
capacitive loading, superior noise margin and
low propagation delays. This results in a high
bandwidth, reliable backplane.

The 74F8960 and 74F8961 A ports have TTL
3–state drivers and TTL receivers with a latch
function. A separate High–level control input
(VX) is provided to limit the A side output
level to a given voltage level (such as 3.3V).
For 5.0V systems, VX is simply tied to VCC.

The 74F8961 is the non–inverting version of
74F8960.

TYPE

TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT( TOTAL)

74F8960 6.5ns 80mA
74F8961 6.5ns 80mA

ORDERING INFORMATION

ORDER CODE

DESCRIPTION COMMERCIAL RANGE

V

CC

= 5V ±10%, T

amb

= 0°C to +70°C

28–pin plastic DIP (300 mil)

1

N74F8960N, N748961N

28–pin PLCC

1

N74F8960A, N74F8961A

NOTE: Thermal mounting techiques are recommended.

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

PINS DESCRIPTION

74F (U.L.)

HIGH/LOW

LOAD VALUE

HIGH/LOW

A0 – A8 PNP latched inputs 3.5/0.117 70µA/70µA
B0 – B8 Data inputs with threshold circuitry 5.0/0.167 100µA/100µA

OEA A output enable input (active high) 1.0/0.033 20µA/20µA

OEB0, OEB1 B output enable inputs (active low) 1.0/0.033 20µA/20µA

LE Latch enable input (active low) 1.0/0.033 20µA/20µA
A0 – A7 3–state outputs 150/40 3mA/24mA
B0 – B7 Open collector outputs OC/166.7 OC/100mA

NOTES:

1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.

2. OC = Open collector.

Philips Semiconductors FAST Products Product specification

74F8960/74F8961

Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)

December 19, 1990

2

PIN CONFIGURATION PIN CONFIGURATION PLCC LOGIC SYMBOL

1
2
3
4
5
6
7
8
9

10 19

20

21

22

23

24

25

26

27

28

OEA

A1

GND

A3

A4

V

CC

15

2
28
16

A0

V

X

OEB1
OEB

0

OEB1

OEB0
OEA
LE

3 5 6

A0 A1 A2

GND

A5

4 3 2 1 28 27

25
24
23
22
21
20

11

10

9

8

7

6

18

16 17151413

26

19

12

5

PLCC

A1
A2

A3

GND

A4

11
12
13
14 15

16

17

18

A2

GND

A5

A6

GND

A7

B0

B2

GND

GND

B5

LE

B1

B3

B4

B6

B7

GND

V

CC

OEAA0GND LE B0 B1

GND

B2
B3
GND

B5

B4

B6

GNDOEB

1OEB2 B7

V

X

A7A6

7 9 10 12 13

A6 A7A3 A4 A5

27 26 24

B0 B1 B2

23 21 20 19 17

B6 B7B3 B4 B5

V

CC

= Pin 1, V

X

= Pin 14

GND = Pin 4, 8, 11, 18, 22, 25

74F8960

74F8960 74F8960

PIN CONFIGURATION PIN CONFIGURATION PLCC LOGIC SYMBOL

15

2
28
16 OEB1

OEB0
OEA
LE

3 5 6

A0 A1 A2

7 9 10 12 13

A6 A7A3 A4 A5

27 26 24

B0 B1 B2

23 21 20 19 17

B6 B7B3 B4 B5

V

CC

= Pin 1, V

X

= Pin 14

GND = Pin 4, 8, 11, 18, 22, 25

74F8961

74F8961 74F8961

1
2
3
4
5
6
7
8
9

10 19

20

21

22

23

24

25

26

27

28

OEA

A1

GND

A3

A4

V

CC

A0

V

X

OEB1
OEB

0

11
12
13
14 15

16

17

18

A2

GND

A5

A6

GND

A7

B0

B2

GND

GND

B5

LE

B1

B3

B4

B6

B7

GND

GND

A5

4 3 2 1 28 27

25
24
23
22
21
20

11

10

9

8

7

6

18

16 17151413

26

19

12

5

PLCC

A1
A2

A3

GND

A4

V

CC

OEAA0GND LE B0 B1

GND

B2
B3
GND

B5

B4

B6

GNDOEB

1OEB2 B7

V

X

A7A6

Philips Semiconductors FAST Products Product specification

74F8960/74F8961

Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)

December 19, 1990

3

IEC/IEEE SYMBOL FOR 74F8960 IEC/IEEE SYMBOL FOR 74F8961

74F8960 74F8961

3

2

3

&

EN2

EN3

C1

1D

27

26
24
23
21
20
19
17

5
6
7
9
10
11
13

15
16
28
2

3

2

3

&

EN2

EN3

C1

1D

27

26
24
23
21
20
19
17

5
6
7
9
10
11
13

15
16
28
2

PIN DESCRIPTION

SYMBOL PINS TYPE NAME AND FUNCTION

A0 – A7 3, 5, 6, 7, 9, 10, 12, 13 I/O PNP latched input/3–state output (with VX control option)
B0 – B7 27, 26, 24, 23, 21, 20, 19, 17 I/O

Data input with special threshold circuitry to reject noise/ open collector output, high

current drive
OEB0 15 Input Enables the B outputs when both pins are low
OEB1 16 Input Enables the A outputs when high

LE 28 Input Latched when high (a special feature is buillt in for proper enabling times)
V

X

14 Input Clamping voltage keeping VOH from rising above VX (VX = Vcc for normal use)

Philips Semiconductors FAST Products Product specification

74F8960/74F8961

Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)

December 19, 1990

4

LOGIC DIAGRAM

LE

B0

OEB0

Data

Q

27

3

LE

OEA

V

CC

= Pin 1, V

X

= Pin 14,

GND = Pin 4, 8, 11, 18, 22, 25

A0

LE

B1

Data

Q

26

5

A1

LE

B2

Data

Q

24

6

A2

LE

B3

Data

Q

23

7

A3

LE

B4

Data

Q

21

9

A4

LE

B5

Data

Q

20

10

A5

LE

B6

Data

Q

19

12

A6

LE

B7

Data

Q

17

13

A7

28

2

16

15

OEB

1

LE

B0

OEB0

Data

Q

27

3

LE

OEA

A0

LE

B1

Data

Q

26

5

A1

LE

B2

Data

Q

24

6

A2

LE

B3

Data

Q

23

7

A3

LE

B4

Data

Q

21

9

A4

LE

B5

Data

Q

20

10

A5

LE

B6

Data

Q

19

12

A6

LE

B7

Data

Q

17

13

A7

28

2

16

15

OEB1

74F9861

74F9860

Philips Semiconductors FAST Products Product specification

74F8960/74F8961

Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)

December 19, 1990

5

FUNCTION TABLE FOR 74F8960

INPUTS LATCH OUTPUTS OPERATING MODE

An Bn* LE OEA OEB0OEB1STATE An Bn

H X L L L L H Z L A 3–state, data from A to B
L X L L L L L Z H**
X X H L L L Qn Z Qn A 3–state, latched data to B
– – L H L L (1) (1) (1) Feedback: A to B, B to A
– H H H L L H (2) H Z(2) Preconditioned latch enabling data transfer from B to A
– L H H L L H (2) L Z(2)
– – H H L L Qn Qn Qn Latch state to A and B
H X L L H X H Z Z

l X L L H X l Z Z B and A 3–state
X X H L H X Qn Z Z
– H L H H X H H Z
– L L H H H L L Z B 3–state, data from B to A
– H H H H H Qn H Z
– L H H H H Qn L Z
H X L L X H H Z Z

l X L L X H l Z Z B and A 3–state
X X H L X H Qn Z Z
– H L H X H H H Z
– L L H X H L L Z B 3–state, data from B to A
– H H H X H Qn H Z
– L H H X H Qn L Z

NOTES:

1. H = High–voltage level

2. L = Low–voltage level

3. X = Don’t care

4. – = Input not externally driven

5. Z = High impedance (off) state

6. Q

n

= High or low voltage level one setup time prior to the low–to–high LE transition.

7. (1) = Condition will cause a feedback loop path: A to B and B to A.

8. (2) = The latch must be preconmditioned such that B inputs may assume a high or low level while OEB

0 and OEB1 are low and LE is high.

9. H**= Goes to level of pullup voltage.

10.B* = Precaution should be taken to insure the B inputs do not float. If they do they are equal to low state.

Philips Semiconductors FAST Products Product specification

74F8960/74F8961

Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)

December 19, 1990

6

FUNCTION TABLE FOR 74F8961

INPUTS LATCH OUTPUTS OPERATING MODE

An Bn* LE OEA OEB0OEB1STATE An Bn

H X L L L L H Z H** A 3–state, data from A to B
L X L L L L L Z L
X X H L L L Qn Z Qn A 3–state, latched data to B
– – L H L L (1) (1) (1) Feedback: A to B, B to A
– H H H L L H (2) H Z(2) Preconditioned latch enabling data transfer from B to A
– L H H L L H (2) L Z(2)
– – H H L L Qn Qn Qn Latch state to A and B
H X L L H X H Z Z

l X L L H X l Z Z B and A 3–state
X X H L H X Qn Z Z
– H L H H X H H Z
– L L H H H L L Z B 3–state, data from B to A
– H H H H H Qn H Z
– L H H H H Qn L Z
H X L L X H H Z Z

l X L L X H l Z Z B and A 3–state
X X H L X H Qn Z Z
– H L H X H H H Z
– L L H X H L L Z B 3–state, data from B to A
– H H H X H Qn H Z
– L H H X H Qn L Z

NOTES:

1. H = High–voltage level

2. L = Low–voltage level

3. X = Don’t care

4. – = Input not externally driven

5. Z = High impedance (off) state

6. Q

n

= High or low–voltage level one setup time prior to the low–to–high LE transition.

7. (1) = Condition will cause a feedback loop path: A to B and B to A.

8. (2) = The latch must be preconmditioned such that B inputs may assume a high or low level while OEB

0 and OEB1 are low and LE is high.

9. H**= Goes to level of pullup voltage.

10.B* = Precaution should be taken to insure the B inputs do not float. If they do they are equal to low state.

Philips Semiconductors FAST Products Product specification

74F8960/74F8961

Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)

December 19, 1990

7

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)

SYMBOL

PARAMETER RATING UNIT

V

CC

Supply voltage

–0.5 to +7.0 V

V

X

Threshold control

–0.5 to +7.0 V

V

IN

Input voltage OEB, OEA, LE –0.5 to +7.0 V

A0 – A7, B0 – B7 –0.5 to +5.5 V

I

IN

Input current

–40 to +5 mA

V

OUT

Voltage applied to output in high output state

–0.5 to V

CC

V

I

OUT

Current applied to output in low output state

A0 – A7 48 mA

B0 – B7 200 mA

T

amb

Operating free air temperature range

0 to +70

°C

Tstg Storage temperature range –65 to +150

°C

RECOMMENDED OPERATING CONDITIONS

LIMITS

SYMBOL

PARAMETER

MIN NOM MAX UNIT

V

CC

Supply voltage

4.5 5.0 5.5 V

V

IH

High–level input voltage

Except B0 – B7 2.0 V

B0 – B7 1.6 V

V

IL

Low–level input voltage

Except B0 – B7 0.8 V

B0 – B7 1.475 V

I

Ik

Input clamp current

Except A0 – A7 –18 mA

A0 – A7 –40 mA

I

OH

High–level output current

A0 – A7 –3 mA

I

OL

Low–level output current

A0 – A7 24 mA
B0 – B7 100 mA

T

amb

Operating free air temperature

0 +70

°C

Philips Semiconductors FAST Products Product specification

74F8960/74F8961

Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)

December 19, 1990

8

DC ELECTRICAL CHARACTERISTICS

(Over recommended operating free-air temperature range unless otherwise noted.)

SYMBOL

PARAMETER TEST LIMITS UNIT

CONDITIONS

1

MIN.

TYP.

2

MAX.

I

OH

High–level output current B0 – B7 VCC = MAX, VIL = MAX, VIH = MIN, VOH = 2.1V 100 µA

I

OFF

Power–off output current B0 – B7 VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 2.1V 100 µA

VCC = MIN, I

OH

= –3mA, VX =V

CC

2.5 V

CC

V

V

OH

High-level output voltage A0 – A7

4

VIL = MAX, VIH = MIN

I

OH

= –4mA,

V

X

=3.13V and 3.47V

2.5 V

A0 – A7

4

VCC = MIN, I

OL

= 20mA, VX = V

CC

0.50 V

V

OL

Low-level output voltage B0 – B78 VIL = MAX I

OL

= 100mA 1.15 V

VIH = MIN I

OL

= 4mA 0.40 V

V

IK

Input clamp voltage A0 – A7 VCC = MIN, II = I

IK

-0.5 V

Except A0 – A7 VCC = MIN, II = I

IK

-1.2 V

I

I

Input current at OEBn, OEA, LE VCC = MAX, VI = 7.0V 100

µA

maximum input voltage A0–A7, B0 – B7 VCC = MAX, VI = 5.5V 1 mA

I

IH

High–level input current OEBn, OEA, LE VCC = MAX, VI = 2.7V 20

µA

B0–B7 VCC = MAX, VI = 2.1V, Bn – An = 0V 100

µA

I

IL

Low–level input current OEBn, OEA, LE VCC = MAX, VI = 0.5V –20

µA

B0 – B7 VCC = MAX, VI = 0.3V –100

µA

I

OZH

+ I

IH

Off–state output current,
high–level current applied

A0 – A7

VCC = MAX, V

O

= 2.7V 70

µA

I

OZL

+ I

IL

Off–state output current,
low–level voltage applied

A0 – A7 VCC = MAX, VI = 0.5V –70

µA

I

X

High–level control current

VCC = MAX, V

X

= VCC, LE = OEA = OEBn =

2.7V, A0 – A7 = 2.7V, B0 – B7 = 2.0V,

–100 100

µA

VCC = MAX, V

X

= 3.13 & 3.47V, LE = OEA =

OEB

n = A0 – A7 = 2.7V, B0 – B7 = 2.0V,

–10 10

µA

I

OS

Short circuit output

A0–A7

74F8960

VCC = MAX, Bn = 1.3V, OEA = 2.0V, OEBn =

2.7V

-60 -150 mA

current

3

only

74F8961

VCC = MAX, Bn = 1.8V, OEA = 2.0V, OEBn =

2.7V

I

CCH

VCC = MAX 65 100 mA

I

CC

Supply current (total) I

CCL

VCC = MAX, VIL = 0.5V 100 145 mA

I

CCZ

75 100 mA

NOTES:

1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type
and function table for operating mode.

2. All typical values are at V

CC

= 5V, T

amb

= 25°C.

3. Not more than one output should be shorted at a time. For testing I

OS

, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I

OS

tests should be performed last.

4. Due to test equipment limitations, actual test conditions are for V

IH

=1.8v and VIL = 1.3V.

Philips Semiconductors FAST Products Product specification

74F8960/74F8961

Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)

December 19, 1990

9

AC ELECTRICAL CHARACTERISTICS FOR 74F8960

A PORT LIMITS

T

amb

= +25°C T

amb

= 0°C to +70°C

SYMBOL PARAMETER TEST VCC = +5.0V

VCC = +5.0V ± 10%

UNIT

CONDITION

CL = 50pF, RL = 500Ω CL = 50p, RL = 500Ω

MIN TYP MAX MIN MAX

t

PLH

t

PHL

Propagation delay
Bn

to An

Waveform 1, 2

4.5

6.0

6.0

10.0

8.5

13.5

3.5

7.5

9.5

14.5

ns

t

PZH

t

PZL

Output enable time to high or low, OEA
to An

Waveform 4
Waveform 5

8.0

8.5

10.5

11.0

13.5

13.5

7.5

8.5

15.0

16.0

ns

t

PHZ

t

PLZ

Output enable time from high or low,
OEA

to An

Waveform 4
Waveform 5

2.0

2.0

3.5

4.5

6.5

7.0

2.0

2.0

7.0

7.5

ns

B PORT LIMITS

T

amb

= +25°C T

amb

= 0°C to +70°C

SYMBOL PARAMETER TEST VCC = +5.0V

VCC = +5.0V ± 10%

UNIT

CONDITION

CD = 50pF, RU = 9Ω C

D

= 50pF, RL = 9Ω

MIN TYP MAX MIN MAX

t

PLH

t

PHL

Propagation delay
An to Bn

Waveform 1, 2

3.5

3.5

5.5

5.0

8.0

8.0

2.0

3.0

9.5

9.0

ns

t

PLH

t

PHL

Propagation delay
LE

to Bn

Waveform 1, 2

3.5

4.0

5.5

6.5

8.5

9.0

2.5

3.0

9.5

10.5

ns

t

PLH

t

PHL

Output enable/disable time
OEB

n to Bn

Waveform 1, 2

2.5

3.5

4.5

5.5

7.5

8.5

1.5

3.5

8.0

9.0

ns

t

TLH

t

THL

Transition time, Bn port

1.3V to 1.7V, 1.7V to 1.3V

Test circuit and

waveforms

0.5

0.5

2.0

2.0

4.5

4.5

0.5

0.5

5.0

6.0

ns

AC SETUP REQUIREMENTS FOR 74F8960

LIMITS

T

amb

= +25°C T

amb

= 0°C to +70°C

SYMBOL PARAMETER TEST VCC = +5.0V

VCC = +5.0V ± 10%

UNIT

CONDITION

CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω

MIN TYP MAX MIN MAX

tsu(H)
t

su

(L)

Setup time, high or low
An

to LE

Waveform 3

5.0

3.0

5.0

5.0

ns

t

h

(H)

t

h

(L)

Hold time, high or low
An

to LE

Waveform 3

0.0

0.0

0.0

0.0

ns

tw(L) LE pulse width, low Waveform 3 4.5 5.0 ns

Philips Semiconductors FAST Products Product specification

74F8960/74F8961

Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)

December 19, 1990

10

AC ELECTRICAL CHARACTERISTICS FOR 74F8961

A PORT LIMITS

T

amb

= +25°C T

amb

= 0°C to +70°C

SYMBOL PARAMETER TEST VCC = +5.0V

VCC = +5.0V ± 10%

UNIT

CONDITION

CL = 50pF, RL = 500Ω CL = 50p, RL = 500Ω

MIN TYP MAX MIN MAX

t

PLH

t

PHL

Propagation delay
Bn

to An

Waveform 1, 2

5.5

4.5

8.0

6.0

12.0

9.0

5.5

4.5

12.0

9.0

ns

t

PZH

t

PZL

Output enable time to high or low, OEA
to An

Waveform 4
Waveform 5

8.0

8.5

10.5

11.0

13.5

13.5

7.5

8.0

15.0

15.5

ns

t

PHZ

t

PLZ

Output enable time from high or low,
OEA

to An

Waveform 4
Waveform 5

2.0

2.0

3.5

4.5

6.0

7.0

1.5

2.0

6.5

7.5

ns

B PORT LIMITS

T

amb

= +25°C T

amb

= 0°C to +70°C

SYMBOL PARAMETER TEST VCC = +5.0V

VCC = +5.0V ± 10%

UNIT

CONDITION

CD = 50pF, RU = 9Ω C

D

= 50pF, RU = 9Ω

MIN TYP MAX MIN MAX

t

PLH

t

PHL

Propagation delay
An to Bn

Waveform 1, 2

3.0

3.0

5.0

4.5

7.0

7.5

2.5

2.5

8.0

8.5

ns

t

PLH

t

PHL

Propagation delay
LE

to Bn

Waveform 1, 2

3.5

3.5

5.0

5.0

8.0

8.0

3.0

2.5

9.0

9.0

ns

t

PLH

t

PHL

Output enable/disable time
OEB

n to Bn

Waveform 1, 2

3.0

3.5

4.5

5.5

7.0

9.0

2.5

3.5

8.0

10.0

ns

t

TLH

t

THL

Transition time, Bn port

1.3V to 1.7V, 1.7V to 1.3V

Test circuit and

waveforms

0.5

0.5

2.0

2.0

4.5

4.5

0.5

0.5

5.0

4.5

ns

AC SETUP REQUIREMENTS FOR 74F8961

LIMITS

T

amb

= +25°C T

amb

= 0°C to +70°C

SYMBOL PARAMETER TEST VCC = +5.0V

VCC = +5.0V ± 10%

UNIT

CONDITION

CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω

MIN TYP MAX MIN MAX

tsu(H)
t

su

(L)

Setup time, high or low
An

to LE

Waveform 3

3.5

4.5

4.5

5.0

ns

t

h

(H)

t

h

(L)

Hold time, high or low
An

to LE

Waveform 3

0.0

0.0

0.0

0.0

ns

tw(L) LE pulse width, low Waveform 3 4.0 5.0 ns

Philips Semiconductors FAST Products Product specification

74F8960/74F8961

Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)

December 19, 1990

11

AC WAVEFORMS

V

M

V

M

V

M

V

M

Waveform 1. Propagation delay for data to output

Waveform 3. Data setup and hold times and LE

pulse width

Waveform 4. 3–state output enable time to high level

and output disable time from high level

Waveform 5. 3-state output enable time to low level

and output disable time from low level

LE

V

M

V

M

VMV

M

V

M

V

M

ts(L) ts(H)

th(L) th(H)

V

M

V

M

V

M

t

PHZ

t

PZH

VOH -0.3V

0V

V

M

V

M

V

M

t

PLZ

t

PZL

VOL +0.3V

OEA

An

OEA

An

An

An, Bn

An, Bn, OEB

n

t

PLH

t

PHL

V

M

tw(L)

V

M

V

M

V

M

V

M

Waveform 2. Propagation delay for data to output

An, Bn

An, Bn, OEB

n

t

PHL

t

PLH

NOTES:

1. For all waveforms, V

M

= 1.5V.

2. The shaded areas indicate when the input is permitted to change for predictable output performance.

TEST CIRCUITS AND WAVEFORMS

C

D

t

w

90%

V

M

10%

90%

V

M

10%

90%

V

M

10%

90%

V

M

10%

NEGATIVE
PULSE

POSITIVE
PULSE

t

w

AMP (V)

Low V

Low V

t

THL (tf

)

INPUT PULSE REQUIREMENTS

rep. rate

t

w

t

TLHtTHL

Input pulse definition

V

CC

family

74F

D.U.T.

PULSE

GENERATOR

R

L

C

L

R

T

V

IN

V

OUT

Test circuit for 3–state outputs on A port

DEFINITIONS:

R

L

= Load resistor; see AC electrical characteristics for value.
CL= Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value.
RU= Pull up resistor; see AC electrical characteristics for value.
C

D

= Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value.
RT= Termination resistance should be equal to Z

OUT

of pulse generators.

t

THL (tf

)

t

TLH (tr

)

t

TLH (tr

)

AMP (V)

amplitude

V

M

R

L

7.0V

V

CC

D.U.T.

PULSE

GENERATOR

R

T

V

IN

V

OUT

Test circuit for outputs on B port

R

U

7.0V

Low V

SWITCH POSITION

TEST SWITCH

closed

openAll other

t

PLZ

, t

PZL

A port 3.0V 0.0V 1.5V 1MHz 500ns 2.5ns 2.5ns
B port 3.0V 1.0V 1.5V 1MHz 500ns 4.0ns 4.0ns