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INTEGRATED CIRCUITS
74F786
4-bit asynchronous bus arbiter
Product specification
IC15 Data Handbook
1991 Feb 14
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Philips Semiconductors Product specification
74F7864-bit asynchronous bus arbiter
FEA TURES
•Arbitrates between 4 asynchronous inputs
•Separate grant output for each input
•Common output enable
•On board 4 input AND gate
•Metastable–free outputs
•Industrial temperature range available (–40°C to +85°C)
The 74F786 is designed so that contention between two or more
request signals will not glitch or display a metastable condition. In
this situation an increase in the BR
n to BGn t
may be observed.
PHL
A typical 74F786 has an h = 6.6ns, t = 0.41ns and To = 5µsec.
Where:
h = Typical propagation delay through the device and t and To are
device parameters derived from test results and can most nearly be
defined as:
t = A function of the rate at which a latch in a metastable state
resolves that condition.
DESCRIPTION
The 74F786 is an asynchronous 4–bit arbiter designed for high
speed real–time applications. The priority of arbitration is determined
on a first–come first–served basis. Separate bus grant (BGn)
outputs are available to indicate which one of the request inputs is
served by the arbitration logic. All BG
common enable (EN
) pin. In order to generate a bus request signal
a separate 4 input AND gate is provided which may also be used as
an independent AND gate. Unused bus request (BR
disabled by tying them high.
n outputs are enabled by a
) inputs may be
To = A function of the measurement of the propensity of a latch to
enter a metastable state. To is also a very strong function of the
normal propagation delay of the device.
For further information, please refer to the 74F786 application notes.
TYPE
TYPICAL
PROPAGATION DELAY
TYPICAL
SUPPLY CURRENT
74F786 6.6ns 55mA
ORDERING INFORMATION
ORDER CODE
COMMERCIAL RANGE INDUSTRIAL RANGE
DESCRIPTION VCC = 5V ±10%, VCC = 5V ±10%, PKG DWG #
T
= 0°C to +70°C T
amb
16–pin plastic DIP N74F786N I74F786N SOT 38-4
16–pin plastic SO N74F786D I74F786D SOT109-1
= –40°C to +85°C
amb
(TOTAL)
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
BR0 – BR3
A, B, C, D
EN
YOUT
BG0 – BG3
Bus request inputs (active low)
AND gate inputs
Common bus grant output enable input (active low)
AND gate output
Bus grant outputs (active low)
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
LOGIC SYMBOL
456715123
BR0 BR1 BR2 BR3 A B C D
EN
6
BG0 BG1 BG2 BG3 YOUT
13 12 11 10 14
V
= Pin 16
CC
GND = Pin 8
SF00442
DESCRIPTION
IEC/IEEE SYMBOL
74F (U.L.) HIGH/
1.0/3.0
1.0/1.0
1.0/1.0
150/40
150/40
9
4
5
6
7
15
1
2
3
EN
BR0
BR1
BR2
BR3
LOW
BUS ARBITER
Φ
74F786
&
LOAD VALUE HIGH/
20µA/1.8mA
20µA/0.6mA
20µA/0.6mA
3.0mA/24mA
3.0mA/24mA
BG0
BG1
BG2
BG3
13
12
11
10
14
SF00443
LOW
February 14, 1991 853–1269 01717
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Philips Semiconductors Product specification
74F7864-bit asynchronous bus arbiter
FUNCTIONAL DESCRIPTION
PIN CONFIGURATION
The BRn inputs have no inherent priority. The arbiter assigns priority
to the incoming requests as they are received, therefore, the first BR
asserted will have the highest priority. When a bus request is
received its corresponding bus grant becomes active, provided that
EN
is low. If additional bus requests are made during this time they
are queued. When the first request is removed, the arbiter services
the bus request with the next highest priority. Removing a request
while a previous request is being serviced can cause a grant to be
changed when arbitrating between three or four requests. For that
reason, the user should not remove ungranted requests when
arbitrating between three or four requests. This does not apply to
arbitration between two requests.
If two or more BR
one of them will be selected at random, and all BG
n inputs are asserted at precisely the same time,
n outputs will be
BR
BR
BR
BR3
GND
1
B
2
C
3
D
4
0
5
1
6
2
held in the high state until the selection is made. This guarantees
that an erroneous BG
n will not be generated even though a
metastable condition may occur internal to the device. When the EN
is in the high state the BGn outputs are forced high.
PIN DESCRIPTION
SYMBOL PINS TYPE NAME FUNCTION
BR0 – BR3 4, 5, 6, 7 Input Bus request inputs (active low)
A, B, C, D 15, 1, 2, 3 Input Inputs of the 4–input AND gate
EN 9 Input Enable input When low it enables the BG0 – BG3 outputs.
BG0 – BG3 13, 12, 11, 10 Output Bus grant outputs (active low)
YOUT 14 Output Output of the 4–input AND gate
GND 8 Ground ground (0V)
V
CC
16 Power Positive supply voltages
The logic of this device arbitrates between these four inputs.
Unused inputs should be tied high.
These outputs indicate the selected bus request. BG0 corresponds to BR0, BG1 to BR1, etc.
16
V
CC
15
A
14
YOUT
13
BG
12
BG1
11
BG
107
BG
98
EN
SF00441
0
2
3
February 14, 1991
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Philips Semiconductors Product specification
74F7864-bit asynchronous bus arbiter
ARBITER FUNCTION TABLE
INPUTS OUTPUTS
EN BR0 BR1 BR2 BR3 BG0 BG1 BG2 BG3
L 1 X X X L H H H
L X 1 X X H L H H
L X X 1 X H H L H
L X X X 1 H H H L
H X X X X H H H H
Notes to mode selection function table
H = High–voltage level
L = Low–voltage level
X = Don’t care
1 = First of inputs to go low
ARBITER FUNCTION TABLE
INPUTS OUTPUT
A B C D YOUT
L L L L L
L L L H L
L L H L L
L L H H L
L H L L L
L H L H L
L H H L L
L H H H L
H L L L L
H L L H L
H L H L L
H L H H L
H H L L L
H H L H L
H H H L L
H H H H H
Notes to AND function table
H = High–voltage level
L = Low–voltage level
February 14, 1991
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Philips Semiconductors Product specification
74F7864-bit asynchronous bus arbiter
LOGIC DIAGRAM
15
A
BR0
BR
BR
BR
1
B
2
C
3
D
4
5
1
6
2
7
3
14
YOUT
13
BG0
12
1
BG
11
BG2
10
BG
3
V
= Pin 16
CC
GND = Pin 8
EN
SF00444
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage –0.5 to +7.0 V
Input voltage –0.5 to +7.0 V
Input current –30 to +5 mA
Voltage applied to output in high output state –0.5 to V
Current applied to output in low output state 48 mA
Operating free air temperature range Commercial range 0 to +70
Storage temperature range –65 to +150
PARAMETER RATING UNIT
CC
Industrial range –40 to +85
V
°C
°C
°C
February 14, 1991
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Philips Semiconductors Product specification
74F7864-bit asynchronous bus arbiter
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER LIMITS T
UNIT MIN NOM MAX
V
V
V
I
I
I
T
CC
IN
IL
Ik
OH
OL
amb
Supply voltage 4.5 5.0 5.5 V
High–level input voltage 2.0 V
Low–level input voltage 0.8 V
Input clamp current –18 mA
High–level output current –1 mA
Low–level output current 24 mA
Operating free air temperature range Commercial range 0 +70
Industrial range –40 +85
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
V
OH
V
OL
V
IK
I
I
I
IH
I
IL
I
OS
I
CC
High–level output voltage VCC = MIN, VIL =
Low–level output voltage
Input clamp voltage VCC = MIN, II = I
Input current at maximum input voltage VCC = 0.0V, VI = 7.0V 100 µA
High–level input current VCC = MAX, VI = 2.7V 20 µA
Low–level input current A – D, EN VCC = MAX, VI = 0.5V -0.6 mA
Short–circuit output current
Supply current (total) VCC = MAX 55 80 mA
Notes to DC electrical characteristics
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
3. Not more than one output should be shorted at a time. For testing I
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
PARAMETER TEST LIMITS UNIT
MAX,
VIH = MIN
VCC = MIN, VIL =
MAX,
VIH = MIN
CONDITIONS
IK
I
OH
I
OL
1
= MAX
= MAX
±10%V
±5%V
±10%V
±5%V
MIN TYP2MAX
2.4 V
CC
2.7 3.3 V
CC
CC
CC
0.30 0.50 V
0.30 0.50 V
-0.73 -1.2 V
BRn -1.8 mA
3
= 5V, T
CC
= 25°C.
amb
tests should be performed last.
OS
VCC = MAX -60 -150 mA
, the use of high-speed test apparatus and/or sample-and-hold
OS
=
A
–40 to
°C
+85
°C
°C
February 14, 1991
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Philips Semiconductors Product specification
74F7864-bit asynchronous bus arbiter
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
SYMBOL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
PARAMETER TEST VCC = +5.0V
CONDITION CL = 50pF,
MIN TYP MAX MIN MAX MIN MAX
Propagation delay,
A, B, C, D to YOUT
Propagation delay,
BRn to BGn
Propagation delay,
EN
to BGn
Propagation delay,
BRa to BGb
Waveform 1
Waveform 2
Waveform 2
Waveform 2 5.0 7.0 10.0 4.5 10.5 4.5 10.5 ns
2.5
2.5
5.0
4.5
3.0
2.5
= +25°C T
amb
= 500Ω
R
L
4.5
7.5
4.5
7.5
7.0
10.0
6.5
9.5
5.0
8.0
4.5
7.5
= 0°C to +70°C T
amb
= –40°C to
amb
+85°C
VCC = +5.0V ± 10% VCC = +5.0V ± 10%
CL = 50pF,
= 500Ω
R
L
2.0
2.5
4.5
4.0
2.5
2.5
8.5
7.5
10.5
10.0
8.5
8.0
CL = 50pF,
= 500Ω
R
L
2.0
2.5
4.5
4.0
2.5
2.5
8.5
7.5
10.5
10.0
8.5
8.0
UNIT
ns
ns
ns
AC WAVEFORMS
V
A, B, C, D
YOUT
M
t
PLH
Waveform 1. Propagation delay for AND gate to output
BRn, EN
BGn
V
M
t
PHL
Waveform 2. Propagation delay for bus request or enable to
bus grant output
V
M
t
PHL
t
PLH
V
M
SF00445
V
M
SF00446
V
M
V
M
V
M
V
BRa
BG
BR
BG
a
b
b
M
V
M
t
PHL
V
M
SF00447
Waveform 3. Propagation delay for bus request to bus grant
output
Notes to AC waveforms
1. For all waveforms, V
2. a and b represents any of the bus requests or grants. BG
low–to–high transition and the BG
= 1.5V.
M
b high–to–low transition occur
a
simultaneously .
February 14, 1991
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Philips Semiconductors Product specification
74F7864-bit asynchronous bus arbiter
TEST CIRCUIT AND WAVEFORMS
V
CC
PULSE
GENERATOR
V
IN
R
T
D.U.T.
V
OUT
R
C
L
L
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
= Load resistor;
R
L
see AC ELECTRICAL CHARACTERISTICS for value.
C
= Load capacitance includes jig and probe capacitance;
L
see AC ELECTRICAL CHARACTERISTICS for value.
R
= Termination resistance should be equal to Z
T
pulse generators.
OUT
of
NEGATIVE
PULSE
POSITIVE
PULSE
family
74F
90%
10%
amplitude
t
w
V
M
10%
)
V
90%
M
t
THL (tf
t
TLH (tr
)
t
TLH (tr
t
THL (tf
t
w
Input Pulse Definition
INPUT PULSE REQUIREMENTS
V
rep. rate
M
3.0V 1.5V
1MHz 500ns
10%
)
)
90%
t
w
V
M
V
M
90%
10%
t
TLHtTHL
2.5ns 2.5ns
AMP (V)
0V
AMP (V)
0V
SF00006
February 14, 1991
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Philips Semiconductors Product specification
74F7864-bit asynchronous bus arbiter
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
1991 Feb 14
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Philips Semiconductors Product specification
74F7864-bit asynchronous bus arbiter
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
1991 Feb 14
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Philips Semiconductors Product specification
74F7864-bit asynchronous bus arbiter
NOTES
1991 Feb 14
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Philips Semiconductors Product specification
74F7864-bit asynchronous bus arbiter
Data sheet status
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1]
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 10-98
Document order number: 9397-750-05181
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