Datasheet N74F776A, N74F776N, N74F776F Datasheet (Philips)

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74F776
Pi-bus transceiver
Product specification IC15 Data Handbook
1990 Dec 19
INTEGRATED CIRCUITS
Page 2
74F776Pi–bus transceiver
2
December 19, 1990 853 1121 01321
FEA TURES
Octal latched transceiver
Drives heavily loaded backplanes with equivalent load impedances
down to 10 ohms
High drive (100mA) open collector drivers on B port
Reduced voltage swing (1 volt) produces less noise and reduces
power consumption
High speed operation enhances performance of backplane buses and facilitates incident wave switching
Compatible with Pi–bus and IEEE 896 Futurebus standards
Built–in precision band–gap reference provides accurate receiver
thresholds and improved noise immunity
Controlled output ramp and multiple GND pins minimize ground bounce
Glitch–free power up/power down operation
Multiple package options
Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F776 is an octal bidirectional latched transceiver and is intended to provide the electrical interface to a high performance wired–OR bus. The B port inverting drivers are low–capacitance open collector with controlled ramp and are designed to sink 100mA from 2 volts. The B port inverting receivers have a 100 mV threshold region and a 4ns glitch filter.
The 74F776 B port interfaces to ’Backplane Transceiver Logic’ (BTL). BTL features a reduced (1V to 2V) voltage swing for lower power
consumption and a series diode on the drivers to reduce capacitive loading. Incident wave switching is employed, therefore BTL propagation delays are short. Although the voltage swing is less for BTL, so is its receiver threshold, therefore noise margins are excellent.
BTL offers low power consumption, low ground bounce, EMI and crosstalk, low capacitive loading, superior noise margin and low propagation delays. This results in a high bandwidth, reliable backplane.
The 74F776 A port has TTL 3–state drivers and TTL receivers with a latch function. A separate high–level control voltage input (V
X
) is provided to limit the A side output level to a given voltage level (such as 3.3V). For 5.0V systems, V
X
is simply tied to VCC.
The 74F776 has a designed feature to control the B output transitions during power sequencing. There are two possible sequencing, They are as follows:
1.When LE
= low and OEBn = low then the B outputs are disabled until
the LE
circuitry takes control. Then the B outputs will follow the A inputs,
making a maximum of one transition during power–up (or down).
2. If LE = high or OEBn = high then the B outputs will be disabled during power–up (or down).
TYPE
TYPICAL PROPAGA-
TION DELAY
TYPICAL SUPPL Y
CURRENT( TOTAL)
74F776 6.5ns 80mA
ORDERING INFORMATION
ORDER CODE
COMMERCIAL RANGE INDUSTRIAL RANGE
DESCRIPTION
VCC = 5V ±10%, T
amb
= 0°C to +70°C VCC = 5V ±10%, T
amb
= –40°C to +85°C
PKG DWG #
28–pin plastic DIP (600 mil) N74F776N I74F776N SOT117-2
28–pin PLCC N74F776A I74F776A SOT261-2
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
A0 – A7 PNP latched inputs 3.5/0.1 17 70µA/70µA B0 – B7 Data inputs with threshold circuitry 5.0/0.167 100µA/100µA
OEA A output enable input (active high) 1.0/0.033 20µA/20µA
OEB0, OEB1 B output enable inputs (active low) 1.0/0.033 20µA/20µA
LE Latch enable input (active low) 1.0/0.033 20µA/20µA A0 – A7 3–state outputs 150/40 3mA/24mA B0 – B7 Open collector outputs OC/166.7 OC/100mA
Notes to input and output loading and fan out table
One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state. OC = Open collector.
Page 3
Philips Semiconductors Product specification
74F776Pi–bus transceiver
December 19, 1990
3
PIN CONFIGURATION
1 2 3 4 5 6 7 8 9
10 19
20
21
22
23
24
25
26
27
28
V
CC
11 12 13 14 15
16
17
18
LE B0 B1 GND B2 B3 GND B4 B5 B6 GND B7 OEB
1
OEB
0
OEA
A0
GND
A1 A2 A3
GND
A4 A5
GND
A6 A7 VX
SF00422
PIN CONFIGURA TION PLCC
4 3 2 1 28 27
25 24 23 22 21 20
11
10
9
8
7
6
18
16 17151413
26
19
12
5
PLCC
A1 A2 A3
GND
A4 A5
GND
V
CC
OEAA0GND LE B0 B1
GNDOEB0
B7
V
X
A7A6 OEB1
GND B2 B3 GND B4 B5 B6
SF00423
IEC/IEEE SYMBOL
2
3
&
EN2
EN1 EN3
ID
27
26 24 23 21 20 19 17
5 6 7 9 10 12 13
3
15 16 28 2
SF00424
LOGIC SYMBOL
VCC = Pin 1, V
X
= Pin 14
GND = Pin 4, 8, 11, 18, 22, 25
15
2 28 16
OEB0 OEA LE OEB1
B0 B1 B2 B3 B4 B5 B6 B7
27 26 24 23 21 20 19 17
35679101213
A0 A1 A2 A3 A4 A5 A6 A7
SF00425
PIN DESCRIPTION
SYMBOL PINS TYPE NAME AND FUNCTION
A0 – A7 3, 5, 6, 7, 9, 10, 12, 13 I/O PNP latched input/3–state output (with VX control option) B0 – B7 27, 26, 24, 23, 21, 20, 19, 17 I/O
Data input with special threshold circuitry to reject noise/ open collector output, high
current drive OEB0 15 Input Enables the B outputs when both pins are low OEB1 16 Input
OEA 2 Input Enables the A outputs when high
LE 28 Input Latched when high (a special feature is built in for proper enabling times) V
X
14 Input Clamping voltage keeping VOH from rising above VX (VX = Vcc for normal use)
Page 4
Philips Semiconductors Product specification
74F776Pi–bus transceiver
December 19, 1990
4
LOGIC DIAGRAM
LE
B0
OEB0
Data
Q
27
3
LE
OEA
V
CC
= Pin 1, V
X
= Pin 14,
GND = Pin 4, 8, 11, 18, 22, 25
A0
LE
B1
Data
Q
26
5
A1
LE
B2
Data
Q
24
6
A2
LE
B3
Data
Q
23
7
A3
LE
B4
Data
Q
21
9
A4
LE
B5
Data
Q
20
10
A5
LE
B6
Data
Q
19
12
A6
LE
B7
Data
Q
17
13
A7
28
2
16
15
OEB
1
SF00426
Page 5
Philips Semiconductors Product specification
74F776Pi–bus transceiver
December 19, 1990
5
FUNCTION TABLE
INPUTS LATCH OUTPUTS OPERATING MODE
An Bn* LE OEA OEB0 OEB1 STATE An Bn
H X L L L L H Z Z A 3–state, data from A to B L X L L L L L Z L X X H L L L Qn Z Qn A 3–state, latched data to B – L H L L (1) (1) (1) Feedback: A to B, B to A – H H H L L H (2) H Z(2) Preconditioned latch enabling data transfer from B to A – L H H L L H (2) L Z(2) – H H L L Qn Qn Qn Latch state to A and B H X L L H X H Z Z L X L L H X L Z Z B and A 3–state X X H L H X Qn Z Z – H L H H X H H Z – L L H H X L L Z B 3–state, data from B to A – H H H H X Qn H Z – L H H H X Qn L Z H X L L X H H Z Z L X L L X H L Z Z B and A 3–state X X H L X H Qn Z Z – H L H X H H H Z – L L H X H L L Z B 3–state, data from B to A – H H H X H Qn H Z – L H H X H Qn L Z
Notes to function table
H = High voltage level L = Low voltage level X = Don’t care – = Input not externally driven Z = High impedance ”off” state Q
n
= High or Low voltage level one setup time prior to the low–to–high LE transition. (1) = Condition will cause a feedback loop path: A to B and B to A. (2) = The latch must be preconditioned such that B inputs may assume a high or low level while OEB
0 and OEB1 are low and LE is high.
B* = Precaution should be taken to insure the B inputs do not float. If they do they are equal to low state.
Page 6
Philips Semiconductors Product specification
74F776Pi–bus transceiver
December 19, 1990
6
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.)
SYMBOL
PARAMETER RATING UNIT
V
CC
Supply voltage –0.5 to +7.0 V
V
X
Threshold control –0.5 to +7.0 V
V
IN
Input voltage OEBn, OEA, LE –0.5 to +7.0 V
A0 – A7, B0 – B7 –0.5 to +5.5 V
I
IN
Input current –40 to +5 mA
V
OUT
Voltage applied to output in high output state –0.5 to V
CC
V
I
OUT
Current applied to output in low output state A0 – A7 48 mA
B0 – B7 200 mA
T
amb
Operating free air temperature range Commercial range 0 to +70
°C
Industrial range –40 to +85
°C
T
stg
Storage temperature range –65 to +150
°C
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER LIMITS UNIT
MIN NOM MAX
V
CC
Supply voltage 4.5 5.0 5.5 V
V
IH
High–level input voltage Except B0 – B7 2.0 V
B0 – B7 1.6 V
V
IL
Low–level input voltage Except B0 – B7 0.8 V
B0 – B7 1.45 V
I
Ik
Input clamp current Except A0 – A7 –18 mA
A0 – A7 –40 mA
I
OH
High–level output current A0 – A7 –3 mA
I
OL
Low–level output current A0 – A7 24 mA
B0 – B7 100 mA
T
amb
Operating free air temperature range
Commercial range 0 +70
°C
range
Industrial range –40 +85
°C
Page 7
Philips Semiconductors Product specification
74F776Pi–bus transceiver
December 19, 1990
7
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER TEST LIMITS UNIT
CONDITIONS
1
MIN TYP2MAX
I
OH
High–level output current B0 – B7 VCC = MAX, VIL = MAX, VIH = MIN, VOH = 2.1V 100 µA
I
OFF
Power–off output current B0 – B7 VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 2.1V 100 µA
VCC = MIN, I
OH
= –3mA, VX =V
CC
2.5 V
CC
V
V
OH
High-level output voltage A0 – A7
4
VIL = MAX, VIH = MIN
I
OH
= –4mA,
VX =3.13V and 3.47V
2.5 V
A0 – A7
4
VCC = MIN, I
OL
= 20mA, VX = V
CC
0.50 V
V
OL
Low-level output voltage B0 – B7 VIL = MAX I
OL
= 100mA 1.15 V
VIH = MIN I
OL
= 4mA 0.40 V
V
IK
Input clamp voltage A0 – A7 VCC = MIN, II = I
IK
-0.5 V
Except A0 – A7 VCC = MIN, II = I
IK
-1.2 V
I
I
Input current at OEBn, OEA, LE VCC = 0.0V, VI = 7.0V 100 µA maximum input voltage A0 – A7, B0 – B7 VCC = MAX, VI = 5.5V 1 mA
I
IH
High–level input current OEBn, OEA, LE VCC = MAX, VI = 2.7V , Bn –An =0V 20 µA
B0 – B7 VCC = MAX, VI = 2.1V 100 µA
I
IL
Low–level input current OEBn, OEA, LE VCC = MAX, VI = 0.5V –20 µA
B0 – B7 VCC = MAX, VI = 0.3V –100 µA
I
OZH
+ I
IH
Off state output current, high level voltage applied
A0 – A7 VCC = MAX, V
O
= 2.7V 70
µA
I
OZL
+ I
IL
Off state output current, low level voltage applied
A0 – A7 VCC = MAX, VO = 0.5V –70
µA
I
X
High–level control current
VCC = MAX, V
X
= VCC, LE = OEA = OEBn =
2.7V, A0 – A7 = 2.7V, B0 – B7 = 2.0V,
–100 100 µA
VCC = MAX, V
X
= 3.13 & 3.47V , LE = OEA =
2.7V, OEBn = A0 – A7 = 2.7V, B0 – B7 = 2.0V,
–10 10 µA
I
OS
Short circuit output current
3
A0 – A7 only
VCC = MAX, Bn = 1.8V, OEA = 2.0V, OEBn = 2.7V
-60 -150 mA
I
CCH
VCC = MAX 65 100 mA
I
CC
Supply current (total) I
CCL
VCC = MAX, VIL = 0.5V 100 145 mA
I
CCZ
75 100 mA
Notes to DC electrical characteristics
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. Unless otherwise specified, V
X
= VCC for all test conditions.
2. All typical values are at VCC = 5V, T
amb
= 25°C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, I
OS
tests should be performed last.
4. Due to test equipment limitations, actual test conditions are for V
IH
=1.8v and VIL = 1.3V .
Page 8
Philips Semiconductors Product specification
74F776Pi–bus transceiver
December 19, 1990
8
AC ELECTRICAL CHARACTERISTICS
A PORT LIMITS
T
amb
= +25°C T
amb
= 0°C to
+70
°C
T
amb
= –40°C to +85°C
SYMBOL PARAMETER TEST VCC = +5.0V
VCC = +5.0V ± 10% VCC = +5.0V ± 10%
UNIT
CONDITION CL = 50pF,
RL = 500
CL = 50pF,
RL = 500
CL = 50pF,
RL = 500
MIN TYP MAX MIN MAX MIN MAX
t
PLH
t
PHL
Propagation delay Bn to An
Waveform 1
5.5
4.5
8.0
6.0
12.0
9.0
5.5
4.5
12.0
9.0
5.5
4.5
12.0
9.0
ns
t
PZH
t
PZL
Output enable time to high or low, OEA to An
Waveform 3, 4
8.0
8.5
10.5
11.0
13.5
13.5
7.5
8.0
15.0
15.5
7.5
8.0
15.5
15.5
ns
t
PHZ
t
PLZ
Output disable time from high or low, OEA to An
Waveform 3, 4
2.0
2.0
3.5
4.5
6.0
7.0
1.5
2.0
6.5
7.5
1.5
2.0
6.5
7.5
ns
B PORT LIMITS
TEST
T
amb
= +25°C T
amb
= 0°C to
+70
°C
T
amb
= –40°C to +85°C
SYMBOL PARAMETER CONDITION VCC = +5.0V
VCC = +5.0V ± 10% VCC = +5.0V ± 10%
UNIT
C
D
= 30pF, RU = 9 CD = 30pF, RU = 9 CD = 30pF, RU = 9
MIN TYP MAX MIN MAX MIN MAX
t
PLH
t
PHL
Propagation delay An to Bn
Waveform 1
3.0
3.0
5.0
4.5
7.0
7.5
2.5
2.5
8.0
8.5
2.0
2.5
9.0
8.5
ns
t
PLH
t
PHL
Propagation delay LE to Bn
Waveform 1
3.5
3.5
5.0
5.0
8.0
8.0
3.0
2.5
9.0
9.0
2.5
2.5
9.5
9.5
ns
t
PLH
t
PHL
Enable/disable time OEB
n to An
Waveform 1
3.0
3.5
4.5
5.5
7.0
9.0
2.5
3.5
8.0
10.0
2.5
3.5
8.5
10.5
ns
t
TLH
t
THL
Transition time, B port
1.3V to 1.7V , 1.7V to 1.3V
Test Circuit and
Waveforms
0.5
0.5
2.0
2.0
4.5
4.5
0.5
0.5
5.0
4.5
0.5
0.5
5.0
4.5
ns
AC SETUP REQUIREMENTS
LIMITS
TEST
T
amb
= +25°C T
amb
= 0°C to +70°C T
amb
= –40°C to +85°C
SYMBOL PARAMETER CONDITION VCC = +5.0V
VCC = +5.0V ± 10% VCC = +5.0V ± 10%
UNIT
CL = 50pF,
RL = 500
CL = 50pF, RL = 500
CL = 50pF,
RL = 500
MIN TYP MAX MIN MAX MIN MAX
t
su
(H)
t
su
(L)
Setup time, high or low An to LE
Waveform 2
3.5
4.5
4.5
5.0
4.5
5.0
ns
th(H) t
h
(L)
Hold time, high or low An to LE
Waveform 2
0.0
0.0
0.0
0.0
0.0
0.0
ns
t
w
(L) LE pulse width, low Waveform 2 4.0 5.0 5.0 ns
AC WAVEFORMS
V
M
V
M
V
M
V
M
An, Bn
An, Bn, OEB
n
t
PLH
t
PHL
SF00427
Waveform 1. Propagation delay for data to output
LE
V
M
V
M
V
M
V
M
V
M
V
M
tsu(L)
th(L) th(H)
An
V
M
tw(L)
ts(H)
SF00428
Waveform 2. Data setup and hold times and LE pulse width
Page 9
Philips Semiconductors Product specification
74F776Pi–bus transceiver
December 19, 1990
9
AC WAVEFORMS (Continued)
V
M
V
M
V
M
t
PHZ
t
PZH
VOH -0.3V
0V
OEA
An
SF00429
Waveform 3. 3-state output enable time to high level and output disable time from high level
V
M
V
M
V
M
t
PLZ
t
PZL
VOL +0.3V
OEA
An
SF00430
Waveform 4. 3-state output enable time to low level and output disable time from low level
Notes to AC waveforms
For all waveforms, V
M
= 1.5V .
The shaded areas indicate when the input is permitted to change for predictable output performance.
TEST CIRCUIT AND WAVEFORMS
t
w
90%
V
M
10%
90%
V
M
10%
90%
V
M
10%
90%
V
M
10%
NEGATIVE PULSE
POSITIVE PULSE
t
w
AMP (V)
low V
low V
t
THL (tf
)
INPUT PULSE REQUIREMENTS
rep. rate
t
w
t
TLHtTHL
1MHz 500ns 2.5ns
2.5ns
Input pulse definition
V
CC
family
A port
D.U.T.
PULSE
GENERATOR
R
L
C
L
R
T
V
IN
V
OUT
Test circuit for 3–State outputs on A port
DEFINITIONS:
R
L
= Load resistor; see AC electrical characteristics for value. CL= Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RU= Pull up resistor; see AC electrical characteristics for value. C
D
= Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT= Termination resistance should be equal to Z
OUT
of pulse generators.
t
THL (tf
)
t
TLH (tr
)
t
TLH (tr
)
AMP (V)
amplitude
3.0V
1.5V
V
M
R
L
7.0V
V
CC
D.U.T.
PULSE
GENERATOR
C
D
R
T
V
IN
V
OUT
Test circuit for outputs on B port
R
U
7.0V
1MHz 500nsB port 2.0V 1.0V
4.0ns
4.0ns
Low V
0.0V
1.0V
SWITCH POSITION
TEST SWITCH
closed
openAll other
t
PLZ
, t
PZL
SF00431
Page 10
Philips Semiconductors Product specification
74F776Pi-bus transceiver
1990 Dec 19
10
DIP28: plastic dual in-line package; 28 leads (600 mil); long body SOT117-2
Page 11
Philips Semiconductors Product specification
74F776Pi-bus transceiver
1990 Dec 19
11
PLCC28: plastic leaded chip carrier; 28 leads SOT261-2
Page 12
Philips Semiconductors Product specification
74F776Pi-bus transceiver
yyyy mmm dd
12
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 10-98 Document order number: 9397-750-05177
 
Data sheet status
Objective specification
Preliminary specification
Product specification
Product status
Development
Qualification
Production
Definition
[1]
This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Data sheet status
[1] Please consult the most recently issued datasheet before initiating or completing a design.
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