Datasheet N74F74N, N74F74D Datasheet (Philips)

Page 1
74F74
Dual D-type flip-flop
Product specification Supercedes data of 1990 Oct 23 IC15 Data Handbook
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1996 Mar 12
Page 2
Philips Semiconductors Product specification
74F74Dual D-type flip-flop
FEA TURE
Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F74 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock input. When set and reset are inactive (high), data at the D input is transferred to the Q and Q must be stable just one setup time prior to the low-to-high transition of
outputs on the low-to-high transition of the clock. Data
PIN CONFIGURATION
1
D0
R
2
D0
CP0
3
S
D0
4
Q0
5
0
Q
6
GND
the clock for predictable operation. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. Following the hold time interval, data at the D input may be changed without affecting the levels of the output.
TYPE TYPICAL f
max
TYPICAL SUPPLY CURRENT (TOTAL)
74F74 125MHz 11.5mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
T
= 0°C to +70°C
amb
14-pin plastic DIP N74F74N I74F74N SOT27-1
14-pin plastic SO N74F74D I74F74D SOT108-1
INDUSTRIAL RANGE
VCC = 5V ±10%,
T
= –40°C to +85°C
amb
14 13 12 11 10
9 87
SF00045
V
CC
D1
R D1 CP1 SD1 Q1 Q1
PKG. DWG. #
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW
D0, D1 Data inputs 1.0/1.0 20µA/0.6mA CP0, CP1 Clock inputs (active rising edge) 1.0/1.0 20µA/0.6mA SD0, SD1 Set inputs (active low) 1.0/3.0 20µA/1.8mA RD0, RD1 Reset inputs (active low) 1.0/3.0 20µA/1.8mA
Q0, Q1, Q0, Q1 Data outputs 50/33 1.0mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
LOGIC SYMBOL
3 4 1
11 10 13
VCC = Pin 14 GND = Pin 7
212
D0 D1
CP0 SD0 RD0 CP1 SD1 RD1
Q0 Q0 Q1 Q1
56 98
SF00046
IEC/IEEE SYMBOL
4 3 2 1
10
11 12 13
&
S
C1
1D
R
S
C2
2D R
5
6
9
8
SF00047
1996 Mar 12 853 0335 16554
2
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Philips Semiconductors Product specification
T
Operating free air temperature range
SYMBOL
PARAMETER
UNIT
T
O erating free air tem erature range
74F74Dual D-type flip-flop
LOGIC DIAGRAM
FUNCTION TABLE
INPUTS OUTPUTS
S
R
CP
4, 10
D
1, 13
D
3, 11
5, 9
6, 8
Q
Q
SD RD CP D Q Q
L H X X H L Asynchronous set
H L X X L H Asynchronous reset
L L X X H H Undetermined* H H h H L Load ”1” H H l L H Load ”0” H H X NC NC Hold
D
VCC = Pin 14 GND = Pin 7
2, 12
SF00048
NOTES:
H = High voltage level h = High voltage level one setup time prior to low-to-high clock
transition L = Low voltage level l = Low voltage level one setup time prior to low-to-high clock
transition NC= No change from the previous setup X = Don’t care = Low-to-high clock transition
= Not low-to-high clock transition
* = This setup is unstable and will change when either set or reset
return to the high level.
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
amb
T
stg
Supply voltage –0.5 to +7.0 V Input voltage –0.5 to +7.0 V Input current –30 to +5 mA Voltage applied to output in high output state –0.5 to V Current applied to output in low output state 40 mA
p
p
Storage temperature range –65 to +150 °C
PARAMETER RATING UNIT
Commercial range 0 to +70 °C
Industrial range –40 to +85 °C
CC
OPERATING
MODE
V
RECOMMENDED OPERATING CONDITIONS
V
CC
V
IH
V
IL
I
Ik
I
OH
I
OL
amb
1996 Mar 12
Supply voltage 4.5 5.0 5.5 V High-level input voltage 2.0 V Low-level input voltage 0.8 V Input clamp current –18 mA High-level output current –1 mA Low-level output current 20 mA
p
LIMITS
MIN NOM MAX
p
Commercial range 0 +70 °C
Industrial range –40 +85 °C
3
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Philips Semiconductors Product specification
SYMBOL
PARAMETER
TEST CONDITIONS
1
UNIT
VOHHigh-level output voltage
V
MIN, V
MAX, V
MIN
I
MAX
VOLLow-level output voltage
V
MIN, V
MAX, V
MIN
I
MAX
I
74F74Dual D-type flip-flop
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
MIN TYP2MAX
p
p
V
IK
I
I
I
IH
IL
I
OS
I
CC
Input clamp voltage VCC = MIN, II = I Input current at maximum input
voltage High-level input current VCC = MAX, VI = 2.7V 20 µA
Low-level input current
Short-circuit output current Supply current (total)
Dn, CPn VCC = MAX, VI = 0.5V -0.6 mA
SDn, RDn VCC = MAX, VI = 0.5V -1.8 mA
3
4
CC
CC
=
=
=
IL
=
IL
IK
=
IH
=
IH
VCC = MAX, VI = 7.0V 100 µA
VCC = MAX -60 -150 mA VCC = MAX 11.5 16 mA
OH
OL
=
=
±10%V
±5%V
±10%V
±5%V
NOTES:
1 For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2 All typical values are at V 3 Not more than one output should be shorted at a time. For testing I
= 5V, T
CC
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
amb
= 25°C.
, the use of high-speed test apparatus and/or sample-and-hold
OS
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, I
4 Measure I
with the clock input grounded and all outputs open, then with Q and Q outputs high in turn.
CC
tests should be performed last.
OS
2.5 V
CC
2.7 3.4 V
CC
CC
CC
0.30 0.50 V
0.30 0.50 V
-0.73 -1.2 V
AC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER
f
max
t
PLH
t
PHL
t
PLH
t
PHL
Maximum clock frequency Waveform 1 100 125 100 90 MHz
Propagation delay CPn to Qn or Qn
Propagation delay SDn, RDn to Qn or Qn
TEST
CONDITION
Waveform 1
Waveform 2
AC SETUP REQUIREMENTS
SYMBOL PARAMETER
t
(H)
su
t
(L)
su
t
(H)
h
t
(L)
h
t
(H)
w
t
(L)
w
t
(L)
w
t
rec
Setup time, high or low Dn to CPn
Hold time, high or low Dn to CPn
CPn pulse width, high or low
SDn, RDn pulse width, low
Recovery time SDn, RDn to CPn
TEST
CONDITION
Waveform 1
Waveform 1
Waveform 1
Waveform 2 4.0 4.0 4.0 ns
Waveform 3 2.0 2.0 2.0 ns
LIMITS
VCC = +5.0V
T
= +25°C
amb
C
= 50pF, RL = 500
L
VCC = +5.0V ± 10%
T
= 0°C to +70°C
amb
C
= 50pF, RL = 500
L
VCC = +5.0V ± 10%
T
= –40°C to +85°C
amb
C
= 50pF, RL = 500
L
MIN TYP MAX MIN MAX MIN MAX
3.8
5.3
4.4
3.2
3.5
6.2
4.6
7.0
6.8
8.0
6.1
9.0
3.8
4.4
3.2
3.5
7.8
9.2
7.1
10.5
3.8
4.4
3.2
2.5
8.5
9.2
7.5
10.5
LIMITS
VCC = +5.0V
T
= +25°C
amb
C
= 50pF, RL = 500
L
VCC = +5.0V ± 10%
T
= 0°C to +70°C
amb
C
= 50pF, RL = 500
L
VCC = +5.0V ± 10%
T
= –40°C to +85°C
amb
C
= 50pF, RL = 500
L
MIN TYP MAX MIN MAX MIN MAX
2.0
3.0
1.0
1.0
4.0
5.0
2.0
3.0
1.0
1.0
4.0
5.0
2.0
3.0
1.0
1.0
4.0
5.0
UNIT
ns
ns
UNIT
ns
ns
ns
1996 Mar 12
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Philips Semiconductors Product specification
74F74Dual D-type flip-flop
AC WAVEFORMS
For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance.
Dn
CPn
Qn
Qn
V
M
tsu(L) th(L)
V
M
V
M
t
PLH
t
PHL
tw(H)
V
tsu(H) th(H)
1/f
max
(L)
t
V
M
V
M
V
M
w
V
M
M
V
M
t
PHL
V
M
t
PLH
V
M
SF01276
Waveform 1. Propagation delay for data to output, data setup time and hold times, and clock width, and maximum clock frequency
SDn or RDn
CPn
V
M
t
rec
V
M
SF00051
Waveform 3. Recovery time for set or reset to clock
t
PLH
t
PHL
tw(L)
V
M
(L)
t
t
PHL
t
PLH
w
V
M
V
M
SF00050
V
M
V
M
V
M
SDn
RDn
Qn
Qn
V
M
Waveform 2. Propagation delay for set and reset to output, set and reset pulse width
V
M
TEST CIRCUIT AND WAVEFORMS
V
CC
V
PULSE
GENERATOR
IN
R
T
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
R
= Load resistor;
L
see AC ELECTRICAL CHARACTERISTICS for value.
C
= Load capacitance includes jig and probe capacitance;
L
see AC ELECTRICAL CHARACTERISTICS for value.
R
= Termination resistance should be equal to Z
T
pulse generators.
D.U.T.
V
OUT
C
t
NEGATIVE PULSE
R
L
L
POSITIVE PULSE
90%
10%
V
M
10%
t
THL (tf
t
TLH (tr
90%
V
M
w
V
M
10%
)
)
t
w
t
TLH (tr
t
THL (tf
)
)
90%
V
M
90%
10%
AMP (V)
0V
AMP (V)
0V
Input Pulse Definition
INPUT PULSE REQUIREMENTS
V
amplitude
3.0V 1.5V
rep. rate
M
1MHz 500ns
t
w
t
TLHtTHL
2.5ns 2.5ns
SF00006
OUT
of
family
74F
1996 Mar 12
5
Page 6
Philips Semiconductors Product specification
74F74Dual D-type flip-flop
DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1
1996 Mar 12
6
Page 7
Philips Semiconductors Product specification
74F74Dual D-type flip-flop
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
1996 Mar 12
7
Page 8
Philips Semiconductors Product specification
74F74Dual D-type flip-flop
Data sheet status
Data sheet status
Objective specification
Preliminary specification
Product specification
Product status
Development
Qualification
Production
Definition
This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
[1]
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 10-98 Document order number: 9397-750-05066
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