•Two Master Resets to clear each 4-bit counter individually
DESCRIPTION
The 74F393 is a Dual Ripple Counter with separate Clock (CPn) and
Master Reset (MR) inputs to each counter. The two counters are
identified by the “a” and “b” suffixes in the pin configuration. The
operation of each half of the 74F393 is the same. The counters are
triggered by a High-to-Low transition of the Clock (CP
inputs. The counter outputs are internally connected to provide
Clock inputs to succeeding stages. The outputs of the ripple counter
do not change synchronously and should not be used for high speed
address decoding. The Master Resets (MR
and MRb) are active
a
High asynchronous inputs; one for each 4-bit counter. A High level
in the MR input overrides the Clock and sets the outputs Low.
and CPb)
a
PIN CONFIGURATION
1
a
CP
2
MRa
3
Q0a
4
Q1a
5
Q2a
6
Q3a
GND
TYPETYPICAL f
MAX
74F393125MHz40mA
14
V
CC
CP
b
13
MRb
12
Q0b
11
Q1b
10
Q2b
9
Q3b
87
SF00704
TYPICAL SUPPL Y CURRENT
(TOTAL)
ORDERING INFORMATION
COMMERCIAL RANGE
DESCRIPTION
14-pin plastic DIPN74F393NSOT27-1
14-pin plastic SON74F393DSOT108-1
VCC = 5V ±10%,
T
= 0°C to +70°C
amb
PKG DWG #
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINSDESCRIPTION74F (U.L.) HIGH/LOWLOAD VALUE HIGH/LOW
CPa, CP
MRa, MR
Qna – Q
b
b
nb
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
CP
1
13
2
12
VCC= Pin 14
GND = Pin 7
a
CP
b
MR
a
MR
b
Q0a Q1a Q2a Q3a Q0b Q1b Q2b Q3b
345611109 8
Clock inputs1.0/1.020µA/0.6mA
Master Reset inputs1.0/1.020µA/0.6mA
Data outputs50/33.31.0mA/20mA
IEC/IEEE SYMBOL (IEEE/IEC)
2
1
12
13
SF00705
CTR DIV 16
CT=0
+
CTR DIV 16
CT=0
+
0
3
0
3
3
4
5
6
11
10
9
8
SF00706
1988 Nov 01853–0295 94977
2
Page 3
Philips SemiconductorsProduct specification
COUNT
SYMBOL
PARAMETER
UNIT
74F393Dual 4-bit binary ripple counter
LOGIC DIAGRAM
Q
J
1, 13
CPn
2, 12
MRn
VCC = Pin 14
GND = Pin 7
CP
R
D
Q0n
3, 11
FUNCTION TABLE
OUTPUTS
Q
Q
J
CP
KQKQKQK
Q
R
D
Q
J
CP
R
D
Q
J
CP
R
D
0LLLL
1HLLL
0n
2LHLL
3HHLL
4LLHL
Q1n
4, 10
Q2n
5, 9
6, 8
Q3n
5HLHL
6LHHL
SF00707
7HHHL
8LLLH
9HLLH
10LHLH
11HHLH
12LLHH
13HLHH
14LHHH
15HHHH
H = High voltage level transition
L = Low voltage level
Q
1n
Q
2n
Q
3n
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage–0.5 to +7.0V
Input voltage –0.5 to +7.0V
Input current–30 to +5mA
Voltage applied to output in High output state–0.5 to V
Current applied to output in Low output state40mA
Operating free-air temperature range0 to +70°C
Storage temperature range–65 to +150°C
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
MINTYP
p
p
V
IK
I
I
I
IH
I
IL
I
OS
Input clamp voltageVCC = MIN, II = I
Input current at maximum input voltageVCC = MAX, VI = 7.0V100µA
High-level input currentVCC = MAX, VI = 2.7V20µA
Low-level input currentVCC = MAX, VI = 0.5V–0.6mA
Short-circuit output current
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
3. Not more than one output should be shorted at a time. For testing I
= 5V, T
CC
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
amb
= 25°C.
, the use of high-speed test apparatus and/or sample-and-hold
OS
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
tests should be performed last.
OS
2
MAX
0.300.50
0.300.50
–0.73–1.2V
2536mA
4258mA
AC ELECTRICAL CHARACTERISTICS
SYMBOLPARAMETER
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
Maximum clock frequencyWaveform 1100130100MHz
Propagation delay
CPn to Q0a or Q0b
Propagation delay
CPn to Q1a, Q1b
Propagation delay
CPn to Q2a, Q2b
Propagation delay
CPn to Q3a, Q3b
Propagation delay
MR to Qna, Qnb
LIMITS
TEST
CONDITION
VCC = +5V
T
= +25°C
amb
= 50pF, RL = 500Ω
C
L
VCC = +5V ± 10%
T
= 0°C to +70°C
amb
= 50pF, RL = 500Ω
C
L
UNIT
MINTYPMAXMINMAX
Waveform 1
Waveform 1
Waveform 1
Waveform 1
3.5
5.0
5.0
7.5
8.0
9.5
10.5
12.0
5.5
7.0
7.0
9.5
10.0
11.5
12.5
14.0
8.0
10.0
10.0
12.0
13.0
14.5
15.5
16.5
3.5
5.0
4.5
7.0
7.0
9.0
10.0
11.5
9.0
10.5
13.0
13.0
15.0
15.5
17.0
17.5
Waveform 24.06.09.04.09.0ns
ns
ns
ns
ns
1988 Nov 01
4
Page 5
Philips SemiconductorsProduct specification
74F393Dual 4-bit binary ripple counter
AC SETUP REQUIREMENTS
LIMITS
SYMBOLPARAMETER
tW(H)
tW(L)
tW(H)
t
REC
CPn Pulse width
High or Low
MR Pulse width
High
Recovery time
MR to CPn
AC WAVEFORMS
For all waveforms, VM = 1.5V.
1/f
MAX
CPn
Qna, Qnb
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency
V
M
t
tw(L)
PHL
tw(H)
V
M
V
M
t
PLH
TEST
CONDITION
VCC = +5V
T
= +25°C
amb
C
= 50pF, RL = 500Ω
L
MINTYPMAXMINMAX
Waveform 1
4.5
3.5
Waveform 23.54.5ns
Waveform 22.53.0ns
V
M
SF00709
MR
n
CP
Qna, Qnb
V
Waveform 2. Master Reset Pulse Width, Master Reset to
Output Delay, and Master Reset to Clock Recovery T ime
M
t
PHL
T
C
tw(H)
VCC = +5V ± 10%
= 0°C to +70°C
amb
= 50pF, RL = 500Ω
L
5.0
4.0
V
M
t
rec
V
M
V
M
SF00708
UNIT
ns
TEST CIRCUIT AND WAVEFORMS
V
CC
V
PULSE
GENERATOR
IN
R
T
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
R
= Load resistor;
L
see AC ELECTRICAL CHARACTERISTICS for value.
C
= Load capacitance includes jig and probe capacitance;
SO14: plastic small outline package; 14 leads; body width 3.9 mmSOT108-1
1988 Nov 01
7
Page 8
Philips SemiconductorsProduct specification
74F393Dual 4-bit binary ripple counter
Data sheet status
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1]
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print codeDate of release: 10-98
Document order number:9397-750-05125
yyyy mmm dd
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