Datasheet N74F191N, N74F191D Datasheet (Philips)

INTEGRATED CIRCUITS

74F191

Up/down binary counter with reset and ripple clock

Product specification IC15 Data Handbook

 

1995 Jul 17

Philips Semiconductors Product specification

74F191Up/Down binary counter with reset and ripple clock

FEA TURES

•High speed –125MHz typical f

MAX

•Synchronous, reversible counting

•4-Bit binary

•Asynchronous parallel load capability

•Cascadable without external logic

•Single up/down control input

DESCRIPTION

The 74F191 is a 4-bit binary counter. It contains four edge-triggered master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and synchronous count-up and count-down operations.

Asynchronous parallel load capability permits the counter to be preset to any desired number. Information present on the parallel data inputs (D outputs when the Parallel Load (PL overrides the counting function. Counting is inhibited by a High level on the count enable (CE) input. When CE is Low, internal state changes are initiated. Overflow/underflow indications are provided by two types of outputs, the Terminal Count (TC) and Ripple Clock (RC

).

The TC output is normally Low and goes High when: 1) the count reaches zero in the countdown mode or 2) reaches “15” in the count up mode. The TC output will remain High until a state change occurs, either by counting or presetting, or until U output should not be used as a clock signal because it is subject to decoding spikes. The TC signal is used internally to enable the RC output. When TC is High and CE is Low, the RC follows the clock pulse. The RC width, although delayed in time by two gate delays.

- D3) is loaded into the counter and appears on the

0

) input is Low. This operation

/D is changed. TC

output essentially duplicates the Low clock pulse

PIN CONFIGURATION

1

D

1

2

Q

1

3

Q

0

CE

4

U/D

5 6

Q

2

7

Q

3

GND

TYPE TYPICAL f

MAX

74F191 125MHz 40mA

16

V

CC

15

D

0

CP

14

RC

13

TC

12

PL

11 10

D

2

98

D

3

SF00729

TYPICAL

SUPPLY CURRENT

(TOTAL)

ORDERING INFORMATION

COMMERCIAL RANGE

DESCRIPTION

16-pin plastic DIP N74F191N SOT38-4

16-pin plastic SO N74F191D SOT109-1

VCC = 5V ±10%,

T

= 0°C to +70°C

amb

PKG DWG #

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS DESCRIPTION

D0 - D

3

Data inputs 1.0/1.0 20µA/0.6mA

74F(U.L.)

HIGH/LOW

CE Count enable input (active Low) 1.0/3.0 20µA/1.8mA CP Clock pulse input (active rising edge) 1.0/1.0 20µA/0.6mA PL Asynchronous parallel load control input (active Low) 1.0/1.0 20µA/0.6mA U/D Up/down count control input 1.0/1.0 20µA/0.6mA Q0 - Q

3

Flip-flop outputs 50/33 1.0mA/20mA RC Ripple clock output (active low) 50/33 1.0mA/20mA TC Terminal count output 50/33 1.0mA/20mA

NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state.

1995 Jul 17 853–0352 15459

2

LOAD VALUE

HIGH/LOW

Philips Semiconductors Product specification

74F191Up/Down binary counter with reset and ripple clock

LOGIC SYMBOL

4

5

14

11

VCC=Pin 16 GND=Pin 8

LOGIC DIAGRAM

PL

11

15 1 10 9

D0D

CE

/D

U

CP

PL

Q

0

LOGIC SYMBOL (IEEE/IEC)

4 5

D

1

2

3

13

RC

12

TC

Q

Q2Q

1

3

7623

14

11

15 1 10 9

SF00730

D

0

15 1 10 9

D

1

D

2

EN1 M2[DOWN]

M3[UP]

1,2–/1,3+ G4

C5 [LOAD]

5D

CTR DIV 10

[1] [2] [4] [8]

2(CT=0)Z6

3(CT=15)Z6

6, 4, 1

+ –

D

3

12

13

3 2 6 7

SF00731

5

U/D

4

CE

14

CP

VCC= Pin 16 GND = Pin 8

KJ

CP

S

TCRC

Q

R

D

Q

0

D

Q

S

KJ

CP

R

D

Q

1

D

Q

S

KJ

CP

R

D

Q

2

D

Q

S

KJ

CP

R

D

Q

3

D

Q

76231213

SF00732

1995 Jul 17

3

Philips Semiconductors Product specification

74F191Up/Down binary counter with reset and ripple clock

MODE SELECT — FUNCTION TABLE

INPUTS OUTPUTS OPERATING MODE

PL U/D CE CP D

L L

H L l ↑ X Count up Count up H H l ↑ X Count down Count down H X H X X No change Hold (do nothing)

X X

n

L

H

TC AND RC FUNCTION T ABLE

INPUTS TERMINAL COUNT STATE OUTPUTS

U/D CE CP Q

H H X H H H H L H L H X H H H H H H

L L H H H H H L H X L L L L L H H H X L L L L H H

H L L L L L H

H = High voltage level steady state L = Low voltage level steady state X = Don’t care

= Low pulse ↑ = Low-to-High clock transition l = Low voltage level one set-up time prior to the Low-to-High clock transition

0

Q

1

Q

n

L H

Q

2

Parallel load

Q

3

TC RC

1995 Jul 17

4

Philips Semiconductors Product specification

74F191Up/Down binary counter with reset and ripple clock

APPLICATIONS

DIRECTION CONTROL

ENABLE

CLOCK

ENABLE

CLOCK

U/D

RC RC RC CE CP

U/D CE CP

a. N-Stage Counter Using Ripple Clock

ENABLE

CLOCK

U/D

RC RC RC CE CP

U/D CE CP

b. Synchronous N-Stage Counter with Common Clock Using Ripple/Clock

U/D CE CP

* = Carry Gate

U/D CE

TC TC TC

**

CP

U/D CE CP

c. Synchronous N-Stage Counter with Common Clock and Terminal Count

SF00733

Figure 1.

The 74F191 simplifies the design of multi-stage counters, as indicated in Figure 1, each RC

output is used as the clock input for the next higher stage. When the clock source has a limited drive capability this configuration is particularly advantageous, since the clock source drives only the first stage. It is only necessary to inhibit the first stage to prevent counting in all stages, since a High signal on CE

inhibits the RC output pulse as indicated in the Mode Select Table. The timing skew between state changes in the first and last stages is represented by the cumulative delay of the clock as it ripples through the preceding stages. This is a disadvantage of the configuration in some applications.

Figure 1b shows a method of causing state changes to occur simultaneously in all stages. The RC

output signals propagate in

ripple fashion and all clock inputs are driven in parallel. The Low state duration of the clock in this configuration must be long enough to allow the negative-going edge of the RC to the last stage before the clock goes High. Since the RC

signal to ripple through

output of any package goes High shortly after its clock input goes High, there is no such restriction on the High state duration of the clock.

In Figure 1c, the configuration shown avoids ripple delays and their associated restrictions. The combined TC signals from all the preceding stages forms the CE

input signal for a given stage. An enable signal must also be included in each carry gate in order to inhibit counting. The TC output of a given stage is not affected by its own CE

, therefore, the simple inhibit scheme of Figure 1a and 1b

does not apply.

1995 Jul 17

5

Philips Semiconductors Product specification

SYMBOL

PARAMETER

UNIT

SYMBOL

PARAMETER

TEST CONDITIONS

1

UNIT

,

VOHHigh-level output voltage

V

CC

Min, V

IL

Max,

,

VOLLow-level output voltage

V

CC

Min, V

IL

Max,

V

5V

74F191Up/Down binary counter with reset and ripple clock

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.)

SYMBOL

V V I

IN

V I

OUT

T T

CC IN

OUT

amb stg

Supply voltage –0.5 to +7.0 V Input voltage –0.5 to +7.0 V Input current –30 to +5.0 mA Voltage applied to output in High output state –0.5 to +V Current applied to output in Low output state 40 mA Operating free-air temperature range 0 to +70 Storage temperature –65 to +150

RECOMMENDED OPERATING CONDITIONS

V V V I I I T

CC IH

IL IK OH OL

amb

Supply voltage 4.5 5.0 5.5 V High-level input voltage 2.0 V Low-level input voltage 0.8 V Input clamp current –18 mA High-level output current –1 mA Low-level output current 20 mA Operating free-air temperature range 0 70

PARAMETER RATING UNIT

CC

V

o

C

o

C

LIMITS

Min Nom Max

o

C

DC ELECTRICAL CHARACTERISTICS

(Over recommended operating free-air temperature range unless otherwise noted.)

LIMITS

Min Typ

V

= Min, V

p

V

IK

I

IH

I

IL

Input clamp voltage VCC = Min, II = I Input current at maximum input voltage VCC = Max, VI = 7.0V 100 µA High-level input current VCC = Max, VI = 2.7V 20 µA Low-level input current CE

Others

I

OS

I

CC

Short-circuit output current Supply current4 (total) VCC = Max 40 55 mA

3

IOH = Max, VIH = Min

V

= Min, V

IOL = Max, VIH = Min

= Max,

CC

VCC = Max –60 –150 mA

= Max

IK

= 0.

I

±10%V ±5%V ±10%V ±5%V

CC

2.5 V

CC

2.7 3.4 V

CC

NOTES:

1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.

2. All typical values are at V

3. Not more than one output should be shorted at a time. For testing I

= 5V, T

CC

techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting

amb

= 25°C.

, the use of high-speed test apparatus and/or sample-and-hold

OS

of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any

sequence of parameter tests, I

4. Measure I

all inputs grounded and all outputs open.

CC

tests should be performed last.

OS

2

Max

0.30 0.50 V

–0.73 –1.2 V

–1.8 mA –0.6 mA

1995 Jul 17

6

Philips Semiconductors Product specification

74F191Up/Down binary counter with reset and ripple clock

AC ELECTRICAL CHARACTERISTICS

LIMITS

T

= +25°C T

amb

SYMBOL PARAMETER TEST CONDITIONS VCC = +5.0V VCC = +5.0V ± 10% UNIT

CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω

Min Typ Max Min Max

f

MAX

f

MAX

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

Maximum clock frequency to Qn outputs

Maximum clock frequency to RC outputs

Propagation delay CP to Q

n

Propagation delay CP to TC

Propagation delay CP to RC

Propagation delay CE to RC

Propagation delay U

/D to RC

Propagation delay U/D to TC

Propagation delay Dn to Q

n

Propagation delay Dn to TC

Propagation delay Dn to RC

Propagation delay PL to Q

n

Propagation delay PL to TC

Propagation delay PL to RC

Waveform 1 100 125 90 MHz

Waveform 1 85 95 75 MHz

Waveform 1

Waveform 2

Waveform 4

Waveform 3 Waveform 3

Waveform 4 Waveform 3

Waveform 4 Waveform 5

Waveform 5

2.5

5.0

6.5

6.0

2.5

3.0

2.0

3.0

8.0

4.5

4.0

3.0

2.0

6.5

5.5

6.5

6.0

4.5

5.5

6.0

8.5

7.5

4.5

7.5

9.0

8.0

4.5

5.0

4.0

5.0

11.0

7.5

6.5

6.0

4.0

9.0

9.5

14.0

11.0

6.5

8.0

8.5

10.5

16.0

10.0

8.0

11.5

12.5

11.0

7.5

7.0

7.5

16.0

10.5

9.5

7.0

12.0

13.0

18.0

13.5

9.5

11.5

12.0

13.5

18.5

13.0

= 0°C to +70°C

amb

2.0

5.0

6.0

2.0

2.5

2.0

3.0

8.0

4.0

3.0

1.5

6.5

5.0

6.0

4.0

5.0

5.5

6.0

8.5

7.0

8.5

12.0

13.0

12.0

8.0

7.5

8.0

17.0

11.0

10.5

10.0

7.5

13.0

14.0

19.5

15.0

10.5

12.0

13.0

14.5

21.0

13.5

ns ns

1995 Jul 17

7

Philips Semiconductors Product specification

74F191Up/Down binary counter with reset and ripple clock

AC SETUP REQUIREMENTS

LIMITS

T

= +25°C T

SYMBOL PARAMETER TEST CONDITIONS VCC = +5.0V VCC = +5.0V ± 10% UNIT

ts(H) ts(L)

th(H) t

(L)

h

ts(L) Setup time, Low CE to CP Waveform 6 10.0 10.0 ns th(L) Hold time, Low CE to CP Waveform 6 0 0 ns ts(H)

ts(L) th(H)

th(L) tw(H)

tw(L) tw(L) PL Pulse width, Low Waveform 5 6.0 6.0 ns t

rec

Setup time, High or Low Dn to PL

Hold time, High or Low D

to PL

n

Setup time, High or Low U/D to CP

Hold time, High or Low U/D to CP

CP Pulse width, High or Low W aveform 1

Recovery time, PL to CP Waveform 5 6.0 6.0 ns

Waveform 6

amb

CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω

Min Typ Max Min Max

4.5

2.0

12.0

12.0 0

0

3.5

6.0

= 0°C to +70°C

amb

5.0

2.0

12.0

12.0 0

0

3.5

6.0

ns ns

1995 Jul 17

8

Philips Semiconductors Product specification

74F191Up/Down binary counter with reset and ripple clock

AC WAVEFORMS

NOTE: For all waveforms, VM = 1.5V

1/f

MAX

CP

V

M

tW(L)

V

M

tW(H)

t

PLH

V

M

RC

, Qn, TC

t

PHL

V

M

SF00734

Waveform 1. Propagation Delay, Clock Input to Output,

Clock Pulse Width, and Maximum Clock Frequency.

CE, CP

U/D

RC

V

M

t

PHL

V

M

V

M

t

PLH

Waveform 2. Propagation Delay, Clock, Clock Enable or

Up/Down to Ripple Clock Output

V

M

SF00735

RC, TC, Q

D

n

V

M

t

PLH

V

M

t

PHL

M

V

M

SF00736

Waveform 3. Propagation Delay, Non-Inverting Path

TC, Q

RC, Q

PL

V

M

tW(L) t

CP

t

n

PLH

t

PHL

V

M

REC

V

M

V

M

V

M

SF00738

Waveform 5. Parallel Load Pulse Width, Parallel Load to Output

Delay and Parallel Load to Clock Recovery Time

U/D, D

n

RC, TC

V

M

t

PHL

V

M

Waveform 4. Propagation Delay, Inverting Path

CE, D

n

U/D

PL

CP

The shaded areas indicate when the input is permitted to change for predictable output performance.

tS(H)

V

M

th(H)

V

M

V

M

Waveform 6. Data Set Up and Hold Times

V

t

PLH

tS(L)

M

V

M

SF00737

(L)

t

h

V

M

V

M

SF00739

1995 Jul 17

9

Philips Semiconductors Product specification

74F191Up/Down binary counter with reset and ripple clock

TEST CIRCUIT AND WAVEFORM

V

CC

PULSE

GENERATOR

V

IN

R

T

D.U.T.

V

OUT

R

C

L

Test Circuit for Totem-Pole Outputs

DEFINITIONS:

= Load resistor;

R

L

see AC ELECTRICAL CHARACTERISTICS for value.

C

= Load capacitance includes jig and probe capacitance;

L

see AC ELECTRICAL CHARACTERISTICS for value.

R

= Termination resistance should be equal to Z

T

pulse generators.

OUT

of

NEGATIVE PULSE

POSITIVE PULSE

family

74F

90%

10%

amplitude

t

w

V

M

10%

)

V

90%

M

t

THL (tf

t

TLH (tr

)

t

TLH (tr

t

THL (tf

t

w

Input Pulse Definition

INPUT PULSE REQUIREMENTS

V

rep. rate

M

3.0V 1.5V

1MHz 500ns

10%

)

90%

t

w

V

M

V

M

90%

10%

t

TLHtTHL

2.5ns 2.5ns

AMP (V)

0V

AMP (V)

0V

SF00006

1995 Jul 17

10

Philips Semiconductors Product specification

Up/down binary counter with reset and ripple clock

DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4

74F191

1995 Jul 17

11

Philips Semiconductors Product specification

Up/down binary counter with reset and ripple clock

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

74F191

1995 Jul 17

12

Philips Semiconductors Product specification

Up/down binary counter with reset and ripple clock

NOTES

74F191

1995 Jul 17

13

Philips Semiconductors Product specification

Up/down binary counter with reset and ripple clock

Data sheet status

Objective specification

Preliminary specification

Product specification

Product status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

[1]

74F191

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381

 Copyright Philips Electronics North America Corporation 1998

print code Date of release: 10-98 Document order number: 9397-750-05093

 

yyyy mmm dd

14