Page 1
INTEGRATED CIRCUITS
74F125, 74F126
Quad buffers (3-State)
Product specification
IC15 Data Handbook
1989 March 28
Page 2
Philips Semiconductors Product specification
74F125, 74F126Quad buffers (3-State)
FEA TURE
•High impedance NPN base inputs for reduced loading
(20µA in High and Low states)
TYPE
TYPICAL
PROPAGATION
DELAY
TYPICAL
SUPPLY CURRENT
(TOTAL)
ORDERING INFORMATION
COMMERCIAL RANGE
V
DESCRIPTION
14-pin plastic DIP N74F125N, N74F126N SOT27-1
14-pin plastic SO N74F125D, N74F126D SOT108-1
= 5V ±10%,
CC
= 0°C to +70°C
T
amb
74F125 5.0ns 23mA
74F126 5.0ns 26mA
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW
D0–D3 Data inputs 1.0/0.033 20µA/20µA
OE0–OE3 Output Enable inputs (active Low), 74F125 1.0/0.033 20µA/20µA
OE0–OE3 Output Enable inputs (active High), 74F126 1.0/0.033 20µA/20µA
Q0–Q3 Data outputs 750/106.7 15mA/64mA
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
PIN CONFIGURATIONS
74F126
1
2
3
4
5
6
OE
OE
GND
D0
Q0
D1
Q1
74F125
1
0
2
3
1
4
5
6
14
V
OE
13
D3
12
Q3
11
OE2
10
D2
9
Q2
87
SF00117
CC
3
OE0
D0
Q0
OE1
D1
Q1
GND
14
V
OE3
13
D3
12
Q3
11
OE2
10
D2
9
Q2
87
SF00118
PKG DWG #
CC
LOGIC SYMBOLS
74F125
25
10
13
V
= Pin 14
CC
GND = Pin 7
1
4
OE0
OE1
OE2
OE3
Q0 Q0
36
March 28, 1989 853–0341 96146
D1 D2
912
D3D0
Q1 Q1
811
SF00119
2
10
13
= Pin 14
V
CC
GND = Pin 7
1
4
OE0
OE1
OE2
OE3
74F126
25
D1 D2
Q0 Q0
36
912
D3D0
Q1 Q1
811
SF00120
Page 3
Philips Semiconductors Product specification
74F125, 74F126Quad buffers (3-State)
IEC/IEEE SYMBOLS
1
2
4
5
10
9
13
12
LOGIC DIAGRAMS
OE
D0
OE
D1
OE
D2
OE
VCC = Pin 14
GND = Pin 7
D3
74F125
EN
1
3
6
8
11
SF00121
1
2
4
5
10
9
13
12
74F125
1
0
2
4
1
5
10
2
9
13
3
12
3
Q0
6
Q1
8
Q2
11
Q3
SF00123
VCC = Pin 14
GND = Pin 7
OE0
D0
OE1
D1
OE2
D2
OE3
D3
1
2
4
5
10
9
13
12
EN
74F126
1
74F126
3
6
8
11
SF00124
3
6
8
11
SF00122
Q0
Q1
Q2
Q3
FUNCTION TABLE, 74F125
FUNCTION TABLE, 74F126
I NPUTS OUTPUT
OEn Dn Qn
L L L
L H H
OEn Dn Qn
H L L
H H H
H X Z
NOTES TO THE FUNCTION TABLES:
H = High voltage level
L = Low voltage level
X = Don’t care
Z = High impedance “off” state
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage –0.5 to +7.0 V
Input voltage –0.5 to +7.0 V
Input current –30 to +5 mA
Voltage applied to output in High output state –0.5 to V
Current applied to output in Low output state 128 mA
Operating free-air temperature range 0 to +70 °C
Storage temperature range –65 to +150 °C
PARAMETER RATING UNIT
I NPUTS OUTPUT
L X Z
CC
V
March 28, 1989
3
Page 4
Philips Semiconductors Product specification
SYMBOL
PARAMETER
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
1
UNIT
I
3mA
VOHHigh-level output voltage
V
MAX
I
15mA
VOLLow-level output voltage
V
MAX
I
MAX
ICCSupply current (total)
74F125, 74F126Quad buffers (3-State)
RECOMMENDED OPERATING CONDITIONS
LIMITS
MIN NOM MAX
V
CC
V
IH
V
IL
I
IK
I
OH
I
OL
T
amb
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
V
IK
I
I
I
IH
I
IL
I
OZH
I
OZL
I
OS
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
3. Not more than one output should be shorted at a time. For testing I
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
Supply voltage 4.5 5.0 5.5 V
High-level input voltage 2.0 V
Low-level input voltage 0.8 V
Input clamp current –18 mA
High-level output current –15 mA
Low-level output current 64 mA
Operating free air temperature range 0 +70 °C
LIMITS
2
MAX
0.55 V
0.42 0.55 V
–0.73 –1.2 V
VCC = MIN,
=
p
IL
V
IH
,
= MIN
VCC = MIN,
=
p
IL
V
IH
,
= MIN
Input clamp voltage VCC = MIN, II = I
MIN TYP
OH
OH
=–
=–
±10%V
±5%V
±10%V
±5%V
CC
CC
±10%V
=
OH
IK
±5%V
CC
2.4 V
CC
2.7 3.3 V
2.0 V
CC
2.0 V
CC
Input current at maximum input voltage VCC = 0.0V, VI = 7.0V 100 µA
High-level input current VCC = MAX, VI = 2.7V 20 µA
Low-level input current VCC = MAX, VI = 0.5V –20 µA
Off-state output current,
High-level voltage applied
Off-state output current,
Low-level voltage applied
Short circuit output current
pp
= 5V, T
CC
amb
tests should be performed last.
OS
3
74F125
74F126
= 25°C.
VCC = MAX, VO = 2.7V 50 µA
VCC = MAX, VO = 0.5V –50 µA
VCC = MAX –100 –225 mA
I
CCH
I
CCL
I
CCZ
I
CCH
I
CCL
I
CCZ
VCC = MAX
VCC = MAX
OEn = GND, Dn = 4.5V 17 24 mA
OEn = Dn = GND 28 40 mA
OEn = Dn = 4.5V 25 35 mA
OEn = Dn = 4.5V 20 30 mA
OEn = 4.5V, Dn = GND 32 48 mA
OEn = GND, Dn = 4.5V 26 39 mA
, the use of high-speed test apparatus and/or sample-and-hold
OS
March 28, 1989
4
Page 5
Philips Semiconductors Product specification
TEST
CONDITION
74F125, 74F126Quad buffers (3-State)
AC ELECTRICAL CHARACTERISTICS
LIMITS
VCC = +5.0V VCC = +5.0V ± 10%
SYMBOL PARAMETER
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation delay
Dn to Qn
Output Enable time
to High or Low level
Output Disable time
from High or Low level
Propagation delay
Dn to Qn
Output Enable time
to High or Low level
Output Disable time
from High or Low level
74F125
74F126
Waveform 1
Waveform 2
Waveform 3
Waveform 2
Waveform 3
Waveform 1
Waveform 2
Waveform 3
Waveform 2
Waveform 3
T
= +25°C T
amb
= 0°C to +70°C UNIT
amb
CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω
MIN TYP MAX MIN MAX
2.0
3.0
3.5
4.0
1.5
1.5
2.0
3.0
4.0
4.0
2.0
3.0
4.0
5.5
5.5
6.0
3.5
3.5
4.0
5.5
6.0
6.0
4.5
5.5
6.0
7.5
7.5
8.0
5.0
5.5
6.5
8.0
7.5
8.0
6.5
7.5
2.0
3.0
3.5
4.0
1.5
1.5
2.0
3.0
3.5
3.5
2.0
3.0
6.5
8.0
8.5
9.0
6.0
6.0
7.0
8.5
8.5
8.5
7.5
8.0
ns
ns
ns
ns
ns
ns
AC WAVEFORMS
For all waveforms, VM = 1.5V.
Dn
Qn
Waveform 1. Propagation Delay for Input to Output
OEn
OEn
Qn
Waveform 2. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
V
M
t
PLH
V
M
t
PZH
V
M
t
PHL
V
M
V
M
t
PHZ
V
M
V
M
SF00125
VOH–0.3V
SF00126
OEn
V
M
t
PLZ
V
M
VOL+0.3V
SF00127
OEn
Qn
V
M
t
PZL
Waveform 3. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
0V
March 28, 1989
5
Page 6
Philips Semiconductors Product specification
74F125, 74F126Quad buffers (3-State)
TEST CIRCUIT AND WAVEFORM
V
CC
PULSE
GENERATOR
V
IN
R
T
D.U.T.
V
OUT
Test Circuit for Open Collector Outputs
SWITCH POSITION
TEST SWITCH
t
PLZ
t
PZL
closed
closed
All other open
7.0V
R
L
C
R
L
L
NEGATIVE
PULSE
POSITIVE
PULSE
90%
10%
V
M
10%
t
THL (tf
t
TLH (tr
90%
V
M
Input Pulse Definition
t
w
V
M
10%
)
)
t
)
TLH (tr
t
)
THL (tf
90%
V
M
t
w
90%
10%
AMP (V)
0V
AMP (V)
0V
DEFINITIONS:
= Load resistor;
R
L
see AC electrical characteristics for value.
C
= Load capacitance includes jig and probe capacitance;
L
see AC electrical characteristics for value.
R
= T ermination resistance should be equal to Z
T
pulse generators.
OUT
of
family
74F
INPUT PULSE REQUIREMENTS
V
amplitude
3.0V
M
1.5V
rep. rate
1MHz 500ns
t
w
t
TLH
t
THL
2.5ns 2.5ns
SF00128
March 28, 1989
6
Page 7
Philips Semiconductors Product specification
74F125, 74F126Quad buffers (3-State)
DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1
1989 March 28
7
Page 8
Philips Semiconductors Product specification
74F125, 74F126Quad buffers (3-State)
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
1989 March 28
8
Page 9
Philips Semiconductors Product specification
74F125, 74F126Quad buffers (3-State)
NOTES
1989 March 28
9
Page 10
Philips Semiconductors Product specification
74F125, 74F126Quad buffers (3-State)
Data sheet status
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1]
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 10-98
Document order number: 9397-750-05073
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