Page 1
INTEGRATED CIRCUITS
74F109
Positive J-K
flip-flops
Product specification
IC15 Data Handbook
positive edge-triggered
1990 Oct 23
Page 2
Philips Semiconductors Product specification
74F109Postive J-K positive edge-triggered flip-flops
FEA TURE
PIN CONFIGURATION
•Industrial temperature range available (–40°C to +85°C)
1
D0
R
2
CP0
S
J0
K
3
0
4
D0
5
0
6
Q
Q
0
DESCRIPTION
The 74F109 is a dual positive edge-triggered JK-type flip-flop
featuring individual J, K
complementary outputs. Set (S
active low inputs and operate independently of the clock (CP) input.
The J and K
are edge-triggered inputs which control the state
changes of the flip-flops as described in the function table. Clock
triggering occurs at a voltage level and is not directly related to the
transition time of the positive-going pulse. The J and K
, clock, set, and reset inputs; also true and
D) and reset (RD) are asynchronous
inputs must
be stable just one setup time prior to the low-to-high transition of the
clock for predictable operation. The JK
D flip-flop by tying J and K
inputs together. Although the clock input
design allows operation as a
is level sensitive, the positive transition of the clock pulse between
the 0.8V and 2.0V levels should be equal to or less than the clock to
output delay time for reliable operation.
TYPE TYPICAL f
TYPICAL SUPPL Y CURRENT
max
(TOTAL)
74F109 125MHz 12.3mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
16-pin plastic DIP N74F109N I74F109N SOT38-4
16-pin plastic SO N74F109D I74F109D SOT109-1
COMMERCIAL RANGE
VCC = 5V ±10%, T
= 0°C to +70°C
amb
VCC = 5V ±10%, T
INDUSTRIAL RANGE
= –40°C to +85°C
amb
16
15
14
13
12
11
107
98GND Q1
SF00135
V
R
J1
K1
CP1
SD1
Q1
CC
D1
PKG DWG #
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD V ALUE HIGH/LOW
J0, J1 J inputs 1.0/1.0 20µA/0.6mA
K0, K1 K inputs 1.0/1.0 20µA/0.6mA
CP0, CP1 Clock inputs (active rising edge) 1.0/1.0 20µA/0.6mA
SD0, SD1 Set inputs (active Low) 1.0/3.0 20µA/1.8mA
RD0, RD1 Reset inputs (active Low) 1.0/3.0 20µA/1.8mA
Q0, Q1, Q0, Q1 Data outputs 50/33 1.0mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
4
5
1
12
11
15
VCC = Pin 16
GND = Pin 8
CP0
SD0
RD0
CP1
SD1
RD1
2 14 3 13
J1
K0
J0
Q0 Q0 Q1 Q1
6 7 10 9
SF00136
K1
IEC/IEEE SYMBOL
2
4
3
1
5
14
12
13
15
11
1J
C1
1K
R
S
2J
C2
2K
R
S
SF00137
6
7
10
9
October 23, 1990 853–0337 00783
2
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Philips Semiconductors Product specification
OPERATING MODE
T
Operating free-air temperature range
SYMBOL
PARAMETER
UNIT
T
Operating free-air temperature range
74F109Postive J-K positive edge-triggered flip-flops
LOGIC DIAGRAM
7, 9
Q
3, 13
K
2, 14
J
4, 12
CP
5, 11
S
D
1, 15
R
D
V
= Pin 16
CC
GND = Pin 8
6, 10
SF00138
FUNCTION TABLE
INPUTS OUTPUTS
Q
SD RD CP J K Q Q
L H X X X H L Asynchronous set
H L X X X L H Asynchronous reset
L L X X X H H Undetermined*
H H ↑ X X q q Hold
H H ↑ h l q q Toggle
H H ↑ h h H L Load ”1” (set)
H H ↑ l l L H Load ”0” (reset)
H H ↑ l h q q Hold ’no change”
NOTES:
H = High-voltage level
h = High-voltage level one setup time prior to low-to-high
clock transition
L = Low-voltage level
l = Low-voltage level one setup time prior to low-to-high
clock transition
q = Lower case indicate the state of the referenced output
prior to the low-to-high clock transition
X = Don’t care
↑ = Low-to-high clock transition
= Not low-to-high clock transition
↑
* = Both outputs will be high if both S
D and RD go low
simultaneously
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
amb
T
stg
Supply voltage –0.5 to +7.0 V
Input voltage –0.5 to +7.0 V
Input current –30 to +5 mA
Voltage applied to output in High output state –0.5 to V
Current applied to output in Low output state 40 mA
p
p
Storage temperature range –65 to +150 °C
PARAMETER RATING UNIT
CC
Commercial range 0 to +70 °C
Industrial range –40 to +85 °C
RECOMMENDED OPERATING CONDITIONS
LIMITS
MIN NOM MAX
V
V
V
I
I
I
CC
IN
IL
IK
OH
OL
amb
Supply voltage 4.5 5.0 5.5 V
High-level input voltage 2.0 V
Low-level input voltage 0.8 V
Input clamp current –18 mA
High-level output current –1 mA
Low-level output current 20 mA
p
p
Commercial range 0 +70 °C
Industrial range –40 +85 °C
V
October 23, 1990
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Philips Semiconductors Product specification
SYMBOL
PARAMETER
TEST CONDITIONS
1
UNIT
,
VOHHigh-level output voltage
V
CC
MIN, V
IL
MAX,
I
MAX
,
VOLLow-level output voltage
V
CC
MIN, V
IL
MAX,
IILLow-level input current
74F109Postive J-K positive edge-triggered flip-flops
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
MIN TYP2MAX
V
= MIN, V
p
p
V
IK
I
I
I
IH
I
OS
I
CC
Input clamp voltage VCC = MIN, II = I
Input current at maximum input voltage VCC = MAX, VI = 7.0V 100 µA
High-level input current VCC = MAX, VI = 2.7V 20 µA
p
Short-circuit output current
J, K, CPn VCC = MAX, VI = 0.5V –0.6 mA
SDn, RDn VCC = MAX, VI = 0.5V –1.8 mA
3
Supply current4 (total) VCC = MAX 12.3 17 mA
VIH = MIN
V
= MIN, V
VIH = MIN
VCC = MAX -60 –150 mA
= MAX
= MAX
IK
I
OH
OL
=
= MAX
±10%V
±5%V
±10%V
±5%V
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
3. Not more than one output should be shorted at a time. For testing I
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
= 5V, T
CC
amb
= 25°C.
, the use of high-speed test apparatus and/or sample-and-hold
OS
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
4. Measure I
with the clock input grounded and all outputs open, then with Q and Q outputs high in turn.
CC
tests should be performed last.
OS
2.5 V
CC
2.7 3.4 V
CC
CC
CC
0.30 0.50 V
0.30 0.50 V
–0.73 –1.2 V
AC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
Maximum clock frequency Waveform 1 90 125 90 90 MHz
Propagation delay
CPn to Qn or Qn
Propagation delay
SDn, RD to Qn or Qn
CONDITION
Waveform 1
Waveform 2, 3
AC SETUP REQUIREMENTS
SYMBOL PARAMETER
t
(H)
su
tsu(L)
t
(H)
h
t
(L)
h
t
(H)
w
t
(L)
w
t
(L) SDn or RDn pulse width,
w
t
rec
Setup time, high or low
Dn to CPn
Hold time, high or low
Dn to CPn
CP pulse width,
high or low
low
Recovery time
SDn or RDn to CP
CONDITION
Waveform 1
Waveform 1
Waveform 1
Waveform 2
Waveform 3 2.0 2.0 2.0 ns
TEST
TEST
LIMITS
VCC = +5.0V
T
= +25°C
amb
C
= 50pF
L
R
= 500Ω
L
VCC = +5.0V ± 10%
T
= 0°C to +70°C
amb
C
= 50pF
L
R
= 500Ω
L
VCC = +5.0V ± 10%
T
= –40°C to +85°C
amb
C
= 50pF
L
R
= 500Ω
L
MIN TYP MAX MIN MAX MIN MAX
3.8
5.3
4.4
3.2
3.5
6.2
5.2
7.0
7.0
8.0
7.0
9.0
3.8
4.4
3.2
3.5
8.0
9.2
8.0
10.5
3.8
4.4
2.8
3.5
9.0
9.2
9.0
10.5
LIMITS
VCC = +5.0V
T
= +25°C
amb
C
= 50pF
L
= 500Ω
R
L
VCC = +5.0V ± 10%
T
= 0°C to +70°C
amb
C
= 50pF
L
= 500Ω
R
L
VCC = +5.0V ± 10%
T
= –40°C to +85°C
amb
C
= 50pF
L
= 500Ω
R
L
MIN TYP MAX MIN MAX MIN MAX
3.0
3.0
1.0
1.0
4.0
5.0
3.0
3.0
1.0
1.0
4.0
5.0
3.0
3.0
1.0
1.0
4.0
5.0
4.0 4.0 4.0
UNIT
ns
ns
UNIT
ns
ns
ns
ns
October 23, 1990
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Page 5
Philips Semiconductors Product specification
74F109Postive J-K positive edge-triggered flip-flops
AC WAVEFORMS
For all waveforms, VM = 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Jn, K
n
CPn
Qn
Qn
Waveform 1. Propagation Delay for Data to Output, Data Setup
Time and Hold Times, and Clock Width,and Maximum
Clock Frequency
V
M
tsu(L) th(L)
V
M
V
t
t
M
PLH
PHL
tw(H)
V
tsu(H) th(H)
1/f
max
V
M
(L)
t
w
V
M
V
M
V
M
V
M
M
t
PHL
t
PLH
V
M
V
M
SF00139
t
PLH
t
PHL
tw(L)
V
M
t
(L)
t
PHL
t
w
V
PLH
V
V
M
M
SF00050
V
M
V
M
V
M
SDn
RDn
Qn
Qn
V
M
Waveform 2. Propagation Delay for Set and Reset to Output,
Set and Reset Pulse Width
SDn or RDn
CPn
V
M
t
rec
V
M
SF00051
Waveform 3. Recovery Timer for Set or Reset to Clock
M
October 23, 1990
5
Page 6
Philips Semiconductors Product specification
74F109Postive J-K positive edge-triggered flip-flops
TEST CIRCUIT AND WAVEFORMS
V
CC
PULSE
GENERATOR
V
IN
R
T
D.U.T.
V
OUT
R
C
L
L
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
= Load resistor;
R
L
see AC ELECTRICAL CHARACTERISTICS for value.
C
= Load capacitance includes jig and probe capacitance;
L
see AC ELECTRICAL CHARACTERISTICS for value.
R
= Termination resistance should be equal to Z
T
pulse generators.
OUT
of
NEGATIVE
PULSE
POSITIVE
PULSE
family
74F
90%
10%
amplitude
t
w
V
M
10%
)
V
90%
M
t
THL (tf
t
TLH (tr
)
t
TLH (tr
t
THL (tf
t
w
Input Pulse Definition
INPUT PULSE REQUIREMENTS
V
rep. rate
M
3.0V 1.5V
1MHz 500ns
10%
)
)
90%
t
w
V
M
V
M
90%
10%
t
TLHtTHL
2.5ns 2.5ns
AMP (V)
0V
AMP (V)
0V
SF00006
October 23, 1990
6
Page 7
Philips Semiconductors Product specification
Positive J-K
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
positive edge-triggered flip-flops
74F109
1990 Oct 23
7
Page 8
Philips Semiconductors Product specification
Positive J-K
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
positive edge-triggered flip-flops
74F109
1990 Oct 23
8
Page 9
Philips Semiconductors Product specification
Positive J-K
positive edge-triggered flip-flops
NOTES
74F109
1990 Oct 23
9
Page 10
Philips Semiconductors Product specification
Positive J-K
Data sheet status
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
positive edge-triggered flip-flops
Definition
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1]
74F109
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 10-98
Document order number: 9397-750-05069
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