Datasheet N74ALS377D, N74ALS377DB, N74ALS377N Datasheet (Philips)

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74ALS377
Octal D flip–flop with enable
Product specification IC05 Data Handbook
1991 Feb 08
INTEGRATED CIRCUITS
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74ALS377Octal D flip-flop with enable
2
1991 Feb 08 853–1399 01670
FEA TURES
•Ideal for addressable register applications
•Enable for address and data synchronization applications
•Eight edge-triggered D-type flip-flops
•Buffered common clock
•See 74ALS273 for master reset version
•See 74ALS373 for transparent latch version
•See 74ALS374 for 3-State version
DESCRIPTION
The 74ALS377 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E
) is Low.
The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition, is transferred to the corresponding flip-flop’s Q output. The E
input must be stable one setup time prior to the Low-to-High clock transition for predictable operation.
TYPE
TYPICAL f
MAX
TYPICAL
SUPPLY CURRENT
(TOTAL)
74ALS377 95MHz 15mA
PIN CONFIGURATION
20 19 18 17 16 15 14 13 12
10 11
9
8
7
6
5
4
3
2
1
V
CC
Q7 D7 D6 Q6 Q5 D5 D4 Q4
CP
Q0
D0
D1 Q1 Q2
D2
D3 Q3
GND
E
SF00350
ORDERING INFORMA TION
ORDER CODE
DESCRIPTION COMMERCIAL RANGE
V
CC
= 5V ±10%,
T
amb
= 0°C to +70°C
DRAWING
NUMBER
20-pin plastic DIP 74ALS377N SOT146-1
20-pin plastic SOL 74ALS377D SOT163-1
20-pin plastic SSOP
Type II
74ALS377DB SOT339-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
74ALS (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
D0 – D7 Data inputs 1.0/2.0 20µA/0.2mA
CP Clock pulse input (active rising edge) 1.0/1.0 20µA/0.1mA
E Latch enable input 1.0/1.0 20µA/0.1mA
Q0 – Q7 Data outputs 130/240 2.6mA/24mA
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
LOGIC SYMBOL
SF00351
3 4 7 8 13 14 1817
D0 D1 D2 D3 D4 D5 D6 D7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 5 6 9 12 15 16 19
1
11
E
CP
V
CC
= Pin 20
GND = Pin 10
IEC/IEEE SYMBOL
SF00352
1
32 4
5
7
6
8
9
G1
11
1C2
13
12
14
15
17
16
18
19
2D
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74ALS377Octal D flip-flop with enable
1991 Feb 08
3
LOGIC DIAGRAM
DQ
CP
D
CP
D
CP
DQ
CP
QQ
3478
11
Q0 Q1 Q2 Q3
CP
D0 D1 D2 D3
DQ
CP
D
CP
D
CP
DQ
CP
QQ
13 14 17 18
D4 D5 D6 D7
1
2 5 6 9 12 15 16 19
Q4 Q5 Q6 Q7
E
SF00353
VCC = Pin 20 GND = Pin 10
FUNCTION TABLE
INPUTS OUTPUTS
E CP Dn Qn
OPERATING MODE
l ↑ h H Load “1”
l ↑ l L Load “0” h ↑ X NC H X X NC
Hold (do nothing)
H = High-voltage level h = High state must be present one setup time before the Low-to-High clock transition L = Low-voltage level l = Low state must be present one setup time before the Low-to-High clock transition NC= No change X = Don’t care ↑ = Low-to-High clock transition
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74ALS377Octal D flip-flop with enable
1991 Feb 08
4
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.)
SYMBOL
PARAMETER RATING UNIT
V
CC
Supply voltage –0.5 to +7.0 V
V
IN
Input voltage –0.5 to +7.0 V
I
IN
Input current –30 to +5 mA
V
OUT
Voltage applied to output in High output state –0.5 to V
CC
V
I
OUT
Current applied to output in Low output state 48 mA
T
amb
Operating free-air temperature range 0 to +70 °C
T
stg
Storage temperature range –65 to +150 °C
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
MIN NOM MAX
UNIT
V
CC
Supply voltage 4.5 5.0 5.5 V
V
IH
High-level input voltage 2.0 V
V
IL
Low-level input voltage 0.8 V
I
IK
Input clamp current –18 mA
I
OH
High-level output current –2.6 mA
I
OL
Low-level output current 24 mA
T
amb
Operating free-air temperature range 0 +70 °C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
1
MIN TYP
2
MAX
UNIT
p
VCC±10%, VIL = MAX,
IOH = –0.4mA V
CC
– 2 V
VOHHigh-level output voltage
CC
,
IL
,
VIH = MIN
IOH = MAX 2.4 3.2 V
p
VCC = MIN, VIL = MAX,
I
OL
= 12mA 0.25 0.40 V
VOLLow-level output voltage
CC
,
IL
,
VIH = MIN
I
OL
= 24mA 0.35 0.50 V
V
IK
Input clamp voltage VCC = MIN, II = I
IK
–0.73 –1.5 V
I
I
Input current at maximum input voltage VCC = MAX, VI = 7.0V 0.1 mA
I
IH
High-level input current VCC = MAX, VI = 2.7V 20 µA
p
E, CP
–0.1 mA
IILLow-level input current
Dn
V
CC
=
MAX, V
I
= 0.
4V
–0.2 mA
I
O
Output current
3
VCC = MAX, VO = 2.25V –30 –112 mA
pp
I
CCH
12 18 mA
ICCSupply current (total)
I
CCL
V
CC
=
MAX
20 29 mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25°C.
3. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
OS
.
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74ALS377Octal D flip-flop with enable
1991 Feb 08
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AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL PARAMETER TEST CONDITION
T
amb
= 0°C to +70°C
V
CC
= +5.0V ± 10%
C
L
= 50pF, RL = 500Ω
UNIT
MIN MAX
f
MAX
Maximum clock frequency Waveform 1 65 MHz
t
PLH
t
PHL
Propagation delay CP to Qn
Waveform 1
2.0
3.0
8.0
11.0
ns
AC SETUP REQUIREMENTS
LIMITS
SYMBOL PARAMETER TEST CONDITION
T
amb
= 0°C to +70°C
V
CC
= +5.0V ± 10%
C
L
= 50pF, RL = 500Ω
UNIT
MIN MAX
tsu(H)
t
su
(L)
Setup time, High or Low Dn to CP
Waveform 2
5.0
5.0
ns
th(H) t
h
(L)
Hold time, High or Low Dn to CP
Waveform 2
0.0
0.0
ns
tsu(H)
t
su
(L)
Setup time, High or Low E
to CP
Waveform 2
1.0
1.0
ns
th(H) t
h
(L)
Hold time, High or Low E
to CP
Waveform 2
3.0
3.0
ns
tw(H)
t
w
(L)
CP pulse width, High or Low
Waveform 1
6.0
8.0
ns
AC WAVEFORMS
For all waveforms, VM = 1.3V . The shaded areas indicate when the input is permitted to change for predictable output performance.
CP
V
M
V
M
V
M
tw(H)
1/f
max
V
M
V
M
t
PLH
tw(L)t
PHL
Qn
SF00294
Waveform 1. Propagation Delay for Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency
SC00076
t
su
t
h
Dn
E
V
M
V
M
tsu(L)
t
h
= 0
CP
V
M
V
M
V
M
V
M
V
M
V
M
tsu(H)
t
h
= 0
Waveform 2. Data and Enable Setup and Hold Times
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74ALS377Octal D flip-flop with enable
1991 Feb 08
6
TEST CIRCUIT AND WAVEFORMS
t
w
90%
V
M
10%
90%
V
M
10%
90%
V
M
10%
90%
V
M
10%
NEGATIVE PULSE
POSITIVE PULSE
t
w
AMP (V)
0.3V
0.3V
t
THL (tf
f
)
INPUT PULSE REQUIREMENTS
Rep.Rate
t
w
t
TLHtTHL
1MHz
500ns
2.0ns 2.0ns
Input Pulse Definition
V
CC
Family
74ALS
D.U.T.
PULSE
GENERATOR
R
L
C
L
R
T
V
IN
V
OUT
Test Circuit for Totem-pole Outputs
DEFINITIONS:
R
L
= Load resistor;
see AC electrical characteristics for value.
CL= Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
R
T
= T ermination resistance should be equal to Z
OUT
of
pulse generators.
t
THL (tf
)
t
TLH (tr
)
t
TLH (tr
)
AMP (V)
Amplitude
3.5V
1.3V
V
M
SC00005
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74ALS377Octal D flip–flop with enable
1991 Feb 08
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DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1
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74ALS377Octal D flip–flop with enable
1991 Feb 08
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SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
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74ALS377Octal D flip–flop with enable
1991 Feb 08
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SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1
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74ALS377Octal D flip–flop with enable
1991 Feb 08
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Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
LIFE SUPPORT APPLICA TIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381
DEFINITIONS
Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Copyright Philips Electronics North America Corporation 1997
All rights reserved. Printed in U.S.A.
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