Datasheet N25S80 Datasheet (Nantronics)

N25S80

8 Megabit Serial Flash Memory with 4Kbytes Uniform Sector
N25S80

FEATURES

Single power supply operation Flexible Architecture with 4KB sectors

- Full voltage range: 2.7-3.6 volt - Sector Erase (4K-bytes)

8 Mbit Serial Flash

- 8 M-bit/1024 K-byte/4096 pages - More than 100K erase/write cycles

- 256 bytes per programmable page - More than 20-year data retention

- Uniform 4K-byte Sectors

- Uniform 32K and 64K-byte Blocks

Standard and Dual

- Standard SPI: CLK, CS#, DI, DO, WP#, software
HOLD# - Enable/Disable protection with WP# pin

- Dual SPI: CLK, CS#, DIO, DO, WP#,
HOLD#

- Fast Read Dual Output instruction - Page program time: 1.8ms typical

- Auto-increment Read capability - Sector erase time: 45ms typical

High performance

- 104MHz clock rate for one data bit

- 85MHz clock rate for two data bits

Low power consumption

- 12 mA typical active current - 8-pin PDIP 300-mil

- 1 uA typical power down current - All Pb-free packages are RoHS compliant

GENERAL DESCRIPTION

The N25S80 is a 8 Megabit (1024K-byte) Serial Flash memory, with advanced write protection
mechanisms. The N25S80 supports the standard Serial Peripheral Interface (SPI), and a high
performance Dual output using SPI pins: Serial Clock, Chip Select, Serial DIO, DO, WP# and
HOLD#. SPI clock frequencies of up to 104MHz are supported allowing equivalent clock rates of
85MHz for Dual Output. The memory can be programmed 1 to 256 bytes at a time, using the Page
Program instruction.

The N25S80 also offers a sophisticated method for protecting individual blocks against erroneous or
malicious program and erase operations. By providing the ability to individually protect and unprotect
blocks, a system can unprotect a specific block to modify its contents while keeping the remaining
blocks of the memory array securely protected. This is useful in applications where program code is
patched or updated on a subroutine or module basis, or in applications where data storage
segments need to be modified without running the risk of errant modifications to the program code
segments.

The N25S80 is designed to allow either single Sector/Block at a time or full chip erase operation.
The N25S80 can be configured to protect part of the memory as the software protected mode. The
device can sustain a minimum of 100K program/erase cycles on each sector or block.

- Block Erase (32K and 64K-bytes)

- Page Program up to 256 bytes

Software and Hardware Write Protection:

- Write Protect all or portion of memory via

High performance program/erase speed

- Block erase time: 450ms typical

- Chip erase time: 7 Seconds typical

Package Options

- 8-pin SOIC 150/208-mil

- 8-pad WSON 6x5-mm

Nantronics Semiconductor, Inc.

1

N25S80

V

1. ORDERING INFORMATION

N 25S XX X X X X X

Green Code

G: Green package

Packaging Type

T:Tube
R:Tape & Reel
Y:Tray

Temperature Range & Lead Free

I: Industriial(-40℃~85℃) with Pb-free package
E: Extended(-25℃~85℃)with Pb-free package

Package Type

H: 208mil S0P8
N: 150mil SOP8
W: 8 contact WSON
D: 8-pin DIP

ersion

A: A Version
B: B Version
C: C Version

Device Density

32: 32Mbit
16:16Mbit
80:8Mbit
40:4Mbit
20:2Mbit
10:1Mbit
05:512Kbit

Base Part Number

N: Nantronics
25S:3V Serial 4Kbyte Uniform-sector Flash

Figure 1, Ordering Information

Nantronics Semiconductor, Inc.

2

N25S80

2. BLOCK DIAGRAM

Figure 2, Block Diagram

3. CONNECTION DIAGRAMS

CS#

DO

WP#

1

2

3

8

7

6

54

VCC

HOLD#

CLK

DIOGND

CS# VCC

DO

WP#

GND

1

2

3

4

Figure 3.1, 8-pin SOP (150/208mil)/ PDIP (300mil) Figure 3.2, 8-Contact 6 x 5 mm WSON

Nantronics Semiconductor, Inc.

3

8

7

6

5

HOLD#

CLK

DIO

N25S80

4. SIGNAL DESCRIPTIONS

Serial Data Input / Output (DIO)

The SPI Serial Data Input/Output (DIO) pin provides a means for instructions, addresses and data to
be serially written to (shifted into) the device. Data is latched on the rising edge of the Serial Clock
(CLK) input pin. The DIO pin is also used as an output pin when the Fast Read Dual Output
instruction is executed.

Serial Data Output (DO)

The SPI Serial Data Output (DO) pin provides a means for data and status to be serially read from
(shifted out of) the device. Data is shifted out on the falling edge of the Serial Clock (CLK) input pin.

Serial Clock (CLK)

The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See
SPI Mode")

Chip Select (CS#)

The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device
is deselected and the Serial Data Output pins are at high impedance.

When deselected, the devices power consumption will be at standby levels unless an internal erase,
program or status register cycle is in progress. When CS# is brought low the device will be selected,
power consumption will increase to active levels and instructions can be written to and data read
from the device. After power-up, CS# must transition from high to low before a new instruction will
be accepted.

HOLD (HOLD#)

The HOLD# pin allows the device to be paused while it is actively selected. When HOLD# is brought
low, while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will
be ignored (don’t care). The HOLD# function can be useful when multiple devices are sharing the
same SPI signals.

Write Protect (WP#)

The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (BP0, BP1and BP2, BP3) bits and Status
Register Protect (SRP) bits, a portion or the entire memory array can be hardware protected.

Table1, Pin Descriptions

Symbol Pin Name

CLK Serial Clock Input

DIO Serial Data Input / Output (Note 1)

DO Serial Data Output

CS# Chip Enable

WP# Write Protect

HOLD# Hold Input

VCC Supply Voltage (2.7-3.6V)

GND Ground

Note 1: DIO output is used for Dual instructions.

Nantronics Semiconductor, Inc.

4

N25S80

5. MEMORY ORGANIZATIONS

The memory is organized as:

- 1,048,576bytes

- Uniform Sector Architecture
16 blocks of 64-Kbyte
256 sectors of 4-Kbyte

- 4,096 pages (256 bytes each)

Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector,
Block or Chip Erasable but not Page Erasable.

xxFF00h xxFFFFh 0FFF00h 0FFFFFh

....

xx F000h xxF0FFh 0F0000h 0F00FFh

xxEF00h xxEFFFh

Sector 15(4KB) Block 15(64KB)

...

..

xxE000h xxE0FFh

xx1F00h xx1FFFh

Sector 14(4KB)

…

08FF00h 08FFFFh

..

080000h 0800FFh

07FF00h 07FFFFh

..

070000h 0700FFh

Block 8(64KB)

Block 7(64KB)

...

..

xx1000h xx10FFh
xx0F00h xx0FFFh 00FF00h 00FFFFh

Sector 1(4KB)

....

xx0000h xx00FFh 000000h 0000FFh

Nantronics Semiconductor, Inc.

Sector 0(4KB)

Figure 4, Memory Organization

5

Block 0(64KB)

N25S80

6. FUNCTION DESCRIPTION

SPI Modes

The N25S80 are accessed through an SPI compatible bus consisting of four signals: Serial Clock
(CLK), Chip Select (CS#), Serial Data Input / Output (DIO) and Serial Data Output (DO). Both SPI
bus operation Modes 0 (0, 0) and 3 (1, 1) are supported. The primary difference between Mode 0
and Mode 3, as shown in Figure 5, concerns the normal state of the CLK signal when the SPI bus
master is in standby and data is not being transferred to the Serial Flash. For Mode 0 the CLK is
normally low. For Mode 3 the CLK is normally high. In either case data input on the DIO pin is
sampled on the rising edge of the CLK. Data on the DO and DIO pins are clocked out on the falling
edge of CLK.

Figure 5, SPI Modes

Dual Output SPI

The N25S80 supports Dual Output Operation when using the “Fast Read with Dual Output” (3B hex)
instruction. This feature allows data to be transferred from the Serial Flash at twice the rate possible
with the standard SPI. This instruction is ideal for quickly downloading code from Flash to RAM upon
Power-up (Code-shadowing) or for applications that cache code-segments to RAM for execution.
The Dual Output feature simply allows the SPI input pin to also serve as an output during this
instruction. All other operations use the standard SPI interface with single signal.

Hold Function

The /HOLD signal allows the N25S80 operation to be paused while it is actively selected (when CS#
is low). The /HOLD function may be useful in cases where the SPI data and clock signals are shared
with other devices. For example, consider if the page buffer was only partially written when a priority
interrupt requires use of the SPI bus. In this case the /HOLD function can save the state of the
instruction and the data in the buffer so programming can resume where it left off once the bus is
available again.
To initiate a /HOLD condition, the device must be selected with CS# low. A /HOLD condition will
activate on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not
already low the /HOLD condition will activate after the next falling edge of CLK. The /HOLD condition
will terminate on the rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is
not already low the /HOLD condition will terminate after the next falling edge of CLK.
During a /HOLD condition, the Serial Data Output (DO) is high impedance, and Serial Data
Input/Output (DIO) and Serial Clock (CLK) are ignored. The Chip Select (CS#) signal should be kept
active (low) for the full duration of the /HOLD operation to avoid resetting the internal logic state of
the device.

Figure 6, Hold Condition Waveform

Nantronics Semiconductor, Inc.

6

N25S80

Status Register

The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions.

Table 2, Status Register Bit Locations

z BUSY is a read only bit in the status register (R0) that is set to a 1 state when the device is

executing a Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register
instruction. During this time the device will ignore further instructions except for the Read Status
Register instruction (see tW, tPP, tSE, tBE, and tCE in AC Characteristics). When the program,
erase or write status register instruction has completed, the BUSY bit will be cleared to a 0
state indicating the device is ready for further instructions.

z Write Enable Latch (WEL) is a read only bit in the status register (R1) that is set to a 1 after

executing a Write Enable Instruction. The WEL status bit is cleared to a 0 when the device is
write disabled. A write disable state occurs upon power-up or after any of the following
instructions: Write Disable, Page Program, Sector Erase, Block Erase, Chip Erase and Write
Status Register.

z Block Protect Bits (BP3, BP2, BP1, BP0) are non-volatile read/write bits in the status register

(R5, R4, R3 and R2) that provide Write Protection control and status. Block Protect bits can be
set using the Write Status Register Instruction (see tW in AC characteristics). All, none or a
portion of the memory array can be protected from Program and Erase instructions (see Status
Register Memory Protection table). The factory default setting for the Block Protection Bits is 0,
none of the array protected. The Block Protect bits can not be written to if the Status Register
Protect (SRP) bit is set to 1 and the Write Protect (/WP) pin is low.

z Reserved Bits (REV), Status register bit location R6 is reserved for future use. Current devices

will read 0 for this bit location. It is recommended to mask out the reserved bit when testing the
Status Register. Doing this will ensure compatibility with future devices.

z The Status Register Protect (SRP) bit is a non-volatile read/write bit in status register (R7)

that can be used in conjunction with the Write Protect (/WP) pin to disable writes to status
register. When the SRP bit is set to a 0 state (factory default) the /WP pin has no control over
status register. When the SRP pin is set to a 1, the Write Status Register instruction is locked
out while the /WP pin is low. When the /WP pin is high the Write Status Register instruction is
allowed.

R7 R6 R5 R4 R3 R2 R1 R0

SRP REV BP3 BP2 BP1 BP0 WEL BUSY

Write Protection

Applications that use non-volatile memory must take into consideration the possibility of noise and
other adverse system conditions that may compromise data integrity. To address this concern the

N25S80 provide the following data protection mechanisms:

z Power-On Reset and an internal timer (t

changes while the power supply is outside the operating specification.

z Program, Erase and Write Status Register instructions are checked that they consist of a

number of clock pulses that is a multiple of eight, before they are accepted for execution.

z All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set

the Write Enable Latch (WEL) bit . This bit is returned to its reset state by the following events:

- Power-up

- Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction
completion or Page Program (PP) instruction completion or Sector Erase (SE) instruction
completion or Block Erase (BE) instruction completion or Chip Erase (CE) instruction
completion

z The Block Protect (BP3, BP2, BP1, and BP0) bits allow part of the memory to be configured as

read-only. This is the Software Protected Mode (SPM).

z The Write Protect (WP#) signal allows the Block Protect (BP3, BP2, BP1, BP0) bits and Status

Register Protect (SRP) bit to be protected. This is the Hardware Protected Mode (HPM).

z In addition to the low power consumption feature, the Deep Power-down mode offers extra

software protection from inadvertent Write, Program and Erase instructions, as all instructions
are ignored except one particular instruction (the Release from Deep Power-down instruction).

) can provide protection against inadvertent

PUW

Nantronics Semiconductor, Inc.

7

N25S80

Table 3, Protected Area Sizes Block Organization

Status Bit

BP3

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

Page Programming

To program one data byte, two instructions are required: Write Enable (WREN), which is one byte,
and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the
internal Program cycle (of duration t
allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie
in consecutive addresses on the same page of memory.

Sector Erase, Block Erase and Chip Erase

The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied,
the bytes of memory need to have been erased to all 1s (FFh). This can be achieved a sector at a
time, using the Sector Erase (SE) instruction, a block at a time using the Block Erase (BE)
instruction or throughout the entire memory, using the Chip Erase (CE) instruction. This starts an
internal Erase cycle (of duration t
Enable (WREN) instruction.

Polling During a Write, Program or Erase Cycle

A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE, BE
or CE ) can be achieved by not waiting for the worst case delay (t
Progress (WIP) bit is provided in the Status Register so that the application program can monitor its
value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete.

Active Power, Stand-by Power and Deep Power-Down Modes

When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip
Select (CS#) is High, the device is disabled, but could remain in the Active Power mode until all
internal cycles have completed (Program, Erase, Write Status Register). The device then goes into
the Standby Power mode. The device consumption drops to I

The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down
Mode (DP) instruction) is executed. The device consumption drops further to I
remains in this mode until another specific instruction (the Release from Deep Power-down Mode
and Read Device ID (RDI) instruction) is executed.

All other instructions are ignored while the device is in the Deep Power-down mode. This can be
used as an extra software protection mechanism, when the device is not in active use, to protect the
device from inadvertent Write, Program or Erase instructions.

BP2 BP1 BP0

PP). To spread this overhead, the Page Program (PP) instruction

SE tBE or tCE). The Erase instruction must be preceded by a Write

Protect Blocks
0（None）
1（1Block,Block 15)
2（2blocks,block14th~15th)
3（4blocks,block12

th~15th)

4（8blocks,block8th~15th)
5（16blocks,all)
6（16blocks,all)
7（16blocks,all)
8（none)
9 （254 sectors,sector 0th~253th)
10（252 sectors,sector 0th~251th)
11（248 sectors,sector 0th~247th)
12（240 sectors,sector 0th~239th)
13（224 sectors,sector 0th~223th)
14（192 sectors,sector 0th~191th)
15（16

blocks,

CC1.

all)

W, tPP, tSE, tBE or tCE). The Write In

CC2. The device

Nantronics Semiconductor, Inc.

8

N25S80

7 INSTRUCTIONS

The instruction set of the N25S80 consists of fifteen basic instructions that are fully controlled
through the SPI bus (see Instruction Set table). Instructions are initiated with the falling edge of Chip
Select (CS#). The first byte of data clocked into the DIO input provides the instruction code. Data on
the DIO input is sampled on the rising edge of clock with most significant bit (MSB) first.

Instructions vary in length from a single byte to several bytes and may be followed by address bytes,
data bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed
with the rising edge of edge CS#. Clock relative timing diagrams for each instruction are included in
figures 7 through 22. All read instructions can be completed after any clocked bit. However, all
instructions that Write, Program or Erase must complete on a byte boundary (CS driven high after a
full 8-bits have been clocked) otherwise the instruction will be terminated. This feature further
protects the device from inadvertent writes. Additionally, while the memory is being programmed or
erased, or when the Status Register is being written, all instructions except for Read Status Register
will be ignored until the program or erase cycle has completed.

Table 4, Instruction Set

INSTRUCTION
NAME

Write Enable 06h
write Disable 04h

Read Status
Register
Write Status
Register

Read Data 03h A23-A16 A15-A8 A7-A0 (D7-D0) (Next byte) continuous

Fast Read 0Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0)

Fast Read
Dual Output

Page Program 02h A23-A16 A15-A8 A7-A0 (D7-D0) (Next byte)

Block
Erase(64KB)
Block
Erase(32KB)
Sector
Erase(4KB)
Chip Erase C7h/60h

Power-down B9h

Release
Power-down
/Device ID

Manufacturer
/Device ID

JEDEC ID 9Fh

(3)

BYTE1

CODE

05h (S7-S0)

01h S7-S0

3Bh A23-A16 A15-A8 A7-A0 dummy

D8h A23-A16 A15-A8 A7-A0

52h A23-A16 A15-A8 A7-A0

20h A23-A16 A15-A8 A7-A0

ABh dummy dummy dummy

90h dummy dummy 00h (M7-M0) (ID7-ID0)

BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 N-BYTES

(1)

(Next byte)
continuous

(M7-M0)

manufacture

r

(ID15-ID8)

Memory

Type

(ID7-ID0)
Capacity

I/O=
(D6,D4,D2,D

0)
O=
(D7,D5,D3,D

1)

(ID7-

(4)

ID0)

(One byte

per 4

clocks,

continuous

Up to 256

bytes

(2)

)

Notes:

1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate
data being read from the device on the DO pin.

2. The Status Register contents will repeat continuously until CS# terminates the instruction.

3. See Manufacturer and Device Identification table for Device ID information.

4. The Device ID will repeat continuously until CS# terminates the instruction.

Nantronics Semiconductor, Inc.

9

N25S80

Table 5, Manufacturer and Device Identification

OP Code (M7-M0) (ID15-ID0) (ID7-ID0)

ABh

90h D5h

9Fh D5h 3014h

Write Enable (06h)

The Write Enable instruction (Figure 7) sets the Write Enable Latch (WEL) bit in the Status Register
to a 1. The WEL bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip
Erase and Write Status Register instruction. The Write Enable instruction is entered by driving CS#
low, shifting the instruction code “06h” into the Data Input (DI) pin on the rising edge of CLK, and
then driving CS# high.

13h

13h

Figure 7, Write Enable Instruction Sequence Diagram

Write Disable (04h)

The Write Disable instruction (Figure 8) resets the Write Enable Latch (WEL) bit in the Status
Register to a 0. The Write Disable instruction is entered by driving CS# low, shifting the instruction
code “04h” into the DIO pin and then driving CS# high. Note that the WEL bit is automatically reset
after Power-up and upon completion of the Write Status Register, Page Program, Sector Erase,
Block Erase and Chip Erase instructions.

Figure 8, Write Disable Instruction Sequence Diagram

Nantronics Semiconductor, Inc.

10

N25S80

Read Status Register (05h)

The Read Status Register instruction allows the 8-bit Status Register to be read. The instruction is
entered by driving CS# low and shifting the instruction code “05h” into the DIO pin on the rising edge
of CLK. The status register bits are then shifted out on the DO pin at the falling edge of CLK with
most significant bit (MSB) first as shown in figure 9. The Status Register bits are shown in figure 3
and include the BUSY, WEL, BP3-BP0, TB and SRP bits (see description of the Status Register
earlier in this datasheet).

The Read Status Register instruction may be used at any time, even while a Program, Erase or
Write Status Register cycle is in progress. This allows the BUSY status bit to be checked to
determine when the cycle is complete and if the device can accept another instruction. The Status
Register can be read continuously, as shown in Figure 9. The instruction is completed by driving
CS# high.

Figure 9, Read Status Register Instruction Sequence Diagram

Write Status Register (01h)

The Write Status Register instruction allows the Status Register to be written. A Write Enable
instruction must previously have been executed for the device to accept the Write Status Register
Instruction (Status Register bit WEL must equal 1). Once write enabled, the instruction is entered by
driving CS# low, sending the instruction code “01h”, and then writing the status register data byte as
illustrated in figure 10. The Status Register bits are shown in figure 3 and described earlier in this
datasheet.

Only non-volatile Status Register bits SRP, BP3, BP2, BP1 and BP0 (bits 7, 5, 4, 3 and 2) can be
written to. All other Status Register bit locations are read-only and will not be affected by the Write
Status Register instruction.

The CS# pin must be driven high after the eighth bit of the last byte has been latched. If this is not
done the Write Status Register instruction will not be executed. After CS# is driven high, the self­timed Write Status Register cycle will commence for a time duration of tW (See AC Characteristics).
While the Write Status Register cycle is in progress, the Read Status Register instruction may still
accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register
cycle and a 0 when the cycle is finished and ready to accept other instructions again. After the Write
Register cycle has finished the Write Enable Latch (WEL) bit in the Status Register will be cleared to

0.

The Write Status Register instruction allows the Block Protect bits (BP3, BP2, BP1 and BP0) to be
set for protecting all, a portion, or none of the memory from erase and program instructions.
Protected areas become read-only (see Status Register Memory Protection table). The Write Status
Register instruction also allows the Status Register Protect bit (SRP) to be set. This bit is used in
conjunction with the Write Protect (/WP) pin to disable writes to the status register. When the SRP
bit is set to a 0 state (factory default) the /WP pin has no control over the status register. When the
SRP pin is set to a 1, the Write Status Register instruction is locked out while the /WP pin is low.
When the /WP pin is high the Write Status Register instruction is allowed.

Nantronics Semiconductor, Inc.

11

N25S80

Figure 10, Write Status Register Instruction Sequence Diagram

Read Data (Read) (03h)

The Read Data instruction allows one more data bytes to be sequentially read from the memory.
The instruction is initiated by driving the CS# pin low and then shifting the instruction code “03h”
followed by a 24-bit address (A23-A0) into the DIO pin. The code and address bits are latched on
the rising edge of the CLK pin. After the address is received, the data byte of the addressed memory
location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB)
first. The address is automatically incremented to the next higher address after each byte of data is
shifted out allowing for a continuous stream of data. This means that the entire memory can be
accessed with a single instruction as long as the clock continues. The instruction is completed by
driving CS# high.

The Read Data instruction sequence is shown in figure 11. If a Read Data instruction is issued while
an Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have
any effects on the current cycle. The Read Data instruction allows clock rates from D.C. to a
maximum of fR (see AC Electrical Characteristics).

Figure 11. Read Data Instruction Sequence Diagram

Nantronics Semiconductor, Inc.

12

N25S80

Fast Read (0Bh)

The Fast Read instruction is similar to the Read Data instruction except that it can operate at the
highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding
eight “dummy” clocks after the 24-bit address as shown in figure 12. The dummy clocks allow the
devices internal circuits additional time for setting up the initial address. During the dummy clocks
the data value on the DIO pin is a “don’t care”.

Figure 12, Fast Read Instruction Sequence Diagram

Fast Read Dual Output (3Bh)

The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction
except that data is output on two pins, DO and DIO, instead of just DO. This allows data to be
transferred from the N25S80 at twice the rate of standard SPI devices. The Fast Read Dual Output
instruction is ideal for quickly downloading code from Flash to RAM upon power-up or for
applications that cache code-segments to RAM for execution.

Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the
highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding
eight “dummy” clocks after the 24-bit address as shown in figure 13. The dummy clocks allow the
device's internal circuits additional time for setting up the initial address. The input data during the
dummy clocks is “don’t care”. However, the DIO pin should be high-impedance prior to the falling
edge of the first data out clock.

Nantronics Semiconductor, Inc.

13

N25S80

Figure 13, Fast Read Dual Output Instruction Sequence Diagram

Page Program (PP) (02h)

The Page Program instruction allows up to 256 bytes of data to be programmed at previously
erased to all 1s (FFh) memory locations. A Write Enable instruction must be executed before the
device will accept the Page Program Instruction (Status Register bit WEL must equal 1). The
instruction is initiated by driving the CS# pin low then shifting the instruction code “02h” followed by
a 24-bit address (A23-A0) and at least one data byte, into the DIO pin. The CS# pin must be held
low for the entire length of the instruction while data is being sent to the device. The Page Program
instruction sequence is shown in figure 14.

If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address
bits) should be set to 0. If the last address byte is not zero, and the number of clocks exceed the
remaining page length, the addressing will wrap to the beginning of the page. In some cases, less
than 256 bytes (a partial page) can be programmed without having any effect on other bytes within
the same page. One condition to perform a partial page program is that the number of clocks can
not exceed the remaining page length. If more than 256 bytes are sent to the device the addressing
will wrap to the beginning of the page and overwrite previously sent data.

As with the write and erase instructions, the CS# pin must be driven high after the eighth bit of the
last byte has been latched. If this is not done the Page Program instruction will not be executed.
After CS# is driven high, the self-timed Page Program instruction will commence for a time duration
of tpp (See AC Characteristics). While the Page Program cycle is in progress, the Read Status
Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a
1 during the Page Program cycle and becomes a 0 when the cycle is finished and the device is
ready to accept other instructions again. After the Page Program cycle has finished the Write Enable
Latch (WEL) bit in the Status Register is cleared to 0. The Page Program instruction will not be
executed if the addressed page is protected by the Block Protect (BP3, BP2, BP1, and BP0) bits
(see Status Register Memory Protection table).

Nantronics Semiconductor, Inc.

14

N25S80

Figure 14, Page Program Instruction Sequence Diagram

Sector Erase (SE) (20h)

The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state
of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector
Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the
CS# pin low and shifting the instruction code “20h” followed a 24-bit sector address (A23-A0) (see
Figure 2). The Sector Erase instruction sequence is shown in figure 15.

The CS# pin must be driven high after the eighth bit of the last byte has been latched. If this is not
done the Sector Erase instruction will not be executed. After CS# is driven high, the self-timed
Sector Erase instruction will commence for a time duration of tSE (See AC Characteristics). While
the Sector Erase cycle is in progress, the Read Status Register instruction may still be accessed for
checking the status of the BUSY bit. The BUSY bit is a 1 during the Sector Erase cycle and
becomes a 0 when the cycle is finished and the device is ready to accept other instructions again.
After the Sector Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is
cleared to 0. The Sector Erase instruction will not be executed if the addressed page is protected by
the Block Protect (BP3, BP2, BP1, and BP0) bits (see Status Register Memory Protection table).

Figure 15, Sector Erase Instruction Sequence Diagram

Nantronics Semiconductor, Inc.

15

N25S80

Block Erase (BE) (D8h)

The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state
of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block
Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the
CS# pin low and shifting the instruction code “D8h” followed a 24-bit block address (A23-A0) (see
Figure 2). The Block Erase instruction sequence is shown in figure 16.

The CS# pin must be driven high after the eighth bit of the last byte has been latched. If this is not
done the Block Erase instruction will not be executed. After CS# is driven high, the self-timed Block
Erase instruction will commence for a time duration of tBE (See AC Characteristics). While the Block
Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking
the status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when
the cycle is finished and the device is ready to accept other instructions again. After the Block Erase
cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block
Erase instruction will not be executed if the addressed page is protected by the Block Protect (BP3,
BP2, BP1, and BP0) bits (see Status Register Memory Protection table).

Figure 16. Block Erase Instruction Sequence Diagram

Chip Erase (CE) (C7h)

The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A
Write Enable instruction must be executed before the device will accept the Chip Erase Instruction
(Status Register bit WEL must equal 1). The instruction is initiated by driving the CS# pin low and
shifting the instruction code “C7h”. The Chip Erase instruction sequence is shown in figure 17.

The CS# pin must be driven high after the eighth bit has been latched. If this is not done the Chip
Erase instruction will not be executed. After CS# is driven high, the self-timed Chip Erase instruction
will commence for a time duration of tCE (See AC Characteristics). While the Chip Erase cycle is in
progress, the Read Status Register instruction may still be accessed to check the status of the
BUSY bit. The BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the
device is ready to accept other instructions again. After the Chip Erase cycle has finished the Write
Enable Latch (WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction will not be
executed if any page is protected by the Block Protect (BP3,BP2, BP1, and BP0) bits (see Status
Register Memory Protection table).

Nantronics Semiconductor, Inc.

16

N25S80

Deep Power-down (DP) (B9h)

Although the standby current during normal operation is relatively low, standby current can be
further reduced with the Power-down instruction. The lower power consumption makes the Power­down instruction especially useful for battery powered applications (See ICC1 and ICC2 in AC
Characteristics). The instruction is initiated by driving the CS# pin low and shifting the instruction
code “B9h” as shown in figure 18.

The CS# pin must be driven high after the eighth bit has been latched. If this is not done the Power­down instruction will not be executed. After CS# is driven high, the power-down state will enter
within the time duration of tDP (See AC Characteristics). While in the power-down state only the
Release from Power-down / Device ID instruction, which restores the device to normal operation, will
be recognized. All other instructions are ignored. This includes the Read Status Register instruction,
which is always available during normal operation. Ignoring all but one instruction makes the Power
Down state a useful condition for securing maximum write protection. The device always powers-up
in the normal operation with the standby current of ICC1.

Figure 17, Chip Erase Instruction Sequence Diagram

Figure 18, Deep Power-down Instruction Sequence Diagram

Release Power-down / Device ID (ABh)

The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used
to release the device from the power-down state, obtain the devices electronic identification (ID)
number or do both.

When used only to release the device from the power-down state, the instruction is issued by driving
the CS# pin low, shifting the instruction code “ABh” and driving CS# high as shown in figure 19.
After the time duration of tRES1 (See AC Characteristics) the device will resume normal operation
and other instructions will be accepted. The CS# pin must remain high during the tRES1 time
duration.
When used only to obtain the Device ID while not in the power-down state, the instruction is initiated
by driving the CS# pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The
Device ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as
shown in figure 20. The Device ID value for the N25S80 is listed in Manufacturer and Device

Nantronics Semiconductor, Inc.

17

N25S80

Identification table. The Device ID can be read continuously. The instruction is completed by driving
CS# high.

When used to release the device from the power-down state and obtain the Device ID, the
instruction is the same as previously described, and shown in figure 20, except that after CS# is
driven high it must remain high for a time duration of tRES2 (See AC Characteristics). After this time
duration the device will resume normal operation and other instructions will be accepted. If the
Release from Power-down / Device ID instruction is issued while an Erase, Program or Write cycle
is in process (when BUSY equals 1) the instruction is ignored and will not have any effects on the
current cycle.

Figure 19, Release Power-down Instruction Sequence

Figure 20, Release Power-down / Device ID Instruction Sequence Diagram

Read Manufacturer / Device ID (90h)

The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down
/Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific
device ID.

The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down /
Device ID instruction. The instruction is initiated by driving the CS# pin low and shifting the
instruction code “90h” followed by a 24-bit address (A23-A0) of 000000h. After which, the
Manufacturer ID for Nantronics (D5h) and the Device ID are shifted out on the falling edge of CLK
with most significant bit (MSB) first as shown in Figure 21. The Device ID values for the N25S80 are
listed in Table 5. If the 24-bit address is initially set to 000001h the Device ID will be read first.

Nantronics Semiconductor, Inc.

18

N25S80

Figure 21, Read Manufacturer / Device ID Diagram

Read Identification (RDID) (9Fh)

For compatibility reasons, the N25S80 provides several instructions to electronically determine the
identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for
SPI compatible serial memories that was adopted in 2003.

The instruction is initiated by driving the CS# pin low and shifting the instruction code “9Fh”. The
JEDEC assigned Manufacturer ID byte for Nantronics (D5h) and two Device ID bytes, Memory Type
(ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling edge of CLK with most
significant bit (MSB) first as shown in figure 22. For memory type and capacity values refer to
Manufacturer and Device Identification table.

Nantronics Semiconductor, Inc.

19

CS#

N25S80

CLK

DIO

DO

Mode3
Mode0

01 1514

Instruction(9FH)

High Impedance

5432

6

Manufacturer ID

7 6 5 4

*

CS#

16 17 313029282726252423

CLK

DIO

Memory Type ID15-ID8

DO

*=MSB

7 6 5 4

*

Figure 22, Read JEDEC ID instruction Sequence Diagram

21201918

22

3 2 1 0

Capacity ID7-ID0

7 6 5 4

*

121110987

13

3 2 1 0

3 2 1 0

Mode3
Mode0

Nantronics Semiconductor, Inc.

20

N25S80

8 ELECTRICAL CHARACTERISTICS

Power-up Timing

Vcc

Vcc(max)

Program,Erase and Write Instruction are Igored

/CS Must Track Vcc

Vcc(min)

V

tVSL

Reset

Stast

WI

tPUW

Read Instructions

Allowed

Device is Fully

Accessible

Time

Figure 23, Power-up Timing

Table 6, Power-up Timing

SYMBOLPARAMETER UNIT

tPUW

tVSL

VWI

(1)

(1)

Vcc(min) to CS# Low

Tim e Dela y Befo re Write Instru cti on

Write Inhibit Threshold Voltage

Note:

1.The parameters are characterized only.

2. VCC (max.) is 3.6V and VCC (min.) is 2.7V

Absolute Maximum Ratings

Stresses above the values so mentioned above may cause permanent damage to the device. These
values are for a stress rating only and do not imply that the device should be operated at conditions
up to or above these values.

TYPE

MIN MAX

10 μs

(1)

110ms

12V

Nantronics Semiconductor, Inc.

21

N25S80

Table 7, Absolute Maximum Ratings

PARAMETERS SYMBOL CONDITIONS RANGE UNIT

Supply Voltage VCC -0.6 to +4.0 V

Voltage applied on any pin V

Transient Voltage on any Pin V

Storage Temperature T

Lead Temprature T

Electrostatic Discharge Voltage V

Notes:

1. Specification for N25S80 is preliminary. See preliminary designation at the end of this document.

2. This device has been designed and tested for the specified operation ranges. Proper operation outside
of these levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability.
Exposure beyond absolute maximum ratings may cause permanent damage.

3. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and
the European directive on restrictions on hazardous substances (RoHS) 2002/95/EU.

4. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 ohms, R2=500 ohms).

IO

IOT

STG

LEAD

ESD

Relative to Ground -0.6 to VCC+0.4 V

<20ns Transient Relative

to Grou nd

Human Body Model

-2.0 to VCC+2.0 V

-65 to +150

See Note

(4)

-2000 to +2000 V

(3)

Recommended Operating Ranges

Table 8, Recommended Operating Ranges

PARAMETER SYMBOL CONDITIONS

Supply Voltage VCC FR=104MHz,fR=50MHz 2.7 3.6 V

SPEC

MIN MAX

UNIT

℃

℃

Ambient Temperature,
Operating

Notes: 1. Recommended Operating Ranges define those limits between which the functionality of the
device is guaranteed.

TA Industrial -40 +85 ℃

Nantronics Semiconductor, Inc.

22

DC Characteristics

N25S80

Table 9. DC Characteristics

SYMBOL PARAMETER CONDITIONS

CIN(1) Input Capacitance VIN = 0V(2) 6 pF

Cout(1) Output Capacitance VOUT = 0V(2) 8 pF

ILI Input Leakage ±2 μA

ILO I/O Leakage ±2 μA

ICC1 Standby Current

ICC2 Power-down Current

ICC3

ICC3

ICC4

ICC5

ICC6

ICC7 Current Chip Erase CS# = VCC 20 25 mA

VIL Input Low Voltage –0.5 VCC x 0.3 V

VIH Input High Voltage VCC x0.7 VCC +0.4 V
VOL Output Low Voltage IOL = 1.6 mA 0.4 V
VOH Output High Voltage IOH = –100 μA VCC –0.2 V

Current Read Data /
Dual Output Read
33MHz(2)
Current Read Data /
Dual Output Read
100MHz(2)
Current Page
Program
Current Write Status
Register
Current Sector/Block
Erase

CS# = VCC, VIN
= GND or VCC
CS# = VCC, VIN
= GND or VCC

C = 0.1 VCC / 0.9
VCC DO = Open

C = 0.1 VCC / 0.9
VCC DO = Open

CS# = VCC 15 20 mA

CS# = VCC 10 18 mA

CS# = VCC 20 25 mA

MIN TYP MAX

20 μA

20 μA

12/10 15/18 mA

25 mA

SPEC

UNIT

Notes:

1. Tested on sample basis and specified through design and characterization data. TA=25° C, VCC 3V.

2. Checker Board Pattern.

AC Measurement Conditions

Table 10, AC Measurement Conditions

Symbol PARAMETER Min. Max. Unit

CL Load Capacitance 30 pF
TR, TF Input Rise and Fall Times 5 ns
VIN Input Pulse Voltages 0.2VCC to 0.8VCC V
VtIN Input Timing Reference Voltages 0.3VCC to 0.7VCC V
VtON Output Timing Reference Voltages 0.5 VCC to 0.5 VCC V

Figure 24, AC Measurement I/O Waveform

Nantronics Semiconductor, Inc.

23

N25S80

AC Electrical Characteristics

Table 11, AC Electrical Characteristics

SYMBOL ALT Parameter

Clock frequency
For all instructions, except Read
Data (03h) and Dual output(3bh)

FR fC

fR

tCLH, tCLL(1)

tCRLH, tCRLL(1)

tCLCH(2) Clock Rise Time peak to peak 0.1 V/ns
tCHCL(2) Clock Fall Time peak to peak 0.1 V/ns

tSLCH tCSS

tCHSL

tDVCH tDSU Data In Setup Time 2 ns
tCHDX tDH Data In Hold Time 5 ns

tCHSH

tSHCH

tSHSL tCSH

tSHQZ(2) tDIS Output Disable Time 6 ns

tCLQV tV

tCLQX tHO Output Hold Time 0 ns

tHLCH

tCHHH

tHHCH

tCHHL

tHHQX(2) tLZ /HOLD to Output Low-Z 7 ns
tHLQZ(2) tHZ /HOLD to Output High-Z 12 ns

tWHSL(3)

tSHWL(3)

tDP(2) CS# High to Power-down Mode 3 us

tRES1(2)

tRES2(2)

tW Write Status Register Time 3 5 ms
tBP1 Byte Program Time (First Byte) (4) 30 50 us

tBP2

tPP Page Program Time 1.8 5 ms
tSE Sector Erase Time (4KB) 45 200 ms
tBE Block Erase Time (64KB) 0.45 1 s
tBE2 Half Block erase 0.25 0.5 s
tCE Chip Erase Time 7 15 s

2.7V-3.6V VCC & Industrial
Temperature
Clock frequency
For dual output(3bh) 2.7V-3.6V
VCC & Industrial Temperature
Clock freq. Read Data instruction
(03h)
Clock High, Low Time for all
instructions except Read Data
(03h)
Clock High, Low Time for Read
Data (03h) instruction

CS# Active Setup Time relative to
CLK
CS# Not Active Hold Time relative
to CLK

CS# Active Hold Time relative to
CLK
CS# Not Active Setup Time
relative to CLK
CS# Deselect Time (for Array
Read ÆArray Read / Erase or
Program Æ Read Status Register)

Clock Low to Output Valid 2.7V-

3.6V / 3.0V-3.6V

/HOLD Active Setup Time relative
to CLK
/HOLD Active Hold Time relative
to CLK
/HOLD Not Active Setup Time
relative to CLK
/HOLD Not Active Hold Time
relative to CLK

Write Protect Setup Time Before
CS# Low
Write Protect Hold Time After CS#
High

CS# High to Standby Mode
without Electronic Signature Read
CS# High to Standby Mode with
Electronic Signature Read

Additional Byte Program Time
(After First Byte) (4)

MIN TYP MAX

D.C. 104 MHz

D.C. 50 MHz

4 ns

4 ns

5 ns

5 ns

5 ns

5 ns

50/100 ns

5 ns

5 ns

5 ns

5 ns

20 ns

100 ns

SPEC

85

9 12 ns

3 us

1.8 us

6 12 us

UNIT

Notes:

1, Clock high + Clock low must be less than or equal to 1/fC.
2, Value guaranteed by design and/or characterization, not 100% tested in production.
3, Only applicable as a constraint for a Write Status Register instruction when Sector Protect Bit is set to 1.
4, For multiple bytes after first byte within a page, tBPN = tBP1 + tBP2 * N (typical) and tBPN = tBP1 +

Nantronics Semiconductor, Inc.

24

N25S80

tBP2 * N (max), where N = number of bytes programmed.

Figure 25, Serial Output Timing

Figure 26, Input Timing

Figure 27, Hold Timing

Nantronics Semiconductor, Inc.

25

N25S80

9 PACKAGE MECHANICAL

8-Pin SOIC 150-mil

Nantronics Semiconductor, Inc.

26

8-Pin SOIC 208-mil

N25S80

Nantronics Semiconductor, Inc.

27

N25S80

8-Contact WSON (6x5mm)

Nantronics Semiconductor, Inc.

28

8-Pin PDIP 300-mil

N25S80

Nantronics Semiconductor, Inc.

29

N25S80

REVISION LIST

Version No. Description Date

A Initial Release 2009/05/12
B Adding PDIP package 2010/08/20

Nantronics Semiconductor, Inc.

30