Page 1
Doc No.: 44085409
A
Issued Date: Jul. 10, 2008
Model No.: N184H4 - L02
Preliminary
TFT LCD Preliminary Specification
MODEL NO.: N184H4 - L02
Customer :
pproved by :
Note :
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18:57:12 CST
記錄 工作 審核 角色 投票
2008-07-28
PMMD III
Director
sue_liu(劉
1 / 29
素娟)
Director
(deputy)
Accept
Version 1.0
Page 2
- CONTENTS -
REVISION HISTORY
1. GENERAL DESCRIPTION
1.1 OVERVIEW
1.2 FEATURES
1.3 APPLICATION
1.4 GENERAL SPECIFICATIONS
1.5 MECHANICAL SPECIFICATIONS
2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
2.2 ELECTRICAL ABSOLUTE RATINGS
2.2.1 TFT LCD MODULE
2.2.2 BACKLIGHT UNIT
3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE
3.2 BACKLIGHT UNIT
4. BLOCK DIAGRAM
4.1 TFT LCD MODULE
4.2 BACKLIGHT UNIT
5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD MODULE
5.2 BACKLIGHT UNIT
5.3 TIMING DIAGRAM OF LVDS INPUT SIGNAL
5.4 COLOR DATA INPUT ASSIGNMENT
5.5 EDID CODE DATA STRUCTURE
6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
6.2 POWER ON/OFF SEQUENCE
7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
7.2 OPTICAL SPECIFICATIONS
8. PRECAUTIONS
8.1 ASSEMBL Y AND HANDLING PRECAUTIONS
8.2 SAFETY PRECAUTIONS
9. PACKING
9.1 CARTON
9.2 PALLET
10. DEFINITION OF LABELS
10
.1 CMO MODULE LABEL
10.2 CMO CARTON LABEL
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Doc No.: 44085409
Issued Date: Jul. 10, 2008
Model No.: N184H4 - L02
Preliminary
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Version 1.0
Page 3
Doc No.: 44085409
Issued Date: Jul. 10, 2008
Model No.: N184H4 - L02
Preliminary
Version Date
May. 14, ‘08
July. 10, ‘08
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Ver. 0.0
Ver. 1.0
Page
(New)
All
All
REVISION HISTORY
Section Description
All
Tentative Specification was first issued.
All
Preliminary Specification was first issued .
3 / 29
Version 1.0
Page 4
Doc No.: 44085409
Issued Date: Jul. 10, 2008
Model No.: N184H4 - L02
Preliminary
1. GENERAL DESCRIPTION
1.1 OVERVIEW
N184H4 - L02 is a 18.4” TFT Liquid Crystal Display module with Duo CCFL Backlight unit and 30 pins
LVDS interface. This module supports 1920 x 1080 Full HD mode and can display 262,144 colors. The
optimum viewing angle is at 6 o’clock direction. The inverter module for Backlight is not built in.
1.2 FEATURES
- Thin and High Brightness
- Full HD (1920 x 1080 pixels) resolution
- DE only mode
- 3.3V LVDS (Low Voltage Differential Signaling) interface with 2 pixel/clock
- 2CCFL
1.3 APPLICA TION
- TFT LCD Notebook
1.4 GENERAL SPECIFICATI0NS
Item Specification Unit Note
Active Area 408.96 (H) x 230.04 (V) (18.4” diagonal) mm
Bezel Opening Area 413.11(H) x 234.24(V) mm
Driver Element a-si TFT active matrix - Pixel Number 1920 x R.G.B. x 1080 pixel Pixel Pitch 0.213 (H) x 0.213(V) mm Pixel Arrange ment RGB vertical stripe - Display Colors 262,144 color Transmissive Mode Normally white - Surface Treat ment Hard coating (3H), Glare Type - -
1.5 MECHANICAL SPECIFICATIONS
Module Size
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
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Item Min. Typ. Max. Unit Note
Horizontal (H) 422 422.5 423 mm
Vertical (V) 247.5 248 248.5 mm
Depth (D) 6.2 6.5 mm
Weight 765 780 g -
(1)
(1)
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Version 1.0
Page 5
Doc No.: 44085409
A
Issued Date: Jul. 10, 2008
Model No.: N184H4 - L02
Preliminary
2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item Symbol
Storage Temperature TST -20 +60 ºC (1)
Operating Ambient T emperature TOP 0 +50 ºC (1), (2)
Shock (Non-Operating) S
Vibration (Non-Operating) V
Note (1) (a) 90 %RH Max. (Ta ≦ 40 ºC).
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The temperature of panel display surface area should be 0 ºC Min. and 60 ºC Max.
Relative Humidity (%RH)
100
90
- 220/2 G/ms (3), (5)
NOP
- 1.5 G (4), (5)
NOP
Min. Max.
Value
Unit Note
80
60
40
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Note (3) 1 time for ± X, ± Y, ± Z. for Condition (220G / 2ms) is half Sine Wave,.
Note (4) 10 ~ 500 Hz, 30 min/cycle,1cycles for each X, Y, Z axis.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid
enough so that the module would not be twisted or bent by the fixture.
20
10
Operating Range
Storage Range
8060 -20 400 20-40
Temperature (ºC)
The fixing condition is shown as below:
t Room Temperature
Side Mount Fixing Screw
Gap=2mm
Bracket
5 / 29
LCD Module
Side Mount Fixing Screw
Stage
Version 1.0
Page 6
Doc No.: 44085409
Issued Date: Jul. 10, 2008
Model No.: N184H4 - L02
Preliminary
2.2 ELECTRICAL ABSOLUTE RATINGS
2.2.1 TFT LCD MODULE
Item Symbol
Power Supply V oltage VCC -0.3 +4.0 V
Logic Input Voltage VIN -0.3 VCC+0.3 V
2.2.2 BACKLIGHT UNIT
Item Symbol
Lamp Voltage VL -- 2.5K V
Lamp Current IL 2.0 7.0 mA
Lamp Frequency FL 45 80 KHz
Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation
should be restricted to the conditions described under Normal Operating Co nditions.
Min. Max.
Min. Max.
Value
Value
Unit Note
(1)
Unit Note
(1), (2), IL = 6.0 mA
RMS
RMS
(1), (2)
Note (2) Specified values are for lamp (Refer to 3.2 for further information).
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Version 1.0
Page 7
Doc No.: 44085409
Issued Date: Jul. 10, 2008
Model No.: N184H4 - L02
Preliminary
3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE
Parameter Symbol
Min. Typ. Max.
Power Supply V oltage Vcc 3.0 3.3 3.6 V Permissive Ripple Voltage VRP 50 mV Rush Current I
1.5 A (2)
RUSH
Initial Stage Current IIS 1.0 A (2)
Power Supply Current
LVDS Differential Input High Threshold V
LVDS Differential Input Low Threshold V
White (390) mA (3)a
Black
Icc
TH(LVDS)
TL(LVDS)
(560) mA (3)b
+100 mV
-100 mV
LVDS Common Mode V oltage VCM 1.125 1.375 V (5)
LVDS Differential Input Voltage |VID| 100 600 mV (5)
Terminating Resistor RT 100 Ohm
Power per EBL WG P
- (TBD) - W (4)
EBL
Note (1) The ambient temperature is Ta = 25 ± 2 ºC.
Value
Unit Note
V
CM
V
CM
(5),
=1.2V
(5)
=1.2V
Note (2) I
I
: the maximum current when VCC is rising
RUSH
: the maximum current of the first 100ms after power-on
IS
Measurement Conditions: Shown as the following figure. Test pattern: black.
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(High to Low)
(Control Signal)
SW
+12V
C1
1uF
+3.3V
VR1
R1
47K
R2
1K
47K
Q1 2SK1475
FUSE
Q2
2SK1470
C2
0.01uF
Vcc rising time is 470us
0.9Vcc
0V
470us
0.1Vcc
+3.3V
100ms
I
RUSH
C3
1uF
Vcc
(LCD Module Input)
VCC
I
IS
ICC
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Version 1.0
Page 8
Doc No.: 44085409
|
|
Issued Date: Jul. 10, 2008
Model No.: N184H4 - L02
Preliminary
Note (3) The specified power supply current is under the conditions at Vcc = 3.3 V, Ta = 25 ± 2 ºC, fv = 60
Hz, whereas a power dissipation check pattern below is displayed.
Note (4) The specified power are the sum of LCD panel electronics input power and the inverter input
a. White Pattern
Active Area
power. Test conditions are as follows.
(a) Vcc = 3.3 V, Ta = 25 ± 2 ºC, f
(b) The pattern used is a black and white 32 x 36 checkerboard, slide #100 from the VESA file
“Flat Panel Display Monitor Setup Patterns”, FPDMSU.ppt.
(c) Luminance: 60 nits.
(d) The inverter used is provided from (Sumida). Please contact them for detail information. CMO
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doesn’t provide the inverter in this product.
= 60 Hz,
v
b. Black Pattern
Active Area
Note (5) The parameters of LVDS signals are defined as the following figures.
CM
Single Ended
Differential
V
0V
V
0V
V
VID|
VID|
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Version 1.0
Page 9
Doc No.: 44085409
Issued Date: Jul. 10, 2008
Model No.: N184H4 - L02
Preliminary
3.2 BACKLIGHT UNIT Ta = 25 ± 2 ºC
Parameter Symbol
Lamp Input Voltage VL
Lamp Current IL
Lamp Turn On Voltage VS
Operating Frequency FL 50
Lamp Life Time LBL 15000
Power Consumption PL
Note (1) Lamp current is measured by utilizing a high frequency current meter as shown below:
Min. Typ. Max.
－
－
－ － 1690 (0℃)
－ － 1860(25℃)
－
Value
820
6.0
－
－ －
9.84
Unit Note
－
－
80 KHz (3)
－
V
I
RMS
mA
RMS
V
(2)
RMS
V
(2)
RMS
Hrs (4)
W (5), IL = 6.0 mA
= 6.0 mA
L
(1)
Note (2) The voltage that must be larger than Vs should be applied to the lamp for more than 1 second
Note (3)The lamp frequency may generate interference with horizontal synchronous frequency from the
Note (4) The lifetime of lamp is defined as the time when it continues to operate under the conditions at Ta
LCD
Module
after startup. Otherwise the lamp may not be turned on.
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display, and this may cause line flow on the display. In order to avoid interference, the lamp
frequency should be detached from the horizontal synchronous frequency and its harmonics as far
as possible.
= 25 ±2
(a) When the brightness becomes ≦ 50% of its original value.
HV (Red)
LV (White)
HV (Blue)
HV (Black)
o
C and IL = 6.0 mA
1
2
Inverter
1
2
Ta = 25±2℃
until one of the following events occurs:
RMS
Current Meter
YOKOGAWA 2016
(b) When the effective ignition length becomes ≦ 80% of its original value. (The effective ignition
length is a scope that luminance is over 70% of that at the center point.)
Note (5) P
Note (6) The waveform of the voltage output of inverter must be area-symmetric and the design of the
= IL × VL × 2
L
inverter must have specifications for the modularized lamp. The performance of the Backlight,
such as lifetime or brightness, is greatly influenced by the characteristics of the DC-AC inverter for
the lamp. All the parameters of an inverter should be carefully designed to avoid generating too
much current leakage from high voltage output of the inverter. When designing or ordering the
inverter please make sure that a poor lighting caused by the mismatch of the Backlight and the
inverter (miss-lighting, flicker, etc.) never occurs. If the above situation is confirmed, the module
should be operated in the same manners when it is installed in your instrume nt.
9 / 29
Version 1.0
Page 10
Doc No.: 44085409
Issued Date: Jul. 10, 2008
Model No.: N184H4 - L02
Preliminary
Requirements for a system inverter design, which is intended to have a better display performance, a
better power efficiency and a more reliable lamp. It shall help increase the lamp lifetime and reduce its
leakage current.
a. The asymmetry rate of the inverter waveform should be 10% below;
b. The distortion rate of the waveform should be within √2 ± 10%;
c. The ideal sine wave form shall be symmetric in positive and negative polarities.
* Asymmetry rate:
I p
I -p
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| I
* Distortion rate
I
– I –p | / I
p
(or I –p) / I
p
rms
rms
* 100%
10 / 29
Version 1.0
Page 11
4. BLOCK DIAGRAM
(
)
(
)
4.1 TFT LCD MODULE
LVDS Display
Data & Clock
JAE-FI-XB30SRL-HF11
INPUT CONNECTOR
Vcc
GND
Data
CLK
V
EDID
EDID
EDID
VL
LAMP CONNECTOR
(JST-BHSR-02VS-1)
LVDS INPUT /
TIMING CONTROLLER
DC/DC CONVERTER &
REFERENCE VOLTAGE
GENERATOR
EDID
EEPROM
Issued Date: Jul. 10, 2008
Model No.: N184H4 - L02
SCAN DRIVER IC
TFT LCD PANEL
DA TA DRIVER IC
BACKLIGHT UNIT
Doc No.: 44085409
Preliminary
4.2 BACKLIGHT UNIT
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1. HV (Red)
2. LV
White
3. HV (Blue)
4. LV
Black
11 / 29
Version 1.0
Page 12
5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD MODULE
Pin Symbol Description Polarity Remark
1 Vss Ground
2 Vcc Power Supply +3.3 V (typical)
3 Vcc Power Supply +3.3 V (typical)
4 V
5 NC Non connection
6 CLK
7 DATA
8 RXO0- LVDS Differential Data Input (Odd) Negative
9 RXO0+ LVDS Differential Data Input (Odd) Positive
10 Vss Ground
11 RXO1- LVDS Differential Data Input (Odd) Negative
12 RXO1+ LVDS Differential Data Input (Odd) Positive
13 Vss Ground
14 RXO2- LVDS Differential Data Input (Odd) Negative
15 RXO2+ LVDS Differential Data Input (Odd) Positive
16 Vss Ground
17 RXOC- LVDS Clock Dat a Input (Odd) Negative
18 RXOC+ LVDS Clock Data Input (Odd) Positive
19 Vss Ground
20 RxE0- LVDS Differential Data Input (Even) Negative
21 RxE0+ LVDS Differential Data Input (Even) Positive
22 Vss Ground
23 RxE1- LVDS Differential Data Input (Even) Negative
24 RxE1+ LVDS Differential Data Input (Even) Positive
25 Vss Ground
26 RxE2- LVDS Differential Data Input (Even) Negative
27 RxE2+ LVDS Differential Data Input (Even) Positive
28 Vss Ground
29 RXEC- LVDS Clock Data Input (Even) Negative
30 RXEC+ LVDS Clock Data Input (Even) Positive
Note (1) Connector Part No.: JAE-FI-XB30SRL-HF11 or equivalent
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DDC 3.3V Power
EDID
DDC Clock
EDID
DDC Data
EDID
Doc No.: 44085409
Issued Date: Jul. 10, 2008
Model No.: N184H4 - L02
Preliminary
Note (2) User’s connector Part No: JAE-FI-X30C2L or equivalent
Note (3) The first pixel is odd as shown in the following figure.
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Page 13
5.2 BACKLIGHT UNIT
Pin Symbol Description Color
1 HV High Voltage Red
2 LV Ground White
3 HV High Voltage Blue
4 LV Ground Black
Note (1) Connector Part No.: JST BHSR-02VS-1 or equivalent
Note (2) User’s connector Part No.: JST-SM02B-BHSS-1-TB or equivalent
5.3 TIMING DIAGRAM OF LVDS IN PUT SIGNAL
RXOC+
RXO2+/-
RXO1+/-
RXO0+/-
T/7
IN20 IN19 IN18 IN17 IN16 IN15 IN14
DE OB5 OB4 OB3 OB2 Vsync Hsync
IN13 IN12 IN11 IN10 IN9 IN8 IN7
OB1 OG4 OG3 OG2 OG1 OB0 OG5
IN6 IN5 IN4 IN3 IN2 IN1 IN0
OG0 OR3 OR2 OR1 OR0 OR5 OR4
Doc No.: 44085409
Issued Date: Jul. 10, 2008
Model No.: N184H4 - L02
Preliminary
RXEC+
RXE2+/-
RXE1+/-
RXE0+/-
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T/7
IN20 IN19 IN18 IN17 IN16 IN15 IN14
DE EB5 EB4 EB3 EB2 Vsync Hsync
IN13 IN12 IN11 IN10 IN9 IN8 IN7
EB1 EG4 EG3 EG2 EG1 EB0 EG5
IN6 IN5 IN4 IN3 IN2 IN1 IN0
EG0 ER3 ER2 ER1 ER0 ER5 ER4
Signal for 1 DCLK Cycle (T)
Signal for 1 DCLK Cycle (T)
13 / 29
Version 1.0
Page 14
Doc No.: 44085409
Issued Date: Jul. 10, 2008
Model No.: N184H4 - L02
Preliminary
5.4 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 6-bit gray scale data input for
the color. The higher the binary input, the brighter the color. The table below provides the assignment of
color versus data input.
Data Signal
Color
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Black
Red
Green
Basic
Colors
Gray
Scale
Of
Red
Gray
Scale
Of
Green
Gray
Scale
Of
Blue
Note (1) 0: Low Level Voltage, 1: High Level Voltage
Blue
Cyan
Magenta
Yellow
White
Red(0)/Dark
Red(1)
Red(2)
:
:
Red(61)
Red(62)
Red(63)
Green(0)/Dark
Green(1)
Green(2)
:
:
Green(61)
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Green(62)
Green(63)
Blue(0)/Dark
Blue(1)
Blue(2)
:
:
Blue(61)
Blue(62)
Blue(63)
0
1
0
0
0
1
1
1
0
0
0
:
:
1
1
1
0
0
0
:
:
0
0
0
0
0
0
:
:
0
0
0
Red Green Blue
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
1
0
1
0
0
0
:
:
0
0
0
0
0
0
:
:
0
0
0
0
1
0
:
:
1
0
1
14 / 29
Version 1.0
Page 15
Doc No.: 44085409
Issued Date: Jul. 10, 2008
Model No.: N184H4 - L02
Preliminary
5.5 EDID DATA STRUCTURE
The EDID (Extended Display Identification Data) data formats are to support displays as defined in the
VESA Plug & Display and FPDI standards.
Byte #
(decimal)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
Byte #
(hex)
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Field Name and Comments
0 Header
1 Header
2 Header
3 Header
4 Header
5 Header
6 Header
7 Header
8 EISA ID manufacturer name (“CMO”)
9 EISA ID manufacturer name (Compressed ASCII)
0A ID product code (N184H4-L02) 01
0B ID product code (hex LSB first; N184H4-L02) 18
0C ID S/N (fixed “0”)
0D ID S/N (fixed “0”)
0E ID S/N (fixed “0”)
0F ID S/N (fixed “0”)
10 Week of manufacture (fixed week code)
11 Year of manufacture (fixed year code)
12 EDID structure version # (“1”)
13 EDID revision # (“3”)
14 Video I/P definition (“digital”)
15 Max H image size (“40.896cm”)
16 Max V image size (“23.004cm”)
17 Display Gamma (Gamma = ”2.2”)
18 Feature support (“Active off, RGB Color”)
19 Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0 CC
1A Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0 B5
1B Rx=0.6553 A7
1C Ry=0.3277 54
1D Gx=0.2722 45
1E Gy=0.5905 97
1F Bx=0.1508 26
20 By=0.0887 16
21 Wx=0.313 50
22 Wy=0.329 54
23 Established timings 1
24 Established timings 2
25 Manufacturer’s reserved timings
26 Standard timing ID # 1
27 Standard timing ID # 1
28 Standard timing ID # 2
29 Standard timing ID # 2
Value
(hex)
00 00000000
FF 11111111
FF 11111111
FF 11111111
FF 11111111
FF 11111111
FF 11111111
00 00000000
0D 00001101
AF 10101111
00 00000000
00 00000000
00 00000000
00 00000000
23 00100011
12 00010010
01 00000001
03 00000011
80 10000000
29 00101001
17 00010111
78 01111000
0A 00001010
00 00000000
00 00000000
00 00000000
01 00000001
01 00000001
01 00000001
01 00000001
Value
(binary)
00000010
00011000
11001100
10110101
10100111
01010100
01000101
10010111
00100110
00010110
01010000
01010100
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Doc No.: 44085409
Issued Date: Jul. 10, 2008
Model No.: N184H4 - L02
Preliminary
Byte #
(decimal)
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Byte #
(hex)
2A Standard timing ID # 3
2B Standard timing ID # 3
2C Standard timing ID # 4
2D Standard timing ID # 4
2E Standard timing ID # 5
2F Standard timing ID # 5
30 Standard timing ID # 6
31 Standard timing ID # 6
32 Standard timing ID # 7
33 Standard timing ID # 7
34 Standard timing ID # 8
35 Standard timing ID # 8
Detailed timing description # 1 Pixel clock (“138.65MHz”,
36
According to VESA CVT Rev1.1)
37 # 1 Pixel clock (hex LSB first)
38 # 1 H active (“1920”)
39 # 1 H blank (“160”)
3A # 1 H active : H blank (“1920 : 160”)
3B # 1 V active (”1080”)
3C # 1 V blank (”31”)
3D # 1 V active : V blank (”1080 :31”)
3E # 1 H sync offset (”48”)
3F # 1 H sync pulse width ("32”)
40 # 1 V sync offset : V sync pulse width (”3 : 5”)
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# 1 H sync offset : H sync pulse width : V sync offset : V sync
41
width (”48: 32 : 3 : 5”)
42 # 1 H image size (”408 mm”) 98
43 # 1 V image size (”230 mm”) E6
44 # 1 H image size : V image size (”408 : 230”)
45 # 1 H boarder (”0”)
46 # 1 V boarder (”0”)
# 1 Non-interlaced, Normal, no stereo, Separate sync, H/V pol
47
Negatives
48 Detailed timing description # 2
49 # 2 Flag
4A # 2 Reserved
# 2 FE (hex) defines ASCII string (Mod el Name “N184H4-L02”,
4B
ASCII)
4C # 2 Flag
4D # 2 1st character of name (“N”) 4E
4E # 2 2nd character of name (“1”) 31
4F # 2 3rd character of name (“8”) 38
50 # 2 4th character of name (“4”) 34
51 # 2 5th character of name (“H”) 48
52 # 2 6th character of name (“4”) 34
53 # 2 7th character of name (“-”) 2D
54 # 2 8th character of name (“L”) 4C
Field Name and Comments
Value
(hex)
01 00000001
01 00000001
01 00000001
01 00000001
01 00000001
01 00000001
01 00000001
01 00000001
01 00000001
01 00000001
01 00000001
01 00000001
29 00101001
36 00110110
80 10000000
A0 10100000
70 01110000
38 00111000
1F 00011111
40 01000000
30 00110000
20 00100000
35 00110101
00 00000000
10 00010000
00 00000000
00 00000000
18 00011000
00 00000000
00 00000000
00 00000000
FE 11111110
00 00000000
Value
(binary)
10011000
11100110
01001110
00110001
00111000
00110100
01001000
00110100
00101101
01001100
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Doc No.: 44085409
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Model No.: N184H4 - L02
Preliminary
Byte #
(decimal)
85
86
87
88
89
90
91
92
93
94
95 5F # 3 1st character of string (“C”)
96 60 # 3 2nd character of string (“M”)
97 61 # 3 3rd character of string (“O”)
98 62 # 3 New line character indicates end of ASCII string
99 63 # 3 Padding with “Blank” character
100 64 # 3 Padding with “Blank” character
101 65 # 3 Padding with “Blank” character
102 66 # 3 Padding with “Blank” character
103 67 # 3 Padding with “Blank” character
104 68 # 3 Padding with “Blank” character
105 69 # 3 Padding with “Blank” character
Byte #
(hex)
Field Name and Comments
55 # 2 9th character of name (“0”)
56 # 2 9th character of name (“2”)
57 # 2 New line character indicates end of ASCII string
58 # 2 Padding with “Blank” character
59 # 2 Padding with “Blank” character
5A Detailed timing description # 3
5B # 3 Flag
5C # 3 Reserved
5D # 3 FE (hex) defines ASCII string (Vendor “CMO”, ASCII)
5E # 3 Flag
Value
(hex)
Value
(binary)
30 00110000
32 00110011
0A 00001010
20 00100000
20 00100000
00 00000000
00 00000000
00 00000000
FE 11111110
00 00000000
43 01000011
4D 01001101
4F 01001111
0A 00001010
20 00100000
20 00100000
20 00100000
20 00100000
20 00100000
20 00100000
20 00100000
106 6A # 3 Padding with “Blank” character
107 6B # 3 Padding with “Blank” character
108 6C Detailed timing description # 4
109 6D # 4 Flag
110 6E # 4 Reserved
111 6F
112 70 # 4 Flag
113 71 # 4 1st character of name (“N”) 4E
114 72 # 4 2nd character of name (“1”) 31
115 73 # 4 3rd character of name (“8”) 38
116 74 # 4 4th character of name (“4”) 34
117 75 # 4 5th character of name (“H”) 48
118 76 # 4 6th character of name (“4”) 34
119 77 # 4 7th character of name (“-”) 2D
120 78 # 4 8th character of name (“L”) 4C
121 79 # 4 9th character of name (“0”)
122 7A # 4 9th character of name (“2”)
123 7B # 4 New line character indicates end of ASCII string
124 7C # 4 Padding with “Blank” character
125 7D # 4 Padding with “Blank” character
126 7E Extension flag
127 7F Checksum 9D 10011111
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# 4 FE (hex) defines ASCII string (Model Name“N184H4-L02”,
ASCII)
20 00100000
20 00100000
00 00000000
00 00000000
00 00000000
FE 11111110
00 00000000
01001110
00110001
00111000
00110100
01001000
00110100
00101101
01001100
30 00110000
32 00110011
0A 00001010
20 00100000
20 00100000
00 00000000
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Doc No.: 44085409
Issued Date: Jul. 10, 2008
Model No.: N184H4 - L02
Preliminary
6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram.
Signal Item Symbol Min. Typ. Max. Unit Note
DCLK Frequency 1/Tc TBD 69.25 TBD MHz (2)
Vertical Total Time TV TBD 1111 TBD TH -
Vertical Active Display Period TVD TBD 1080 TBD TH -
DE
Note (1) Because this module is operated by DE only mode, Hsync and Vsync are ignored.
(2) 2 channels LVDS input.
Vertical Active Blanking Period TVB TV-TVD 31 TV-TVD TH
Horizontal Total Time TH TBD 1040 TBD Tc (2)
Horizontal Active Display Period THD TBD 960 TBD Tc (2)
Horizontal Active Blanking Period THB
TH-THD
80
TH-THD
Tc (2)
INPUT SIGNAL TIMING DIAGRAM
DE
DCLK
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DE
DATA
TC
T
HD
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6.2 POWER ON/OFF SEQUENCE
Power On
Doc No.: 44085409
Issued Date: Jul. 10, 2008
Model No.: N184H4 - L02
Preliminary
Restart
Power Off
Power Supply
for LCD, Vcc
LVDS Interface
- Power for Lamp
Timing Specifications:
0.5≦ t1 ≦ 10 ms
0 ≦ t2 ≦ 50 ms
0 ≦ t3 ≦ 50 ms
Note (1) Please follow the power on/off sequence described above. Otherwise, the LCD module might be
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0V
0V
t4 ≧ 500 ms
t5 ≧ 200 ms
t6 ≧ 200 ms
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10%
90%
t1
90%
Valid Data
t6 t5
50%50%
ONOFF OFF
t7
10%
t4
t3 t2
10%
damaged.
Note (2) Please avoid floating state of interface signal at invalid period. When the interface signal is invalid, be
sure to pull down the power supply of LCD Vcc to 0 V.
Note (3) The Backlight inverter power must be turned on after the power supply for the logic and the
interface signal is valid. The Backlight inverter power must be turned off before the power supply
for the logic and the interface signal is invalid.
Note (4) Sometimes some slight noise shows when LCD is turned off (even backlight is already off). To
avoid this phenomenon, we suggest that the Vcc falling time is better to follow (50us)≦t7≦10ms.
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Doc No.: 44085409
Issued Date: Jul. 10, 2008
Model No.: N184H4 - L02
Preliminary
7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
Item Symbol Value Unit
Ambient Temperature Ta
Ambient Humidity Ha
Supply Volt age VCC 3.3 V
Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS"
Inverter Current IL 6.0 mA
Inverter Driving Frequency FL 55 KHz
Inverter Darfon-VK.121164.101
25±2
50±10
7.2 OPTICAL SPECIFICATIONS
The relative measurement methods of optical characteristics are shown in 7.2. The following items
should be measured under the test conditions described in 7.1 and stable environment shown in Note (5).
Item Symbol Condition Min. Typ. Max. Unit Note
Red
Color
Chromaticity
Average Luminance of White L
Contrast Ratio CR
Response Time
White Variation
Viewing Angle
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Green
Blue
White
Horizontal
Vertical
Rx
Ry
Gx
Gy
Bx
By
Wx 0.313
Wy
(250) (300) --- cd/m2(4), (5)
AVE
TR --- 2 8 ms
T
F
δW θ
θ
+
x
θ
-
x
θ
+
Y
θ
-
Y
θ
=0°, θY =0°
x
CS-1000T
=0°, θY =0°
θ
x
=0°, θY =0°
x
CR ≧ 10
Typ –
0.03
500 650 --- - (2), (5)
--- 6 12 ms
--- 1.25 1.40 - (5), (6)
50 60 --50 60 --40 50 --40 50 ---
(0.645)
(0.323)
(0.264)
(0.603)
(0.156)
(0.077)
0.329
Typ +
0.03
o
C
%RH
(1), (5)
(3)
Deg. (1), (5)
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Note (1) Definition of Viewing Angle (θx, θy):
Doc No.: 44085409
Issued Date: Jul. 10, 2008
Model No.: N184H4 - L02
Preliminary
Note (2) Definition of Contrast Ratio (CR):
θX- = 90º
6 o’clock
θ
y- = 90º
The contrast ratio can be calculated by the following expression.
Contrast Ratio (CR) = L63 / L0
x-
y-
Normal
θx = θy = 0º
θy- θy+
θx−
θx+
y+
12 o’clock direction
θ
y+ = 90º
x+
θX+ = 90º
L63: Luminance of gray level 63
L 0: Luminance of gray level 0
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CR = CR (1)
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CR (X) is corresponding to the Contrast Ratio of the point X at Figure in Note (6).
Note (3) Definition of Response Time (T
100%
90%
Optical
Response
10%
0%
R
T
R
66.67 ms
, TF):
T
F
66.67 ms
Time
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Doc No.: 44085409
500
Issued Date: Jul. 10, 2008
Model No.: N184H4 - L02
Preliminary
Note (4) Definition of Average Luminance of White (L
Measure the luminance of gray level 63 at 5 points
L
= [L (1)+ L (2)+ L (3)+ L (4)+ L (5)] / 5
AVE
L (x) is corresponding to the luminance of the point X at Figure in Note (6)
Note (5) Measurement Setup:
The LCD module should be stabilized at given temperature for 20 minutes to avoid abrupt
temperature change during measuring. In order to stabilize the luminance, the measurement
should be executed after lighting Backlight for 20 minutes in a windless room.
LCD Module
LCD Panel
USB2000
AVE
):
CS-1000T
Center of the Screen
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mm
Light Shield Room
(Ambient Luminance < 2 lux)
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Note (6) Definition of White Variation (δW):
Measure the luminance of gray level 63 at 5 points
δW = { Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]
Doc No.: 44085409
Issued Date: Jul. 10, 2008
Model No.: N184H4 - L02
Preliminary
Horizontal Line
Vertical Line
H/4
H/2
H
3H/4
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W/4 W/2 3W/4
2 3
4
W
1
Active Area
: Test Point
X
X=1 to 5
5
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Doc No.: 44085409
Issued Date: Jul. 10, 2008
Model No.: N184H4 - L02
Preliminary
8. PRECAUTIONS
8.1 ASSEMBL Y AND HANDLING PRECAUTIONS
(1) Do not apply rough force such as bending or twisting to the module during assembly.
(2) To assemble or install module into user’s system can be only in clean working areas. The dust and oil
may cause electrical short or worsen the polarizer.
(3) It’s not permitted to have pressure or impulse on the module because the LCD panel and Backlight will
be damaged.
(4) Always follow the correct power sequence when LCD module is connecting and operating. This can
prevent damage to the CMOS LSI chips during latch-up.
(5) Do not pull the I/F connector in or out while the module is operating.
(6) Do not disassemble the module.
(7) Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and
easily scratched.
(8) It is dangerous that moisture come into or contacted the LCD module, because moisture may damage
LCD module when it is operating.
(9) High temperature or humidity may reduce the performance of module. Please store LCD module within
the specified storage conditions.
(10) When ambient temperature is lower than 10ºC may reduce the display quality. For example, the
response time will become slowly, and the starting voltage of CCFL will be higher than room
temperature.
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8.2 SAFETY PRECAUTIONS
(1) The startup voltage of Backlight is approximately 1000 Volts. It may cause electrical shock while
assembling with inverter. Do not disa ssemble the module or insert anything into the Backlight unit.
(2) If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In
case of contact with hands, skin or clothes, it has to be washe d away thoroughly with soap.
(3) After the module’s end of life, it is not harmful in case of normal operation and storage.
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9. PACKING
9.1 CARTON
Doc No.: 44085409
Issued Date: Jul. 10, 2008
Model No.: N184H4 - L02
Preliminary
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Figure. 9-1 Packing method
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9.2 PALLET
Doc No.: 44085409
Issued Date: Jul. 10, 2008
Model No.: N184H4 - L02
Preliminary
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Figure. 9-2 Packing method
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Doc No.: 44085409
Issued Date: Jul. 10, 2008
Model No.: N184H4 - L02
Preliminary
10. DEFINITION OF LABELS
10.1 CMO MODULE LABEL
The barcode nameplate is pasted on each module as illustration, and its definitions are as following
explanation.
N184H4 -L02
(a) Model Name: N184H4 - L02
(b) Revision: Rev. XX, for example: A1, …, C1, C2 …etc.
(c) Serial ID: X X
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(d) Production Location: MADE IN XXXX. XXXX stands for production location.
(e) UL logo: LEOO especially stands for panel manufactured by CMO NingBo satisfying UL requirement.
Serial ID includes the information as below:
(a) Manufactured Date: Year: 1~9, for 2001~2009
(b) Revision Code: cover all the change
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The panel without LEOO mark stands for manufactured by CMO Taiwan satisfying UL requirement.
X X X X X Y M D X N N N N
Month: 1~9, A~C, for Jan. ~ De c.
Day: 1~9, A~Y, for 1
Serial No.
CMO Internal Use
Year, Month, Date
CMO Internal Use
Revision
CMO Internal Use
st
to 31st, exclude I , O and U
(c) Serial No.: Manufacturing sequence of product
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10.2 CMO CARTON LABEL
Doc No.: 44085409
Issued Date: Jul. 10, 2008
Model No.: N184H4 - L02
Preliminary
(a) Production location: Made In XXXX. XXXX stands for production location.
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