2. General Description................................................................................................................................5
3. Absolute Maximum Ratings.................................................................................................................... 8
4. Pixel Format Image ................................................................................................................................9
9.2 Line Defect........................................................................................................................................ 30
9.3 Bright and Black Dots ....................................................................................................................... 31
9.4 CFL Life ............................................................................................................................................ 32
11.1 Serial Number Label ......................................................................................................................... 35
11.2 Date Label ........................................................................................................................................ 35
11.3 UL Label............................................................................................................................................ 36
Logic Power Consumption [watt](VDD Line) 0.9 Typ. (All Black Pattern)
Backlight Power Consumption [watt] 3.5 typ (ICFL = 6.0mA)
Weight [grams] 260 typ, 280 max
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Physical Size [mm] 261.0(W) x 198.0(H) x 4.7(D) Typ. (without inverter space)
Electrical Interface (Logic) Single LVDS(4 pairs LVDS)
Support Color Native 262K colors (RGB 6-bit data driver)
Temperature Range (degree C)
Operating
Storage (Shipping)
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+3.3 Typ
EEDID (clock, data)
0 to +50
-20 to +60
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Document Control Number CAS I-N121X4-L01-HP02 Version 3.1
Page 7
2.2 Functional Block Diagram
Figure 1 shows the functional block of the color TFT/LCD Module:
Figure 1 Block Diagram
TFT LCD Module
LCD Drive Card
Issued Date: Mar. 10, 2005
Model No: N121X4-L01
X-Driver
VDD
GND
4 pairs s ingle
channel LVDS
RxIN0+/RxIN1+/RxIN2+/RxCLKIN+/-
VEE DID
ClkEDID
DataEDID
Signal Connector DF19L-20P-1H
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Timing Controller LSI
DC/DC converter
Reference
voltage circ uit
EEDID EEPROM
Y-Driver
TFT Array/Cell
1024(R/G/B) x 768
Backlight Unit
Lamp Connector
JST BHSR-02VS-1
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Page 8
Issued Date: Mar. 10, 2005
Model No: N121X4-L01
3. Absolute Maximum Ratings
Table 2 Absolute maximum ratings
Item Symbol Min Max Unit Conditions
Supply Voltage VDD -0.3 +4.0 V
Input Voltage of Signal Logic input
signals(LVDS,
EDID)
Lamp Ignition Voltage Vinv - +2,000 Vrms Ta = 0 [deg. C]
CFL Current ICFL - 6.5 mArms
CFL Peak Inrush Current ICFLP - 20 mArms Ta = 25 [deg. C]
Operating Temperature TOP 0 +50 deg. C (Note 2)
Operating Humidity HOP 8 95 %RH (Note 2)
Storage Temperature TST -20 +60 deg. C (Note 2)
Storage Humidity HST 5 95 %RH (Note 2)
Vibration 1.5 10-200 G Hz
Shock 50 18 G ms Rectangle Wave
Note:
1. Duration: 50 [msec] Max.
2. Maximum Wet-Bulb should be 39 degree C and No condensation.
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-0.3 VDD+0.3 V
(Note 1)
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Page 9
Issued Date: Mar. 10, 2005
Model No: N121X4-L01
4. Pixel Format Image
Following figure shows the relationship of the input signals and LCD pixel format image.
Figure 2 Pixel Format
1st Line
768th Line
0
1
R
G
B
G
BR
R
B
R
R
G
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B
G
1022 1023
G
G
BR
B
RG
G
R
B
B
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Page 10
5. Mechanical Characteristics
Figure 3 Reference outline drawing
Issued Date: Mar. 10, 2005
Model No: N121X4-L01
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Page 11
Issued Date: Mar. 10, 2005
Model No: N121X4-L01
6. Optical Characteristics
6.1 Optical Characteristics
The optical characteristics are measured under stable conditions as follows under 25 degree C condition:
Table 3 Optical characteristics
Specification Item Conditions
Min Typ. Max Note
Viewing Angle (Degrees) Horizontal (Right)
K>10(Left)
K: Contrast Ratio Vertical (Upper)
K>10 (Lower)
Contrast ratio 200 250 -
Response Time(ms) Rising + Falling - - 50
Color Chromaticity(CIE)
Red x 0.558 0.584 0.610 +/-0.026
Red y 0.308 0.336 0.364 +/-0.028
Green x 0.296 0.322 0.348 +/-0.026
Green y 0.506 0.534 0.562 +/-0.028
Blue x 0.125 0.151 0.177 +/-0.026
Blue y 0.100 0.128 0.156 +/-0.028
White x 0.287 0.313 0.339 +/-0.026
White y 0.301 0.329 0.357 +/-0.028
-
-
-
-
155 180 - Center White Luminance(cd/m2) ICFL=6.0mA
145 170 - 5pts
40
40
15
30
-
-
-
-
average
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Page 12
Figure 4 Note for the Optical Characteristics
Issued Date: Mar. 10, 2005
Model No: N121X4-L01
Z
Viewing or Measuring
Direction
Viewing or Measuring
Direction
+h-v
LEFT
UPPER
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LOWER
RIGHT
X
CENTER OF LCD
(X=0,Y=0,Z=0)
Chromaticity and White Balance are defined as the C.I.E. 1931 x,y coordinates at the center of LCD. The Standard
Equipments are as shown below table.
Table 4 Standard Equipments
Item Standard Equipment
Viewing Angle MCPD-7000 by Ohtsuka Elec.
Contrast MCPD-7000 by Ohtsuka Elec.
Response Time BM5A by TOPCON OPTICAL Co.,Ltd.
White Luminance MCPD-7000 by Ohtsuka Elec.
Luminance Uniformity MCPD-7000 by Ohtsuka Elec.
Chromaticity MCPD-7000 by Ohtsuka Elec.
White Balance MCPD-7000 by Ohtsuka Elec.
The measurement is to be done after 30 minutes of Power-on of BackLight.
Unless otherwise specified, the ambient conditions are as following.
Y
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Page 13
+
+
Table 5 Ambient conditions
Ambient Temperature 25 +/-2 (degC)
Ambient Humidity 25 to 85 (%)
Atmospheric Pressure 86.0 to 104.0 ( kPa )
6.2 Luminance Uniformity
When backlight is on with all pixels in the unselected state(white raster), average luminance and luminance
uniformity(variation) is defined as below.
LuminanceAverage
=
++
54321
LLLLL
Issued Date: Mar. 10, 2005
Model No: N121X4-L01
5
)5,2,1max(
LLL
UNF(5pts)≤=
UNF(13pts)≤=
L
L
L
L
LLL
LLL
LLL
25.1
)5,2,1min(
)13,2,1max(
65.1
)13,2,1min(
Figure 5 Average luminance and Luminance uniformity test points
L6L7
L9
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L11
10mm
L1L2
L5
L3
L12L13
256
512
768
L8
L10
L4
10mm
10mm
192
384
576
10mm
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Document Control Number CAS I-N121X4-L01-HP02 Version 3.1
Page 14
7. Backlight Characteristics
7.1 CFL Connector
Table 6 Connector Name / Designation
Manufacturer JST
Type / Part Number BHSR-02VS-1
Mating Type / Part Number SM02B-BHSS-1
Table 7 Signal assignment
Pin # Signal Name
1 Lamp High Voltage
2 Lamp Low Voltage
Issued Date: Mar. 10, 2005
Model No: N121X4-L01
7.2 Parameter guideline for CFL Inverter
Table 8 Parameter guideline for CFL Inverter
SYMBOL PARAMETER MIN Design
Point
(L63) White Luminance
(Center)
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(5 points average)
ICFL CFL current 4.0 6.5 [mArms] Ta=25[deg. C]
ICFL
ICFLP CFL Peak Inrush Current 20 [mA] Ta=25[deg. C]
FCFL CFL Frequency 40 60 [kHz] Ta=25[deg. C]
CFL current Dimming
Range
-
-
3.0 6.0
180
170
(100%Duty)
MAX UNITS CONDITION
-
-
6.5 [mArms] Ta=25[deg.C]
[cd/m
[cd/m
2
]
2
]
Ta=25[deg. C]
(Note 2)
(Note 2,6)
(Note 3)
VCFLi Inverter Ignition Voltage 1,600 [Vrms] Ta=0[deg. C]
VCFL CFL Voltage (Reference) 580 [Vrms] Ta=25[deg. C]
PCFL CFL Power consumption 3.5 3.6 [W] ICFL=6.0mA
Ta=25[deg. C]
(Note 4)
Note:
1. -
2. If it exceeds MIN/MAX values, then "CFL Life" , "ON/OFF Cycle", and "SAFETY" will not be guaranteed.
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3. CFL Frequency should be carefully determined to avoid interference between inverter and TFT LCD.
4. Calculated value for reference (ICFL x VCFL = PCFL).
5. It should be employed the inverter that has `Duty Dimming`, if ICFL is less than 4[mA].
6. Duration: 50msec MAX
7. CFL has some amount of delay time after applying kick-off voltage. It is should keep on applying kick-off voltage
for 1[Sec]until discharge.
Figure 6 Luminance versus Lamp Current(reference only)
N121X4-L01
200
180
Issued Date: Mar. 10, 2005
Model No: N121X4-L01
160
140
cd/m2
120
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100
80
3.03.54.04.55.05.56.06.5
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mA
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Page 16
Issued Date: Mar. 10, 2005
Model No: N121X4-L01
8. Electrical Characteristics
8.1 Interface Connector
Table 9 Connector Name / Designation
Manufacturer HIROSE
Type / Part Number DF19L-20P-1H
Mating Receptacle/Part Number DF19G-20S-1F (FPC Type)
DF19G-20S-1C (Cable Type)
Table 10 Signal pin assignment
Pin # Signal Name Description Remarks
1 GND Ground
2 VDD
3 VDD
4 VEDID EEDID 3.3V Power Supply Power source shall be the limited current
5 Reserved LCD test pin This pin must be left unconnected.
6 ClkEDID EEDID Clock CLKEEDID line and DATAEEDID line are
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7 DataEDID EEDID Data
8 RxIN0-
9 RxIN0+
10 GND Ground
11 R xIN1 -
12 RxIN1+
13 GND Ground
+3.3V Power Supply
LVDS differential data input
(Red0-Red5, Green0)
LVDS differential data input
(Green1-Green5, Blue0-Blue1)
circuit that has not exceeding 1A. Refer to
"Enhanced Display Data Channel (E-DDCTM)
Proposed Standard", VESA.
pulled up with 10k ohm resistor to VEEDID
power source line at LCD panel, respectively.
Has 100ohm termination resistor
Has 100ohm termination resistor
14 RxIN2-
15 RxIN2+
16 GND Ground
17 RxCLKIN-
18 RxCLKIN+
19 GND Ground
20 GND Ground
All input signals shall be low or Hi-Z state when VDD is off.
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Document Control Number CAS I-N121X4-L01-HP02 Version 3.1
LVDS differential data input
(Blue2-Blue5, HSync, VSync,
DSPTMG)
LVDS differential clock input Has 100ohm termination resistor
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Has 100ohm termination resistor
Page 17
Table 11 Interface Signal Description
SIGNAL NAME Description
Issued Date: Mar. 10, 2005
Model No: N121X4-L01
+RED5
+RED4
+RED3
+RED2
+RED1
+RED0
+GREEN 5
+GREEN 4
+GREEN 3
+GREEN 2
+GREEN 1
+GREEN 0
+BLUE 5
+BLUE 4
+BLUE 3
+BLUE 2
+BLUE 1
Red Data 5 (MSB)
Red Data 4
Red Data 3
Red Data 2
Red Data 1
Red Data 0 (LSB)
Green Data 5 (MSB)
Green Data 4
Green Data 3
Green Data 2
Green Data 1
Green Data 0 (LSB)
Blue Data 5 (MSB)
Blue Data 4
Blue Data 3
Blue Data 2
Blue Data 1
Red-pixel Data
Each red pixel's brightness data consists of these 6 bits pixel data.
Green-pixel Data
Each green pixel's brightness data consists of these 6 bits pixel data.
Blue-pixel Data
Each blue pixel's brightness data consists of these 6 bits pixel data.
+BLUE 0
-DTCLK Data Clock The signal is used to strobe the pixel data.
DSPTMG Display Timing When the signal is high, the pixel data shall be valid to be displayed.
VSYNC Vertical Sync
HSYNC Horizontal Sync
Blue Data 0 (LSB)
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Issued Date: Mar. 10, 2005
Model No: N121X4-L01
8.2 LVDS Receiver
8.2.1. Signal Electrical Characteristics for LVDS Receiver
The built-in LVDS receiver is compatible with ANSI/TIA/TIA-644 standard.
Table 12 LVDS Receiver Electrical Characteristics
Parameter Symbol Min Typ Max Unit Conditions
Differential Input High Threshold Vth +100 mV Vcm=+1.2V
Differential Input Low Threshold Vtl -100 mV Vcm=+1.2V
Magnitude Differential Input Voltage |Vid| 100 600 mV
Common Mode Voltage Vcm 1.0 1.2 1.4 V Vth - Vtl = 200mV
Common Mode Voltage Offset ∆Vcm -50 +50 mV Vth - Vtl = 200mV
Note:
▪ Input signals shall be low or Hi-Z state when VDD is off.
▪ All electrical characteristics for LVDS signal are defined and shall be measured at the interface connector of
LCD.
Parameter Symbol min typ max unit
Input low voltage VIL 0 0.3VDD V
Input high voltage VIH 0.7VDD VDD V
Input leakage current IIZ -10 10 uA
Table 13 Timing Requirements
Parameter Symbol Min Typ Max Unit Conditions Note
Clock Frequency fc 50 65 67 MHz
Cycle Time tc 14.93 15.38 20.00 ns
Data Setup Time Tsu 600 ps (See Figure 10)
Data Hold Time Thd 600 ps
Cycle-to-cycle jitter tCCJ -150 +150 ps fc = 65MHz
Cycle Modulation
Rate
Note:.All values are at VDD=3.3V, Ta=25 degree C.
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tCJavg 20 ps/clk fc = 65MHz
fc = 65MHz
tCCJ < 50ps
Vth-Vtl = 200m
Vcm = 1.2V
∆Vcm = 0
Tsu=Thd=600ps
Tsu=Thd=600ps
(See Figure 10)
Jitter is the magnitude of the change in input
clock period.
tCJavg is maximum average cycle
modulation rate in peak-to-peak transition
within any 100-clock cycles. Figure
11illustrates a case against this requirement.
This specification is applied only if input
clock peak jitter within any 100-clock cycles
is greater than 300ps.
Figure 7 Voltage Definitions
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Issued Date: Mar. 10, 2005
Model No: N121X4-L01
Figure 8 Measurement System
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Figure 9 Data mapping
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Issued Date: Mar. 10, 2005
Model No: N121X4-L01
Figure 10 Timing Definition (detail A)
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Note: Tsu and Thd are internal data sampling window of receiver. Trskm is the system skew margin; i.e., the sum
of cable skew, source clock jitter, and other inter-symbol interference, shall be less than Trskm.
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Figure 11 Cycle Modulation Rate
Issued Date: Mar. 10, 2005
Model No: N121X4-L01
8.2.2. LVDS Receiver Internal Circuit
Figure 12 shows the internal block diagram of the LVDS receiver. This LCD module equips termination resistors
for LVDS link.
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Figure 12 LVDS Receiver Internal Circuit
Issued Date: Mar. 10, 2005
Model No: N121X4-L01
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8.2.3. Recommended Guidelines for Motherboard PCB Design and Cable Selection
Following the suggestions below will help to achieve optimal results.
Use controlled impedance media for LADS signals. They should have a matched differential impedance of 100 ohm.
Match electrical lengths between traces to minimize signal skew.
Isolate TEL signals from LADS signals.
For cables, twisted pair, twin, or flex circuit with close coupled differential traces are recommended.
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8.3 Interface Timings
If timing signal is invalid, the LCD enters "self protection mode" and the screen becomes whole black. Once the
signal is back, it resumes normal operation.
8.3.1. Timing Characteristics
Table 14 Interface timings
SymbolParameter MINTYP MAXUnitNote
fdck DTCLK Frequency 65.00MHzSee Figure 13
tck DTCLK cycle time 15.38nsec
Htotal H total time 132413442047tck
Hac H active time 102410241024tck
Hsw H-Sync width 8 136 tck
Hbp H back porch 8 160 tck
Hfp H front porch 0 24 tck
Vtotal V total time 779 806 1023tx
Vac V active time 768 768 768 tx
Vsync Frame rate 55 60 61 Hz
Vsw V-sync Width 1 6 tx
Vfp V-sync front porch 1 3 tx
Vbp V-sync back porch 9 29 63 tx Vbp should be static.
Issued Date: Mar. 10, 2005
Model No: N121X4-L01
32 <= Hsw + Hbp < 515
[tck].
8.3.2. Timing Definition
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HSYNC
DSPTMG
VSYNC
DSPTMG
Figure 13 Timing Definition
HfpHswHbp
VfpVs wVbp
Htotal
Vac
Vtotal
Vac
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Page 24
Issued Date: Mar. 10, 2005
Model No: N121X4-L01
8.4 EEDID
Table 15 EEDID
Supported Standards VESA ENHANCED EXTENDED DISPLAY IDENTIFICATION DATA
STANDARD Release A, Revision 1" and supports "EEDID version 1.3
EEPROM IC BR24L02F(ROHM) or equivalent
I2C Device Address A0/A1
Table 16 Data table
AddressCategory Description Data Remark
00h Header Header 00h Header , Fixed
01h Header Header FFh Header , Fixed
02h Header Header FFh Header , Fixed
03h Header Header FFh Header , Fixed
04h Header Header FFh Header , Fixed
05h Header Header FFh Header , Fixed
06h Header Header FFh Header , Fixed
07h Header Header 00h Header , Fixed
EISA Manuf. Code LSB 3 character in compressed ASCII:
08h Vendor/Product Identification ID Manufacturer Name 0Dh
09h Vendor/Product Identification ID Manufacturer Name AFh
0Ah Vendor/Product Identification ID Product Code 01h
0Bh Vendor/Product Identification ID Product Code 12h
0Ch Vendor/Product Identification ID Serial Number 00h Optional 32-bit serial no. Unused(00h)
0Dh Vendor/Product Identification ID Serial Number 00h Optional 32-bit serial no. Unused(00h)
0Eh Vendor/Product Identification ID Serial Number 00h Optional 32-bit serial no. Unused(00h)
0Fh Vendor/Product Identification ID Serial Number 00h Optional 32-bit serial no. Unused(00h)
10h Vendor/Product Identification Week of Manufacture 00h Week of manufacture 1 - 53 (unused: 00h)
11h Vendor/Product Identification Year of Manufacture 00h Year of manufacture year - 1990(unsed:00h)
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"CMO" 0D AF
EISA Manuf. Code LSB 3 character in compressed ASCII:
SYMBOL PARAMETER Min Typ Max UNITS CONDITION
VDD Logic/LCD Drive Voltage 3.0 3.3 3.6 [V] Load Capacitance 20[uF]
PDD VDD Power 1.2 [W] Max pattern
PDD VDD Power 0.9 [W] All Black Pattern
IDD VDD Current 340 [mA] Max Pattern
IDD VDD Current 250 [mA] All Black Pattern
VDDrp Allowable Logic/LCD
Drive Ripple Voltage
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100 [mVp-p]
Issued Date: Mar. 10, 2005
Model No: N121X4-L01
VDD=3.6[V]
VDD=3.3[V]
VDD=3.6[V]
VDD=3.3[V]
8.6 Power ON/OFF Sequence
Figure 14 and Table 18 show VDD power and lamp on/off sequence requirements.
Signals from any system shall be Hi-Z state or low level when VDD is off.
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Issued Date: Mar. 10, 2005
Model No: N121X4-L01
Figure 14 Power sequence
T1
VDD
LVDS signals
FPVEE
5VALW/5VSUS
PWR_SRC
90%
T2T3T4
Valid
T5T6
T7T8
T9T10T11
10%
90%
0V
0V
0V
0V
0V
10%
Table 18 Power Sequencing Requirements
Parameter Symbol Unitmin typ max
VDD rise time T1 ms 0.5 - 10
VDD on => signal on T2 ms 0 - 50
Signal off => VDD off T3 ms 0 - 50
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5VALW/5VSUS on => FPVEE on T7 ms 0 - -
FPVEE off => 5VALW/5VSUS off T8 ms 0 - -
PWR_SRC on => FPVEE on T10 ms 10 - -
FPVEE off => PWR_SRC off T11 ms 0 - -
VDD off T4 ms 500 - -
Signal on => B/L on T5 ms 200 - -
B/L off => signal off T6 ms 200 - -
PWR_SRC rise time T9 ms 1 - 30
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Issued Date: Mar. 10, 2005
Model No: N121X4-L01
9. Qualifications and CFL Life
This Quality Specification is supplied from CHI MEI Optoelectronics to the customer.
Please pay attention the following items, when this LCD Module is checked in your inspection.
You should consider the LCD Module to mount that uneven force is not applied to this LCD Module.
Do not push and put a label on the rear side that is located backlight.
Do not joggle the LCD Module, there will be some ripple on the screen.
Display qualifications depend on the power on time. The visual screen quality is applied the state since 30 seconds after
power on.
9.1 Visual Screen Quality
Table 19 shows the visual screen quality of the general TFT-LCD module at power-off.
Table 19 Visual screen quality
Polarizer Scratch/Bubble Size (mm) Allowable maximum counts
Elliptical defects d < 0.2 Disregarded
Linear defects w < 0.03 Disregarded
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d : diameter, d= (longaxis + shortaxis) / 2
w : line width
l : line length
9.2 Line Defect
No visible line defect is allowed in entire screen.
A Line Defect is defined as a horizontal and vertical apparent line, visible through 5% ND-filter, that differs from adjacent
lines at any gray raster pattern.
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0.2 < d < 0.4 3
0.4 < d 0
0.03 < w < 0.1 and I < 1.0 4
0.1 < w or 1.0 < l 0
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9.3 Bright and Black Dots
The following Table describes the specification of bright and black dots in the visual screen quality of the TFT-LCD
module at power-ON.
Table 20 Pixel defects
Items Specification
Green bright dots
Red/blue bright dots
Any black dots
Bright and black dots(total)
Two joined bright dots
Two joined black dots
Black dots distance
Definitions:
1. A bright dot is a lit sub pixel under all black.
2. A black dot is an unlit subpixel under maximum brightness single color pattern(red, green, blue) or
full white.
Basic Conditions:
Viewing Distance
Viewing angle
Ambient Illumination
Ambient Temperature
approx. 350 mm
+/-25 degree horizontal, +/-10 degree vertical
300 to 500 lux
25 degreeC
0
1 max(note 1)
3 max
4 max
0 pair
1 pair max
25 mm min
Issued Date: Mar. 10, 2005
Model No: N121X4-L01
(Note 1) More than 95% shipping volume is without bright dot defect. No bright dots exist center 49%
area(see Figure 15)Figure 15 Not bright dot area
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.15H
W = active area width
H = active
Center 49% Area
area
Bright Dot
height
.7H
Defect Free
.7W
.15W
.15W
.15H
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9.4 CFL Life
Table 21 CFL life
CFL Life Time 10,000 Hours condition 25 deg.C and
ICFL=6.0mArms
The assumed CFL Life will be until the luminance becomes 50% of its initial value.
Issued Date: Mar. 10, 2005
Model No: N121X4-L01
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10. Packaging Specifications
20 LCD modules / 1 Box
Box dimensions: 383(L) x 323(W) x 341(H)
Meets 90 cm drop test
Figure 16 Packaging(type-A)
Issued Date: Mar. 10, 2005
Model No: N121X4-L01
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Figure 17 Packaging(type-B)
Issued Date: Mar. 10, 2005
Model No: N121X4-L01
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11. Labels
There are labels on the rear side of the Module.
11.1 Serial Number Label
Figure 18 Serial Number Label
Figure 19 Barcode Character Sequence
Issued Date: Mar. 10, 2005
Model No: N121X4-L01
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11.2 Date Label
YY and WW of the Week Code stand for the Year and the Week of the Year of manufacturing of the Module
respectively.
Figure 20 Date label
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11.3 UL Label
Issued Date: Mar. 10, 2005
Model No: N121X4-L01
Figure 21 UL Label
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Issued Date: Mar. 10, 2005
Model No: N121X4-L01
12. Appendix
12.1 National Test Lab Requirement
The display module will satisfy all requirements for compliance to UL 60950, 3rd Edition. U.S.A. Information
Technology Equipment.
12.2 Conditions of Acceptability
When installed on the end product, consideration shall be given to the following.
This component has been judged on the basis of the required specification in
of Information Technology Equipment
which would cover the component itself if submitted for listing.
The unit is intended to be supply by SELV and Limited Power Source. Also separated from electrical
parts, which may produce high temperature that could cause ignition by as least 13mm of air or
by a solid barrio of material of V-1 minimum.
The terminals and connectors are suitable for factory wiring only.
A suitable electrical enclosure shall be provided.
, CAN/CSA C22.2 No.60950-00 *UL60950, Third Edition,
The Standard for Safety
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