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- CONTENTS -
REVISION HISTORY
1. GENERAL DESCRIPTION
1.1 OVERVIEW
1.2 FEATURES
1.3 APPLICATION
1.4 GENERAL SPECIFICATIONS
1.5 MECHANICAL SPECIFICATIONS
2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
2.2 ELECTRICAL ABSOLUTE RATINGS
2.2.1 TFT LCD MODULE
2.2.2 BACKLIGHT UNIT
3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE
3.2 BACKLIGHT UNIT
4. BLOCK DIAGRAM
4.1 TFT LCD MODULE
4.2 BACKLIGHT UNIT
5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD MODULE
5.2 BACKLIGHT UNIT
5.3 TIMING DIAGRAM OF LVDS INPUT SIGNAL
5.4 COLOR DATA INPUT ASSIGNMENT
5.5 EDID DATA STRUCTURE
6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
6.2 POWER ON/OFF SEQUENCE
7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
7.2 OPTICAL SPECIFICATIONS
8. PRECAUTIONS
8.1 HANDLING PRECAUTIO NS
8.2 STORAGE PRECAUTIONS
8.3 OPERATION PRECAUTIONS
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Issued Date: Feb. 06, 2001
Model No.: N121X1 - 01
Tentative
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5
16
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The inform ation described in t his technical spe cification is tentat ive and it is possible t o be changed wit hout prior
notice. Please contact CMO ’s representative while your product des ign is based on this specification.
Version 0.1
Page 3
Issued Date: Feb. 06, 2001
Model No.: N121X1 - 01
Tentative
Version Date
Ve r 0.0
Ve r 0.1
Oct.24,’00
Feb.06,’01
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Page
(New)
All
4
10
11
10,11
13
-
REVISION HISTORY
Section Description
Tentative Specification was first issued.
All
Add “Support EDID Structure Version 1 Revision 3”.
1.2
Change Bezel Opening Area
1.4
4.1
5.1
4.1,5.1
5.5
Attached
from 248.8 (H) x 187.3 (V) mm to 250.5 (H) x 188.9 (V) mm.
Add EDID in Block Diagram.
Revise Pin Assignment as supporting EDID.
Change I/F connector
from HIROSE-DF19L-20P- 1H to HIROSE-DF19KR-20P-1H.
Add “5.5 EDID DATA STRUCTURE” section.
Revise Outline Drawings.
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Version 0.1
Page 4
Issued Date: Feb. 06, 2001
Model No.: N121X1 - 01
1. GENERAL DESCRIPTION
1.1 OVERVIEW
N121X1 - 01 is a 12.1” TFT Liquid Cr ystal Display module w ith single CCFL Backlight un it and 20 pins
LVDS interf ace. This module supports 1024 x 768 XGA mode and can display 262,144 co lors. The optimum
viewing angle is at 6 o’clock direction. The inverter module for Backlight is not built in.
1.2 FEATURES
- Thin and light weight
- XGA (1024 x 768 pixels) resolution
- DE (Data Enable) only mode
- 3.3V LVDS (Low Voltage Differential Signaling) interface with 1 pixel/clock
- Support EDID Structure Version 1 Revision 3
1.3 APPLICA TION
- TFT LCD Notebook
Tentative
1.4 GENERAL SPECIFICATI0NS
Item Specification Unit Note
Active Area 245.8 (H) x 184.3 (V) (12.1” diagonal) mm
Bezel Opening Area 250.5 (H) x 188.9 (V) mm
Driver Element a-si TFT active matrix - Pixel Number 1024 x R.G.B. x 768 pixel Pixel Pitch 0.240 (H) x 0.240 (V) mm Pixel Arrangement RGB vertical stripe - Display Colors 262,144 color Transmissive Mode Normally white - Surface Treatment Hard coating (3H), Anti-glare (Haze 12) - -
1.5 MECHANICAL SPECIFICATIONS
Module Size
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
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Item Min. Typ. Max. Unit Note
Horizontal(H) (260.5) 261 (261.5) mm
Vertical(V) (198.5) 199 (199.5) mm
Depth(D) - (5.2) mm
Weight - (360) g -
(1)
(1)
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Version 0.1
Page 5
Issued Date: Feb. 06, 2001
Model No.: N121X1 - 01
Tentative
2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item Symbol
Storage Temperature TST -20 +60 ºC (1)
Operating Ambient T emperature TOP 0 +50 ºC (1), (2)
Shock (Non-Operat ing) S
Vibration (Non-Operating) V
Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta ≦ 40 ºC).
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation of water.
Note (2) The tem perature of panel surface should be 0 ºC Min. and 60 ºC M ax.
Note (3) 2ms, half sine wave, 1 time for ± X, ± Y, ± Z.
Note (4) 10 ~ 500 Hz, 0.5 Hr each X, Y , Z.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough
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so that the module would not be twisted or bent by the fixture.
Relative Humidity (%RH)
100
90
80
60
40
20
5
- (200) G (3), (5)
NOP
- (1.5) G (4), (5)
NOP
Operating Range
Storage Range
Temperature (ºC)
Min. Max.
Value
Unit Note
80 60 -20 40 0 20 -40
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Version 0.1
Page 6
Issued Date: Feb. 06, 2001
Model No.: N121X1 - 01
2.2 ELECTRICAL ABSOLUTE RATINGS
2.2.1 TFT LCD MODULE
Item Symbol
Power Supply Voltage Vcc -0.3 +4.0 V
Logic Input Voltage VIN -0.3 Vcc+0.3 V
2.2.2 BACKLIGHT UNIT
Item Symbol
Lamp Voltage VL - 2.0K V
Lamp Current IL - 6.5 mA
Lamp Frequency FL - 80 KHz
Note (1) Permanent d am age t o the device ma y occur if ma x imu m va lu es ar e e xce ede d. Func tio n oper at i on
should be restricted to the conditions described under Normal Operating Conditions.
Note (2) Specified values are for lamp (Refer to Section 3.2 for further information).
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Min. Max.
Min. Max.
V alue
V alue
Unit Note
(1)
Unit Note
(1), (2), IL = (6.0) mA
RMS
RMS
(1), (2)
Tentative
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Version 0.1
Page 7
Issued Date: Feb. 06, 2001
Model No.: N121X1 - 01
Tentative
3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE Ta = 25 ± 2 ºC
Parameter Symbol
Power Supply Voltage Vcc 3.0 3.3 3.6 V Ripple Voltage VRP - (50) mV Rush Current I
White - TBD mA (3)a
Power Supply Current
LVDS Receiver Threshold
Terminating Resistor RT - 100 - Ohm -
Note (1) The module should be always operated within above ranges.
Note (2) Measurement Conditions:
(High to Low)
(Control Signal)
SW
+12V
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C1
1uF
+3.3V
TBD - TBD mA (3)b
TBD
“H” Level VIL - - +100 mV - Differential Input Voltage for
“L” Level V
R1
47K
R2
1K
47K
VR1
0.01uF
RUSH
Q1 2SK1475
2SK1470
C2
lcc
-100 - - mV -
IH
Q2
Min. Typ. Max.
- TBD A (2)
- TBD mA (3)c
Value
FUSE
Unit Note
C3
1uF
Vcc
(LCD Module Input)
Vcc rising time is 470us
+3.3V
0.9Vcc
0.1Vcc
GND
470us
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Version 0.1
Page 8
Issued Date: Feb. 06, 2001
Model No.: N121X1 - 01
Tentative
Note (3) The specified power supply current is under the conditions at Vcc = 3.3 V, Ta = 25 ± 2 ºC, DC
Current and f
3.2 BACKLIGHT UNIT
Parameter Symbol
Lamp Input Voltage VL (600) V
Lamp Current IL (2.0) (6.0) (6.5) mA
Lamp Turn On Voltage VS
Operating Frequency FL (50) (60) (70) KHz (3)
Lamp Life Time LBL (10,000) - Hrs (5)
Power Consumption PL - (3.6) - W (4), IL = (6.0) mA
Note (1) Lam p cur r ent is measured by utilizing a high frequency current meter as shown below:
Note (2) The voltage shown above should be applied to the lamp for more than 1 second after startup.
Note ( 3) The lamp frequency may generate interf erence with horizontal s ynchronou s frequency from the
Note (4) P
a. White Pattern
c. TBD
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LCD
Module
Otherwise the lamp may not be turned on.
display, and this may cause line flow on the display. In order to avoid interference, the lamp
frequenc y shoul d b e d etach ed from the hori zo ntal s yn chronous freque nc y and its har mo ni c s as f ar
as possible.
= IL ×VL
L
= 60 Hz, whereas a power dissipation check patter n below is displayed.
v
b. TBD
Active Area
Ta = 25 ± 2 ºC
Value
Min. Typ. Max.
- (1000) (25
- (1300) (0
HV (White)
LV (Black)
1
2
A
Current Meter
Inverter
Unit Note
IL = (6.0) mA
RMS
(1)
o
C) V
o
C) V
RMS
(2)
RMS
(2)
RMS
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Version 0.1
Page 9
Issued Date: Feb. 06, 2001
Model No.: N121X1 - 01
Tentative
Note (5) The lifetime of lamp is defi ned as the time wh en it contin ues to oper ate un der the cond ition s at Ta
o
= 25 ±2
(a) When the brightness becomes ≦ 50% of its original value.
(b) When the effective ignition length becomes ≦ 80% of its original value. (Effective ignition
Note (6) The waveform of the voltage output of inverter must be area-symmetric and the design of the
inverter must have specifications for the modularized lamp. The performance of the Backlight,
such as lifetim e or br ig htne ss, is gr eat l y influ e nced by the char a cter isti cs o f t he DC- AC in ver t er for
the lamp. All t he parameters of an in verter should be carefully designed to avoid generating t oo
much current leakage from high voltage output of the inverter. When designing or ordering the
inverter please m ake sure that a poor lighting cau sed by the mismatch of the Backlight and the
inverter (miss-l ighting, flicker, etc.) never occurs . If the above situation is confirmed, the modul e
should be operated in the same manners when it is installed in your instrument.
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C and IL = (2.0) ~ (6.5) mA
length is defined as an area that the brightness is less than 70% compared to the center point.)
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until one of the following events occurs:
RMS
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Version 0.1
Page 10
4. BLOCK DIAGRAM
(
)
4.1 TFT LCD MODULE
Rxin1(+/-)
Rxin2(+/-)
(HIROSE-DF19KR-20P-1H)
INPUT CONNECTOR
CLK(+/-)
Vcc
GND
Data
CLK
V
EDID
EDID
EDID
VL
LAMP CONNECTOR
(JST-BHSR-02VS-1)
4.2 BACKLIGHT UNIT
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LVDS INPUT /
TIMING CONTROLLER
DC/DC CONVERTER &
REFERENCE VOLTAGE
GENERATOR
EDID
EEPROM
Issued Date: Feb. 06, 2001
Model No.: N121X1 - 01
Tentative
SCAN DRIVER IC
TFT LCD PANEL
DATA DRIVER IC
BACKLIGHT UNIT
1 HV (White)
2 LV
(1024x3x768)
Black
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5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD MODULE
Pin Symbol Description Polarity Remark
1 Vcc Power Supply +3.3 V 2 Vcc Power Supply +3.3 V 3 Vss Ground 4 Vss Ground 5 Rxin0- LVDS Differential Data Input Negative
6 Rxin0+ LVDS Differential Data Input Positive
7 Vss Ground 8 Rxin1- LVDS Differential Data Input Negative
9 Rxin1+ LVDS Differential Data Input Positive
10 Vss Ground 11 Rxin2- LVDS Differential Data Input Negative
12 Rxin2+ LVDS Differential Data Input Positive
13 Vss Ground 14 CLK- LVDS Clock Data Input Negative
15 CLK+ LVDS Clock Data Input Positive
16 Vss Ground 17 V
18 NC Non-Connection 19 CLK
20 DATA
Note (1) Connector Part No.: HIROSE-DF19KR-20P-1H or equivalent
Note (2) User’s connector Part No: HI ROSE-DF19G-20S-1C or equivalent
Note (3) The first pixel is even.
5.2 BACKLIGHT UNIT
Note (1) Connector Part No.: JST-BHSR-02VS-1 or equivalent
Note (2) User’s connector Part No .: JST-SM02B-BHSS-1 or equivalent
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Pin Symbol Description Color
1 HV High Voltage White
2 LV Ground Black
DDC +3.3 V Power -
EDID
DDC Clock -
EDID
DDC Data -
EDID
Issued Date: Feb. 06, 2001
Model No.: N121X1 - 01
Tentative
R0~R5,G0
G1~G5,B0,B1
B2~B5,Hsync,Vsync,DE,
LVDS Level
5.3 TIMING DIAGRAM OF LVDS INPUT SIGNAL
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CLK+
Rxin2
Rxin1
Rxin0
T/7
IN20 IN19 IN18 IN17 IN16 IN15 IN14
DE B5 B4 B3 B2 Vsync Hsync
IN13 IN12 IN11 IN10 IN9 IN8 IN7
B1 G4 G3 G2 G1 B0 G5
IN6 IN5 IN4 IN3 IN2 IN1 IN0
G0 R3 R2 R1 R0 R5 R4
Signal for 1 DCLK Cycle (T)
11 / 22
Version 0.1
Page 12
Issued Date: Feb. 06, 2001
Model No.: N121X1 - 01
Tentative
5.4 COLOR DATA INPUT ASSIGNMENT
The brightne ss of eac h pr imary c olor (r ed, gr een a nd blue) is based on the 6 -bit gra y scale data input f or
the color. The higher the binary input the brighter the color. The table below provides the assignment of
color versus data input.
Data Signal
Color
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Black
Red
Green
Basic
Colors
Gray
Scale
Of
Red
Gray
Scale
Of
Green
Gray
Scale
Of
Blue
Note (1) 0: Low Level Voltage, 1: High Level Voltage
Blue
Cyan
Magenta
Yellow
White
Red(0)/Dark
Red(1)
Red(2)
:
:
Red(61)
Red(62)
Red(63)
Green(0)/Dark
Green(1)
Green(2)
:
:
Green(61)
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Green(62)
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Green(63)
Blue(0)/Dark
Blue(1)
Blue(2)
:
:
Blue(61)
Blue(62)
Blue(63)
0
1
0
0
0
1
1
1
0
0
0
:
:
1
1
1
0
0
0
:
:
0
0
0
0
0
0
:
:
0
0
0
Red Green Blue
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
0
0
:
:
0
0
0
0
0
0
:
:
0
0
0
0
1
0
:
:
1
0
1
12 / 22
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Version 0.1
Page 13
Issued Date: Feb. 06, 2001
Model No.: N121X1 - 01
Tentative
5.5 EDID DATA STRUCTURE
The EDID (Exten ded Display Identi fication Data) data formats are to sup port displays as define d in the
VESA Plug & Display and FPDI standards.
Byte #
(decimal)
10 0A ID product code (N121X1 = ”50104”) B8 10111000
12 0C ID S/N (fixed “0”) 00 00000000
13 0D ID S/N (fixed “0”) 00 00000000
14 0E ID S/N (fixed “0”) 00 00000000
15 0F ID S/N (fixed “0”) 00 00000000
16 10 Week of manufacture (fixed “0”) 00 00000000
17 11 Year of manufacture (fixed “0”) 00 00000000
18 12 EDID structure version # (“1”) 01 00000001
19 13 EDID revision # (“3”) 03 00000011
20 14 Video I/P definition (“digital”) 80 10000000
21 15 Max H image size (“24 cm”) 18 00011100
22 16 Max V image size (“18 cm”) 12 00010101
23 17 Display Gamma (Gamma = ”2.2”) 78 01111000
24 18 Feature support (“RGB, preferred timing”) 0A 00001010
25 19 Red/Green (Rx1, Rx0, Ry1, Ry0, Gx1, Gx0, Gy1, Gy0) 00 00000000
26 1A Blue/W hite (Bx1, Bx0, By1, By0, Wx1, Wx0, Wy1, Wy0) 05 00000101
27 1B Red-x (Rx = “TBD”, “0000000000” first for TBD) 00 00000000
28 1C Red-y (Ry = “TBD”, “0000000000” first for TBD) 00 00000000
29 1D Green-x (Gx = ”TBD”, “0000000000” first for TBD) 00 00000000
30 1E Green-y (Gy = ”TBD”, “0000000000” first for TBD) 00 00000000
31 1F Blue-x (Bx = ”TBD”, “0000000000” first for TBD) 00 00000000
32 20 Blue-y (By = ”TBD”, “000 0000000” first for TBD) 00 00000000
33 21 White-x (Wx = ”0.310”) 4F 01001111
34 22 White-y (Wy = ”0.330” ) 54 01010100
35 23 Established timings 1 00 00000000
36 24 Established timings 2 00 00000000
37 25 Manufacturer’s reserved timings 00 00000000
38 26 Standard timing ID # 1 01 00000001
39 27 Standard timing ID # 1 01 00000001
40 28 Standard timing ID # 2 01 00000001
41 29 Standard timing ID # 2 01 00000001
42 2A Standard timing ID # 3 01 00000001
43 2B Standard timing ID # 3 01 00000001
44 2C Standard timing ID # 4 01 00000001
45 2D Standard timing ID # 4 01 00000001
46 2E Standard timing ID # 5 01 00000001
47 2F Standard timing ID # 5 01 00000001
Byte #
(hex)
0 00 Header 00 00000000
1 01 Header FF 11111111
2 02 Header FF 11111111
3 03 Header FF 11111111
4 04 Header FF 11111111
5 05 Header FF 11111111
6 06 Header FF 11111111
7 07 Header 00 00000000
8 08 EISA ID manufacturer name (“TBD”, “0000” first for TBD) 00 00000000
9 09 EISA ID manufacturer name (Compressed ASCII) 00 00000000
11 0B ID product code (hex LSB first) C3 11000011
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Field Name and Comments
Value
(hex)
Value
(binary)
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Version 0.1
Page 14
Issued Date: Feb. 06, 2001
Model No.: N121X1 - 01
Tentative
Byte #
(decimal)
48 30 Standard timing ID # 6 01 00000001
49 31 Standard timing ID # 6 01 00000001
50 32 Standard timing ID # 7 01 00000001
51 33 Standard timing ID # 7 01 00000001
52 34 Standard timing ID # 8 01 00000001
53 35 Standard timing ID # 8 01 00000001
54 36 Detailed timing description # 1 Pixel clock (“65 MHz”) 64 01100100
55 37 # 1 Pixel clock (hex LSB first) 19 00011001
56 38 # 1 H active (“1024”) 00 00000000
57 39 # 1 H blank (“320”) 40 01000000
58 3A # 1 H active : H blank (“1024 : 320”) 41 01000001
59 3B # 1 V active (”768”) 00 00000000
60 3C # 1 V blank (”38”) 26 00100110
61 3D # 1 V active : V blank ( ” 768 : 38”) 30 00110000
62 3E # 1 H sync offset (”24”) 18 00011000
63 3F # 1 H sync pulse width (”136”) 88 10001000
64 40 # 1 V sync offset : V sync pulse width (”3 : 6”) 36 00110110
65 41
66 42 # 1 H image size (”245 mm”) F5 11110101
67 43 # 1 V image size (”184 mm”) B8 10111000
68 44 # 1 H image size : V image size (”245 : 184”) 00 00000000
69 45 # 1 H boarder ( ”0”) 00 00000000
70 46 # 1 V boarder (”0”) 00 00000000
71 47 # 1 Flags (”Non-Interlace, No n- Stereo, Digital Separate”) 18 00011000
72 48 Detailed timing description # 2 (Flag) 00 00000000
73 49 # 2 Flag 00 00000000
74 4A # 2 Reserved 00 00000000
75 4B # 2 Dummy data type tag (Model Name “N121X1”, ASIC) FE 111111110
76 4C # 2 Flag 00 00000000
77 4D # 2 1st Dummy descriptor data (“N”) 4E 01001110
78 4E # 2 2nd Dummy descriptor data (“1”) 31 00110001
79 4F # 2 3rd Dummy descriptor data (“2”) 32 00110010
80 50 # 2 4th Dummy descriptor data (“1”) 31 00110001
81 51 # 2 5th Dummy descriptor data (“X”) 58 01011000
82 52 # 2 6th Dummy descriptor data (“1”) 31 00110001
83 53 # 2 7th Dummy descriptor data 00 00000000
84 54 # 2 8th Dummy descriptor data 00 00000000
85 55 # 2 9th Dummy descriptor data 00 00000000
86 56 # 2 10th Dummy descriptor data 00 00000000
87 57 # 2 11th Dummy descriptor data 00 00000000
88 58 # 2 New line chara cter # 2 indicates end of S/N 0A 00001010
89 59 # 2 Padding wit h “ B lank” character 20 00100000
90 5A Detailed timing description # 3 (Flag) 00 00000000
91 5B # 3 Flag 00 00000000
92 5C # 3 Reserved 00 00000000
93 5D # 3 Dummy data type tag 10 00010000
94 5E # 3 Flag 00 00000000
95 5F # 3 1st Dummy descriptor data 00 00000000
96 60 # 3 2nd Dummy descriptor data 00 00000000
97 61 # 3 3rd Dummy descriptor data 00 00000000
98 62 # 3 4th Dummy descriptor data 00 00000000
Byte #
(hex)
# 1 H sync offset : H sync pulse width : V sync offset : V sync width
(”24 : 136 : 3 : 6”)
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Field Name and Comments
Value
(hex)
(binary)
00 00000000
Value
14 / 22
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notice. Please contact CMO ’s representative while your product des ign is based on this specification.
Version 0.1
Page 15
Issued Date: Feb. 06, 2001
Model No.: N121X1 - 01
Tentative
Byte #
(decimal)
99 63 # 3 5th Dummy descriptor data 00 00000000
100 64 # 3 6th Dummy descriptor data 00 00000000
101 65 # 3 7th Dummy descriptor data 00 00000000
102 66 # 3 8th Dummy descriptor data 00 00000000
103 67 # 3 9th Dummy descriptor data 00 00000000
104 68 # 3 10th Dummy descriptor data 00 00000000
105 69 # 3 11th Dummy descriptor data 00 00000000
106 6A # 3 New line character # 3 indicates end of S/N 0A 00001010
107 6B # 3 Padding with “Blank” character 20 00100000
108 6C Detailed timing description # 4 (Flag) 00 00000000
109 6D # 4 Flag 00 000000 00
110 6E # 4 Reserved 00 00000000
111 6F # 4 Dummy data type tag 10 00010000
112 70 # 4 Flag 00 00000000
113 71 # 4 1st Dummy descriptor data 00 00000000
114 72 # 4 2nd Dummy descriptor data 00 00000000
115 73 # 4 3rd Dummy descriptor data 00 00000000
116 74 # 4 4th Dummy descriptor data 00 00000000
117 75 # 4 5th Dummy descriptor data 00 00000000
118 76 # 4 6th Dummy descriptor data 00 00000000
119 77 # 4 7th Dummy descriptor data 00 00000000
120 78 # 4 8th Dummy descriptor data 00 00000000
121 79 # 4 9th Dummy descriptor data 00 00000000
122 7A # 4 10th Dummy descriptor data 00 00000000
123 7B # 4 11th Dummy descriptor data 00 00000000
124 7C # 4 New line character # 4 indicate s end of S/N 0A 00001010
125 7D # 4 Padding with “Blank” character 20 00100000
126 7E Extension flag 00 00000000
127 7F Checksum AD 10101101
Byte #
(hex)
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Field Name and Comments
Value
(hex)
Value
(binary)
15 / 22
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Version 0.1
Page 16
Issued Date: Feb. 06, 2001
Model No.: N121X1 - 01
Tentative
6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram
Signal Item Symbol Min. Typ. Max. Unit Note
Frequency 1/Tc - 65 TBD MHz -
Clock
Data
Data Enable Setup Time TES TBD - nsec (1)
Frame Frequency Cycle TV TBD 806 TBD lines Vertical Active Display Term Display Period TVD - 768 - lines One Line Scanning Time Cycle TH TBD 1344 TBD clocks (2)
Horizontal Active Display Term Display Period THD - 1024 - clocks -
Note (1) Because this module is operated by DE only mode, Hsync and Vsync input signals should be set
to low logic level or ground. Otherwise, this module would oper ate abnormally.
Note (2) The dur ation of DE signal must be longer than 1 clock period at every horizontal sync. period.
High Time TCH TBD - - nsec -
Low Time T
Setup Time TDS TBD - - nsec -
Hold Time T
TBD - - nsec -
CL
TBD - - nsec -
DH
INPUT SIGNAL TIMING DIAGRAM
DE
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DCLK
DE
DA TA
SIGNALS
DCLK
DISPLA Y
DATA
DE
T
C
TC
TDS
TES
TH
THD
V alid display data (1024 pixels)
TCL TCH
TDH
50%
50%
50%
.
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Version 0.1
Page 17
Issued Date: Feb. 06, 2001
Model No.: N121X1 - 01
6.2 POWER ON/OFF SEQUENCE
Power Supply
for LCD, Vcc
-
Interface Signal
(LVDS Signal of
Transmitter), V
-
Power for Lamp
Timing S pecifications:
0 < t1 ≦ (10) m sec
0 < t2 ≦ (50) m sec
0 < t3 ≦ (50) m sec
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Note (1) Please avoid floating state of interface signal at invalid period.
Note (2) When the inter face signal is invalid, be sure to pull down the power supply of LCD Vcc to 0 V.
Note (3) The Backlight inverter power must be turned on after the power supply for the logic and the
interface signal is valid. The Backlight inverter power must be turned off before the power supply
for the logic and the interface signal is invalid.
0V
0V
I
t4 ≧ 1 sec
t5 ≧ TBD
t6 ≧ TBD
Power On
90%
10%
t1
Valid Data
ON OFF OFF
Power Off
90%
t3 t2
t6 t5
10%
Restart
t4
10%
Tentative
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Version 0.1
Page 18
Issued Date: Feb. 06, 2001
Model No.: N121X1 - 01
Tentative
7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
Item Symbol Value Unit
Ambient T emperature Ta
Ambient Humidity Ha
Supply V olt age VCC 3.3 V
Input Signal According to typic al value in "3. ELECTRICAL CHARACTERISTICS"
Inverter Current IL (6.0) mA
Inverter Driving Frequency FL (55) KHz
Inverter TBD
The measurement methods of optical characteristics are shown in Section 7.2. The following items
should be measured under the test conditions described in Section 7.1 and stable environment shown in
Note (6).
25±2
50±10
7.2 OPTICAL SPECIFICATIONS
Item Symbol Condition Min. Typ. Max. Unit Note
Contrast Ratio CR (150) (200) - - (2), (6)
Response Time
Average Luminance of White L
White Variation
Cross Talk CT - - (4.0) % (5), (6)
Red
Color
Chromaticity
Viewing Angle
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Green
Blue
White
Horizontal
Vertical
TR - (15) (30) ms
T
- (35) (50) ms
F
(120) (150) - cd/m2 (4), (6)
AVE
δW
θ
Rx TBD Ry TBD -
Gx TBD -
Gy TBD Bx TBD -
By TBD Wx (0.31) Wy
θx+
θ
-
x
θY+
-
θ
Y
=0°, θY =0°
x
Viewing Normal Angle
CR≥10
- (1.4) (1.6) - (6), (7)
(0.33) 40 45 40 45 10 15 30 35 -
o
C
%RH
Deg.
(3)
(1), (6)
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Version 0.1
Page 19
Note (1) Definition of Vi ewi ng Angle (θx, θy):
Issued Date: Feb. 06, 2001
Model No.: N121X1 - 01
Tentative
Note (2) Definition of Contrast Ratio (CR):
θX- = 90º
6 o’cloc k
y-
θ
= 90º
The contrast ratio can be calculated by the following expression.
Contrast Ratio (CR) = L63 / L0
L63: Luminance of gray level 63
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L 0: Luminance of gray level 0
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CR = CR (5)
x-
y-
Normal
θ
x = θy = 0º
θy- θy+
θx-
θx+
12 o’clock direction
y+
y+ = 90º
θ
x+
θX+ = 90º
CR (X) is corresponding to the Contrast Ratio of the point X at Figure in Note (7).
Note (3) Definition of Response Time (T
100%
90%
Optical
Response
10%
0%
R
T
R
, TF):
Time
T
F
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Version 0.1
Page 20
Issued Date: Feb. 06, 2001
A
(
)
A
(
)
(
)
Model No.: N121X1 - 01
Tentative
Note (4) Definition of Average Luminance of White (L
Measure the luminance of gray level 63 at 5 points
L
= [L (1)+ L (2)+ L (3)+ L (4)+ L (5)] / 5
AVE
L (x) is corresponding to the luminance of the point X at Figur e in N ote (7).
Note (5) Definition of Cross Talk (CT):
CT = | Y
Where:
Y
A, L
Y
A, D
Note (6) Measurement Setup:
(0, 0)
(D/8,W/2)
(D/2,7W/8)
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The LCD module should be stabilized at given temperature for 20 minutes to avoid abrupt
temperature change during measuring. In order to stabilize the luminance, the measurement
should be executed after lighting Back light for 20 minutes in a windless room.
– YA | / YA × 100 (%)
B
= Luminance of measured location without gray level 0 pattern (cd/m2)
Y
A
Y
= Luminance of measured location with gray level 0 pattern (cd/m2)
B
ctive Area
Gray 32
D,W
LCD Module
LCD Panel
Center of the Screen
500 mm
):
AVE
Y
(D/2,W/8)
A, U
(D/4,W/4)
Y
(D/8,W/2)
Y
(7D/8,W/2)
A, R
B, L
Y
(D/2,7W/8)
B, D
Field of View = 2º
0, 0
ctive Area
Gray 0
Gray 32
Y
(D/2,W/8)
B, U
Y
(7D/8,W/2)
B, R
(3D/4,3W/4)
D,W
Photometer
(TOPCON BM-5A )
Light Shield Room
(Ambient Luminance < 2 lux)
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Note (7) D efinition of W hite Variation (δW):
Measure the luminance of gray level 63 at 5 points
δW = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]
W
W/4
W/2
3W/4
V e rtical Line
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Issued Date: Feb. 06, 2001
Model No.: N121X1 - 01
Horizontal Line
D
D/4 D/2 3D/4
12
: T e st Point
X
X=1 to 5
3
5
4
Active Area
Tentative
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Version 0.1
Page 22
Issued Date: Feb. 06, 2001
Model No.: N121X1 - 01
8. PRECAUTIONS
8.1 HANDLING PRECAUTIONS
(1) The modul e should be assemb led into the system firmly by using ev ery mounting ho le. Be careful not
to twist or bend the module .
(2) While assem bling or instal ling modules, it can only be in t he clean area. The dust and oil may cause
electrical short or damage the polarizer.
(3) Use fingerstalls or soft gloves in order to keep display clean during the incoming inspection and
assembly process.
(4) Do not press or scratch the surface harder than a HB pencil lead on the panel because the polarizer is
very soft and easily scratched.
(5) If the surface of the p olarizer is dirty, please clean it b y some ab sor bent c otto n or soft clot h. D o not u se
Ketone type materials (ex. Acetone), Ethyl alcohol, Toluene, Ethyl acid or Methyl chloride. It might
permanently damage the polarizer due to chemical reaction.
(6) Wipe off water droplets or oil immediately. Staining and discoloration may occur if they left on panel for
a long time.
(7) If the liquid crystal material leak s from the panel, it should be kept aw ay from the e yes or mouth. In
case of contacting with hands, legs or clothes, it must be washed away thoroughly with soap.
(8) Protect the module from static electricity, it may cause damage to the C-MOS Gate Array IC.
(9) Do not disassemble the module.
(10) Do not pull or fold the lamp wire.
(11) Pins of I/F connector should not be touched directly with bare hands.
8.2 STORAGE PRECAUTIONS
(1) High temperature or humidit y may reduce t he performance of module. Please store LCD module within
(2) It is dangerous that moisture come into or contacted the LCD module, because the moisture may
(3) It may reduce the displa y quality if the ambient temperature is lower than 10 ºC. For example, the
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the specified storage conditions.
damage LCD module when it is oper ating.
response time will become slowly, and the starting voltage of lamp will be higher than the room
temperature.
Tentative
8.3 OPERATION PRECAUTIONS
(1) Do not pull the I/F connector in or out while the module is operating.
(2) Always follow the correct power on/off sequence when LCD module is connecting and operating. This
can prevent the CMOS LSI chips from damage dur ing latch-up.
(3) The startup voltage of Backlight is approximately 1000 Volts. It may cause electrical shock while
assembling with inverter. Do not disassemble the module or insert anything into the Backlight unit.
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Page 23
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DISCONNECT THE ELECTRIC
RISK OF ELECTRIC SHOCK.
POWER BEFORE SERVICING.
HIGH VOLTAGE
CAUTION
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