Analog In / Serial Data Out
µProcessor Compatible Outputs
Speech Discrimination Ability
Low Power Operation
SERIAL OUTPUT
PORT (6-BITS)
LATC H
FREQUENCY
COUNTER
RESET
TIME
DAT A OUT
012345
TIME
V
IRQ
AVAILABLE
PACKAGES
MX613DW
16-pin SOIC
BIAS
14-pin PDIP
MX613P
The MX613 is a wide-band, ‘N-Tone’ non-predictive tone decoder that measures telephone system call progress
tones in PABX, Pay/Feature-Phone, Fax and Modem systems.
Adhering to Must/Must-Not Decode limits and able to measure inband frequencies in outband modulation, this
decoder measures the frequency of input signals in the range 300 to 2,150Hz. The result of each measurement is
presented to a system µProcessor as a 6-bit serial word.
The decode frequency range, which covers the world's call progress application spectrum, is processed internally
as two bands: LO = 300 to 660Hz and HI = 900 to 2150Hz. Frequency measurement is achieved by counting the
number of cycles in a set time period
(LO = 39.47ms or HI = 13.16ms). Bad signal/level quality or NOTONEresults in a count-abort, timing-reset and no
output from the decoder.
Front-end filtering is achieved using our patented Auto-Correlator. Current frequency information is output for the
µProcessor using a Serial Data, Clock and Interrupt interface.
Data from the MX613 should be processed by a µProcessor whose algorithms are able to recognize the
frequency, sequence and/or cadence of input signals as national call progress information; e.g.: ‘Dial,’ ‘Busy,’
‘Number-Unobtainable,’ ‘Ringing’ and automatic tones used by fax and modem systems. Software can be simply
configured to reject speech frequencies.
Available in SOIC and PDIP packages, this low-cost, mixed signal IC has a typical power requirement of less
than 1mA at 3 volts and utilizes a telecom-system clock input of 3.579545MHz to maintain frequency accuracy.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USAAll trademarks and service marks are held by their respective companies
Page 2
Global Call Progress Tone Detector2MX613 Preliminary Information
Pin NumberFunction
MX613DW
1
2
3
4
5
6
MX613P
1
2
3
4
5
6
Xtal/Clock: The input to the on-chip clock oscillator inverter. A 3.579545MHz Xtal or
externally derived telephone system clock (f
) should be connected here. Operation
XTAL
of the MX613 without a suitable Xtal/Clock input may cause device damage.
Xtal: The output of the on-chip clock oscillator inverter. See Figure 2.
No internal connection.
V
: The internal circuitry bias line, held at VDD/2 this pin must be decoupled to VSS.
BIAS
Level In: The input for level discrimination. This input is internally biased to V
. Signals
BIAS
must be a.c. coupled, and the audio signal must be fed to both this pin and the Signal In
pin. Correct level detection determines the operation of this device (see Principles of
Decoder Operation). But if you wish to disregard the amplitude of the input levels, the
MX613 may be permanently enabled by pulling this pin to VDD and disabled by pulling to
VSS.
Signal In: The input for frequency discrimination and decoding. This input is internally
biased to V
. Signals must be a.c. coupled. The audio signal must be fed to both this
BIAS
pin and the Level In pin.
7
8
9
10
11
12
13
14
7
8
9
10
11
12
No internal connection.
VSS: Signal ground (GND).
No internal connection.
No internal connection.
IRQ: This Interrupt Request output from the MX613 is ‘wire-OR able’ allowing the
interrupt outputs of other peripherals to be combined and connected to the Interrupt input
of a µProcessor. This input has a low-impedance pulldown to V
when active and a high-
SS
impedance when inactive. An interrupt is produced on completion of a HI or LO frequency
measurement.
Serial Clock: The serial clock from the µProcessor. Data Out is clocked into the
µProcessor on the rising edge of the Serial Clock. See Data-Read Timing diagram.
Chip Select: A logic “0” at this input will select this device.
Data Out: The serial data output. Under the control of the Chip Select and Serial Clock
inputs, data should be read from this output in 6-bit blocks MSB (Bit-5) first.
If 8 serial clock pulses are applied, two additional logic “0s” will be output after Bit-0.
15
16
13
14
No internal connection.
VDD: Positive supply input. A single, stable supply is required. Levels and voltages within
the MX613 are dependent upon this supply. This pin should be decoupled to VSS by a
capacitor located close to the MX613 pins.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USAAll trademarks and service marks are held by their respective companies
Page 3
Global Call Progress Tone Detector3MX613 Preliminary Information
Application Information
1
R
2
X
1
C
5
2
C
6
XT AL/CLOCK
XT AL
1
2
3
V
AUDIO SIGNAL
C
2
C
1
BIAS
LEVEL IN
SIGNAL IN
4
5
6
7
C
3
Notes
(1) The Xtal/Clock input may be driven from the host telephone
system's 3.579545MHz clock; if a Xtal drive is required, the
configuration shown in the INSET is recommended.
(2) The audio signal should be input to both Signal In and Level In
pins via separate coupling capacitors. If it is wished to operate
the device with disregard to on-chip level thresholds and
permanently enable the MX613, the Level In pin should be held
at VDD.
To disable the MX613 the Level In pin should be held at VSS.
Level thresholds are preset internally.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USAAll trademarks and service marks are held by their respective companies
Page 4
Global Call Progress Tone Detector4MX613 Preliminary Information
Application Information ......
Principles of Decoder Operation
Level Detection
Because level and frequency discrimination operations tak e place in parallel, the audio signal should, under normal
circumstances, be input to both Signal In and Lev el In pins via coupling capacitors.
If the input signal level (Level In) is outside the preset ‘Must/Must Not Decode’ thresholds (see Specifications), the
Universal Call Progress Decoder will be disabled.
If it is wished to disregard signal input
may be permanently enabled by holding the Level In pin at VDD.
The MX613 can disabled by pulling Level In to VSS.
NOTONE Recognition
The NOTONE condition can be recognized using µProcessor software timing as below.
a. Set the µP timer period to a period greater than the relevant frequency-band measurement period (13.16ms
or 39.47ms).
b. Each ‘Tone Measurement Complete’ interrupt from the MX613 must reset the µP timer.
c. With NOTONE or white noise at the decoder input, the MX613 on-chip timer will be continually reset.
i. ‘Tone Measurement Complete' interrupt will not occur - the µP timer will run.
ii. The µP Timer time-out can be considered as a NOTONE indication.
Level InTimerIRQData Out
In LimitsRunningEnabledEnabled
Out of LimitsResetDisabledDisabled(frozen to previous bit-5 level
V
DD
V
SS
Running/ResetEnabled/DisabledEnabled(dependent upon Quality measurement)
ResetDisabledDisabled(frozen to previous bit-5 level)
levels
at the Level In pin and attempt to decode under all conditions, the decoder
Frequency Band Discrimination
The input signal is amplified by a self-biased (zero-crossing) inverting amplifier and then ‘filtered’ to remove highfrequency noise and jitter.
High (HI) and Low (LO) counters are employed to determine the input frequency band (HI = 900Hz to 2150Hz,
LO = 300Hz to 660Hz).
If the input frequency is in the LO Band, the device will operate as a LO Band decoder and will remain so until a
HI frequency signal is detected. If the input frequency is in the HI Band, the device will operate as a HI Band
decoder and will remain so until a LO frequency signal is detected.
Frequency band monitoring is continuous with the band selection taking place every 9.8ms. It will therefore take
9.8ms from Power-Up to set up the initial correct decode frequency band.
On-Chip Timer Operation
For frequency measurement, the MX613 counts the number of input cycles in a fixed time period. This fixed
period, measured by the continuous on-chip timer, is set to 13.16ms for HI Band inputs and 39.47ms for LO Band
inputs.
When the timer expires the following actions take place:
a. A HI or LO (“1” or “0”) band indication bit is latched into Bit-5 of the Serial Output Port.
b. The Frequency Counter count of 5-bits is latched into the Serial Output Port (Bit-4 [MSB] to Bit-0). The
Serial Output Port Contains 6-bits, if 8 Serial Clock edges are employed, two extra “0s”, which should be
ignored, will be output last.
c. An interrupt is generated (IRQ) to the µProcessor. The contents of the Serial Output Port should be read
before the next interrupt is expected; if not data will be overwritten.
When the Chip Select input is set to “0” the interrupt is reset.
The On-Chip Timer and Frequency Counter will be reset in mid-count, and therefore unable to allow a valid
measurement, under the following conditions:
a. A change of decode frequency band.
b. Decoder disabled; signal input level out of specification or Level Detect input set to VSS.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USAAll trademarks and service marks are held by their respective companies
Page 5
Global Call Progress Tone Detector5MX613 Preliminary Information
Application Information ......
N = int (Frequency x Measurement Period)
Measurement Period= 39.47ms for Low Band(300Hz to 660Hz)
= 13.16ms for High Band(900Hz to 2150Hz)
Note: For input frequencies of between 661Hz and 899Hz the MX613 will give no reliable output.
When a ‘correct’ decode has been allowed and an interrupt generated, a 6-bit data word is presented at the Serial Output
Port. This 6-bit word indicates the input frequency's band (Bit 5) and value ‘N’ as indicated below.
Bit 5
Output
First
Band Bit (5)MSB (4)(3)(2)(1)LSB (0)
HI-“1”/LO-“0”Bits 0 to 4 represent the measured frequency in the selected band
Bits
0 to 4
=
N
When a ‘correct’ decode has been allowed and an interrupt generated, a 6-bit data word will be presented at the Serial
Output Port. This 6-bit word indicates the input frequency's band and value as described below.
As an example, the following binary-word presented at the Serial Output Port (1 1 0 1 1 0) will indicate a frequency
in the HI Band of between 1680Hz and 1740Hz (Bit-5 = “1” = HI, ‘N’ = 22).
LO BandHI BandNB5B4B3B2B1B0LO BandHI BandNB5B4B3B2B1B
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USAAll trademarks and service marks are held by their respective companies
Page 6
Global Call Progress Tone Detector6MX613 Preliminary Information
Application Information ......
Decoder Timing
CHIP SELECT
t
CSE
SERIAL CLOCK
t
DE
DA TA OUT
TRI-STATE
t
IR
BIT 5
IRQ
Figure 4 - Data-Read Timing
Decoder Timing Characteristics
With reference to Figure 4,
Data-Read Timing
BIT 0
t
CSH
t
HIZ
t
CYC
t
t
CDS
PWL
BIT 4
t
PWH
t
DH
.
CharacteristicsMin.Typ.Max.Unit
t
PWH
t
PWL
t
CYC
t
CSE
t
CSH
t
DH
t
CDS
t
IR
t
DE
t
HIZ
Serial Clock “High” Pulse Width250--ns
Serial Clock “Low” Pulse Width250--ns
Serial Clock-Cycle Time600--ns
Chip Select Low to Clock “High” Edge450--ns
Last Clock “High” Edge to CS “High”600--ns
Data Out Hold Time0--ns
Clock Edge to Data Out Set Time--200ns
Interrupt (IRQ) Reset Time--200ns
Chip Select “Low” to Data Enable--200ns
Chip Select “High” to Output Tri-State--1000ns
Notes
1 Data is output bit 5 first. Bit 5 can be clocked into the µProcessor by the first Serial Clock rising edge.
If 8 Serial Clock pulses are employed the last 2 data-bits will be “0” and should be ignored by the software.
2 Chip Select should be used to react to Interrupts and then returned to a logic “1”.
If Chip Select stays low there will be no further Interrupts and no Data Output update.