Datasheet MX589DW, MX589P Datasheet (MX COM)

DATA BULLETIN

MX589

High Speed GMSK Modem



1998 MX-COM, Inc. www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: [phone] Doc. # 20480103.010

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

Features Applications

•

Data Rates from 4kbps to 64kbps

•

Full or Half Duplex Gaussian Minimum Shift

Keying (GMSK) Operation

•

Selectable BT: (0.3 or 0.5)

•

Low Power

3.0V, 20kbps, 1.5mA typ.

5.0V, 64kbps, 4.0mA typ.

•

Low Current Non-DSP Solution

•

Small TSSOP size fits PCMCIA / PC CARDs

•

Point of Sale Terminals

•

Low Power Wireless Data Link for

PCs, Laptops, and Printers

•

Data for GPS/Differential GPS

•

Portable Wireless Data Applications

Cellular Digital Packet Data (CDPD)
Mobitex Mobile Data System

TX PS

RX PS

BT

TX D ATA

ClkDIVA

PLLacq
RXDCacq

RX SIGNAL IN
RX FEEDBACK

CLOCK

DIVIDER

XTAL/CLOCK

TX ENABLE

XTAL

V

DD

V

BIAS

V

BIAS

V

BIAS

V

SS

RXHold

RX CLK

TX CLK

TX OUT

RX DAT A

RX S/N

DOC1 DOC2

ClkDIVB

RX CIRCUIT

CONTROL

RX

FILTER

DA TA RETIME &

LEVEL SHIFT

TX

FILTER

RX S/N

DETECTION

RX CLOCK

RX DC LEVEL

MEASURE

+

-

V

BIAS

RX DATA

DETECTION

The MX589 is a single-chip synchronous modem designed for Wireless Data Applications. Employing Gaussian Minimum
shift Keying (GMSK) baseband modulation, the MX589 features a wide range of available data rates: 4k to 64kbps. Data
Rates and the choice of BT (0.3 or 0.5) are pin programmable to provide for different system requirements.

The Tx and Rx digital data interfaces are bit serial, synchronized to Tx and Rx data clocks generated by the modem.
Separate Tx and Rx Powersave inputs allow full or half-duplex operation. Rx input levels can be set by suitable AC and
DC level adjusting circuitry built with external components around an on-chip Rx Input Amplifier.

Acquisition, Lock, and Hold of Rx data signals are made easier and faster by the use of Rx Control Inputs to clamp,
detect, and /or hold input data levels and can be set by the µProcessor as required. The Rx S/N output provides an
indication of the quality of the received signal.

The MX589 may be used with a 3.0V to 5.5V power supply and is available in the following packages: 24-pin TSSOP
(MX589TN), 24-pin SOIC (MX589DW), and 24-pin PDIP (MX589P).

High Speed GMSK Modem 4k to 64kbps 2 MX589

1998 MX-COM, Inc. www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: [phone] Doc. # 20480103.010

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

Contents

Section Page

1 Block Diagram................................................................................................................................. 3

2 Signal List ....................................................................................................................................... 4

3 External Components..................................................................................................................... 5

4 General Description........................................................................................................................ 7

4.1 Clock Oscillator Divider .......................................................................................................................... 7

4.2 Receive .................................................................................................................................................. 7

4.2.1 Rx Signal Path Description..........................................................................................................................7

4.2.2 Rx Circuit Control Modes ............................................................................................................................8

4.2.3 Rx Clock Extraction.....................................................................................................................................9

4.2.4 Rx Data Extraction ......................................................................................................................................9

4.2.5 Rx S/N Detection.........................................................................................................................................9

4.2.6 Rx Signal Quality........................................................................................................................................10

4.3 Transmit ................................................................................................................................................ 11

4.3.1 TX Signal Path Description ........................................................................................................................11

4.4 Data Formats......................................................................................................................................... 13

4.5 Acquisition and Hold Modes.................................................................................................................. 13

5 Application..................................................................................................................................... 14

5.1 Radio Channel Requirements ............................................................................................................... 14

5.1.1 Bit Rate, BT, and Bandwidth......................................................................................................................14

5.1.2 FM Modulator, Demodulator and IF ...........................................................................................................14

5.1.3 Two-Point Modulation.................................................................................................................................15

5.2 AC Coupling of Tx and Rx Signals........................................................................................................ 16

6 Performance Specifications ......................................................................................................... 17

6.1 Electrical Specifications......................................................................................................................... 17

6.1.1 Absolute Maximum Limits ..........................................................................................................................17

6.1.2 Operating Limits.........................................................................................................................................17

6.1.3 Operating Characteristics...........................................................................................................................18

6.1.4 Packages....................................................................................................................................................19

MXCOM, Inc. reserves the right to change specifications at any time without notice.

High Speed GMSK Modem 4k to 64kbps 3 MX589

1998 MX-COM, Inc. www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: [phone] Doc. # 20480103.010

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

1 Block Diagram

TX PS

RX PS

BT

TX DATA

ClkDIVA

PLLacq
RXDCacq

RX SIGNAL IN
RX FEEDBACK

CLOCK

DIVIDER

XTAL/CLOCK

TX ENABLE

XTAL

V

DD

V

BIAS

V

BIAS

V

BIAS

V

SS

RXHold

RX CLK

TX CLK

TX OUT

RX DAT A

RX S/N

DOC1 DOC2

ClkDIVB

RX CIRCUIT

CONTROL

RX

FILTER

DA TA RETIME &

LEVEL SHIFT

TX

FILTER

RX S/N

DETECTION

RX CLOCK

RX DC LEVEL

MEASURE

+

-

V

BIAS

RX DATA

DETECTION

Figure 1: Block Diagram

RX Frequency

Discriminator

Frequency

Modulator

Signal and

DC Level

Adjustment

DC Level
Adjust

RX Sig In

RX Feedback

RX circuits

TX circuits

RXD
RXC

TXD
TXC

uController
or UAR T

RX Data
RX Clock
TX Data
TX Clock

MX589

GMSK MODEM

TX Out

TX Out
Filter

RX Filter

and Gain

Figure 2: System Block Diagram

High Speed GMSK Modem 4k to 64kbps 4 MX589

1998 MX-COM, Inc. www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: [phone] Doc. # 20480103.010

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

2 Signal List

Pin No.

TN/DW/P

Signal Type Description

1

XTAL

output The output of the on-chip clock oscillator.

2 XTAL/CLOCK input

The input to the on-chip Xtal oscillator. A Xtal, or externally derived clock (f

XTAL

)
pulse input should be connected here. If an externally generated clock is to be
used, it should be connected to this pin and the

XTALpin left unconnected.
Note: Operation of the MX589 without a suitable Xtal or clock input may cause
device damage.

3 ClkDivA input Logic level inputs control the internal clock divider and therefore the transmit and

receive data rate. See Table 4.

4 ClkDivB input

Logic level inputs control the internal clock divider and therefore the transmit and
receive data rate. See Table 4.

5

HOLDRx

input

A logic 0 applied to this input will freeze the Clock Extraction and Level
Measurement circuits unless they are in ‘Acquire’ mode.

6 RxDCacq input A logic 1 applied to this input will set the RX Level Measurement circuitry to the

Acquire mode.

7 PLLacq input A logic 1 applied to this input will set the RX Clock Extraction circuitry to the

‘Acquire’ mode. See Table 5.

8 Rx PSAVE input A logic 1 applied to this input will powersave all receive circuits except for RX

CLK output (which will continue at the set bit-rate) and cause the RX Data and
RX S/N outputs to go to a logic 0.

9

V

BIAS

The internal circuitry bias line, held at VDD/2. This pin must be bypassed to V

SS

by a capacitor mounted close to the pin.

10 Rx FB Output of the RX Input Amplifier.
11 Rx Signal In input Input to RX input amplifier.
12

V

SS

power Negative supply (GND).

13 DOC1 Connections to the RX Level Measurement Circuitry. A capacitor should be

connected from each pin to V

SS

.

14 DOC2

Connections to the RX Level Measurement Circuitry. A capacitor should be
connected from each pin to V

SS

.

15 BT A logic level to select the modem BT (the ratio of the TX Filter's -3dB frequency

to the Bit-Rate). A logic 1 = BT of 0.5 and a logic 0 = BT of 0.3.

16 Tx Out output The TX signal output from the MX589 GMSK Modem.
17 Tx Enable input A logic 1 applied to this input, enables the transmit data path, through the TX

Filter to the TX Out pin. A logic 0 will place the TX Out pin to V

BIAS

via a high

impedance.

18 Tx PSAVE input

A logic 1 applied to this input will powersave all transmit circuits except for the
TX Clock.

19 Tx Data input The logic level input for the data to be transmitted. This data should be

synchronous with TX CLK.

20 Rx Data output A logic level output carrying the received data, synchronous with RX CLK.
21 Rx CLK output A logic level clock output at the received data bit-rate.
22 Tx CLK output A logic level clock output at the transmit-data rate.
23 Rx S/N output A logic level output which may be used as an indication of the quality of the

received signal.

24

V

DD

power Positive supply. A single 5.0V power supply is required. Levels and voltages

within this modem are dependent upon this supply. This pin should be bypassed
to V

SS

by a capacitor mounted close to the pin.

High Speed GMSK Modem 4k to 64kbps 5 MX589

1998 MX-COM, Inc. www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: [phone] Doc. # 20480103.010

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

Table 1: Signal List

3 External Components

ClkDivA
ClkDivB

RX HOLD
RXDCacq

PLLacq

RX PSAVE

V

BIAS

RX FB

RX SIGNAL IN

V

SS

V

DD

RX S/N
TXCLK
RXCLK
RXDATA
TXDATA
TXPSAVE
TXENABLE
TXOUT
BT
DOC1
DOC2

1
2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

MX589

C6

R4

R3

C7 C8

C4

R1

C1

V

DD

XTAL/CLOCK

XTAL

XTAL

XTAL/CLOCK

1

2

C3

C2

X1 R2

C5

Figure 3: Recommended External Components

Component Notes Value Tolerance Component Notes Value Tolerance

R1 Note 1 ±5% C4 0.1µF ±20%
R2

1.0M

Ω

±10% C5 1.0µF ±20%
R3 Note 2 ±10% C6 22.0pF ±20%
R4

100k

Ω

±10% C7 Note 4
C1 Note 1 ±10% C8 Note 4
C2 Note 3
C3 Note 3 X1 Note 5

Table 2: Recommended External Components

High Speed GMSK Modem 4k to 64kbps 6 MX589

1998 MX-COM, Inc. www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: [phone] Doc. # 20480103.010

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

Recommended External Component Notes:

1.

The RC network formed by R1 and C1 is required between the TX Out pin and the input to the modulator. This
network, which can form part of any DC level shifting and gain adjustment circuitry, forms an important part of the
transmit signal filtering. The ground connection to the capacitor C1 should be positioned to give maximum attenuation
of high-frequency noise into the modulator.
The component values should be chosen so that the product of the resistance and the capacitance is:

For a BT of 0.3 R1C1 = 0.34/bit rate (bps)
For a BT of 0.5 R1C1 = 0.22/bit rate (bps)

BT =- 0.3 BT = 0.5

Data Rates

(bps)

R1 C1 R1 C1

4000

120k

Ω

680pF

120k

Ω

470pF

4800

100k

Ω

680pF

100k

Ω

470pF

8000

91k

Ω

470pF

120k

Ω

220pF

9600

91k

Ω

390pF

47k

Ω

470pF

16000

47k

Ω

470pF

91k

Ω

150pF

19200

100k

Ω

180pF

91k

Ω

120pF

32,000

47k

Ω

220pF

47k

Ω

150pF

38,400 *

47k

Ω

180pF

47k

Ω

120pF

64,000 *

56k

Ω

100pF

51k

Ω

68pF

* VDD ≥ 4.5V

Table 3: Data Rate vs. BT and Selected External Component Values

Note: In all cases, the value of R1 should not be less than 20.0kΩ, and that the calculated value of C1 includes

calculated parasitic capacitance.

2. R3, R4 and C6 form the gain components for the RX Input signal. R3 should be chosen as required by the signal
input level.

3. The values chosen for C2 and C3 (including stray capacitance), should be suitable for the applied VDD and the
frequency of X1.
As a guide: C2 = C3 = 33pF at 1.0MHz falling to 18pF at the maximum frequency.
At 3.0V, C2 = C3 = 33pF falling to 18pF at 5.0MHz the equivalent series resistance of X1 should be less than 2.0K

Ω

falling to 150Ω at the maximum frequency. Stray capacitance on the Xtal/Clock circuit pins must be minimized.

4. C7 and C8 should both be .015µF for a data rate of 8kbps, and inversely proportional to the data rate for other data
rates, e.g. .030µF at 4kbps, 1800pF at 64kbps.

5. The MX589 can operate correctly with the Xtal/Clock frequencies between 1.0MHz and 8.2MHz (V

DD

= 5.0V) and

1.0MHz to 5.0MHz (V

DD

= 3.0V) see Table 1 for examples. For best results, a crystal oscillator design should drive
the clock inverter input with signal levels of at least 40% of VDD, peak to peak. Tuning fork crystals generally cannot
meet this requirement. To obtain crystal oscillator design assistance, consult your crystal manufacturer. Operation of

this device without a Xtal or Clock input may cause device damage.

High Speed GMSK Modem 4k to 64kbps 7 MX589

1998 MX-COM, Inc. www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: [phone] Doc. # 20480103.010

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

4 General Description

4.1 Clock Oscillator Divider

The TX and (nominal) RX data rates are determined by division of the frequency present at the

Xtal

pin, which may be

generated by the on-chip Xtal oscillator or derived from an external source. Any Xtal/Clock frequency in the range of

1.0MHz to 5.0MHz for V

DD

= 3.0V, or 1.0MHz to 8.2MHz for VDD = 5.0V may be used, depending on the desired data

rate.
The division ratio is controlled by the logic level inputs on ClkDivA and ClkDivB pins as shown in Table 4, together with an

indication of how various standard data rates may be derived from common µP Xtal frequencies.

A/B)(ClkDiv Ratio Division

Frequency Xtal/Clk

Rate Data

=

Xtal/Clock Frequency (MHz)

8.192 4.9152 4.096 2.4576 2.048

Inputs 12.288/3 12.288/5 6.144/3

ClkDivA ClkDivB

Division Ratio

Xtal Frequency Data Rate

Data Rate (bps)
0 0 128 64000* 38400* 32000 19200 16000
0 1 256 32000 19200 16000 9600 8000
1 0 512 16000 9600 8000 4800 4000
1 1 1024 8000 4800 4000

* VDD ≥ 4.5V

Table 4: Clock/Data Rates

Note: The device operation is not guaranteed above 64kbps or below 4kbps at the relevant supply voltage.

Tx Enable

ClkDIVA
ClkDIVB

BT

RxHOLD

Rx S/N

Tx PS

Rx PS

XTAL/CLOCK
XTAL

Rx DATA
Rx CLOCK

Tx DATA

Tx ClOCK

PLLacq
RxDCacq

RxD
RxC

TxD
TxC

SERIAL

I/O PORT

µCONTROLLER

SETTINGS: D/RATE 4800 bps -BT 0.5 - Rx andTx Enabled

MX589

GMSK MODEM

V

DD

4.9152MHz

Figure 4: Minimum µController System Connections

4.2 Receive

4.2.1 Rx Signal Path Description

The function of the RX circuitry is to:

1. Set the incoming signal to a usable level.

2. Clean the signal by filtering.

3. Provide DC level thresholds for clock and data extraction.

4. Provide clock timing information for data extraction and external circuits.

5. Provide RX data in a binary form.

6. Assess signal quality and provide Signal-to-Noise information.

High Speed GMSK Modem 4k to 64kbps 8 MX589

1998 MX-COM, Inc. www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: [phone] Doc. # 20480103.010

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

The output of the radio receiver's Frequency Discriminator should be fed to the MX589's RX Filter by a suitable gain and
DC level adjusting circuit. This circuit can be built with external components around the on-chip RX Input Amplifier. The
gain should be set so that the signal level at the RX Feedback pin is nominally 1V peak to peak (for V

DD

=5.0V) centered

around V

BIAS

when receiving a continuous 1111000011110000.. data pattern.

Positive going signal excursions at RX Feedback pin will produce a logic 0 at the RX Data Output. Negative going
excursions will produce a logic 1.

The received signal is fed through the lowpass RX Filter, which has a -3dB corner frequency of 0.56 times the data
bit-rate, before being applied to the Level Measure and Clock and Data extraction blocks.

The Level Measuring block consists of two voltage detectors, one of which measures the amplitude of the positive parts of
the received signal. The other measures the amplitude of the negative portions. (Positive refers to signal levels higher
than V

DD

/2, and negative to levels lower than VDD/2.) External capacitors are used by these detectors, via the Doc1 &

Doc2 pins, to form voltage ‘hold’ or ‘integrator’ circuits. These two levels are then used to establish the optimum DC level
decision-thresholds for the Clock and Data extraction, depending upon the RX signal amplitude and any DC offset.

4.2.2 Rx Circuit Control Modes

The operating characteristics of the Rx Level Measurement and Clock Extraction circuits are controlled, as shown in Table
5, by logic level inputs applied to the PLLacq,

HOLDRx

, and RxDCacq pins to suit a particular application, or to cope with

changing reception conditions, reference Figure 5.
In general, a data transmission will begin with a preamble, for example, 1100110011001100, to allow the receive modem

to establish timing and level-lock as quickly as possible. After the Rx carrier has been detected, and during the time that
the preamble is expected, the RxDCacq and PLLacq Inputs should be switched from a logic 0 to a logic 1 so that the
Level Measuring and Clock Extraction modes are operated and sequenced as shown.

The

HOLDRx

input should normally be held at a logic 1 while data is being received, but may be driven to a logic 0 to

freeze the Level Measuring Clock Extraction circuits during a fade. If a fade lasts for less than 200 bit periods, normal
operation can be resumed by returning the

HOLDRx

input to a logic 1 at the end of the fade. For longer fades, it may be

better to reset the Level Measuring circuits by placing the RxDCacq to a logic 1 for 10 to 20 bit periods.

HOLDRx

has no effect on the Level Measuring circuits while RxDCacq is at a logic 1, and has no effect on the PLL while

PLLacq is at a logic 1.
A logic 0 on

HOLDRx

does not disable the Rx Clock output, and the Rx Data Extraction and S/N Detector circuits will

continue to operate.

Rx Signal Input

Rx CARRIER DET
(RSSI) Input

RxDCacq
Rx LEVEL MEASURE
MODE

PLLacq
CLOCK EXTRACTION
CCT MODE

F AST PEAK

DETECT

30 BITS

MEDIUM

BANDWIDTH

NARROW

BANDWIDTH

AVERAGING PEAK

DETECT

ACQUIRE

CLAMP

PREAMBLE DATA

Figure 5: Rx Mode Control Diagram

High Speed GMSK Modem 4k to 64kbps 9 MX589

1998 MX-COM, Inc. www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: [phone] Doc. # 20480103.010

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

PLLacq

HOLD Rx

PLL Action

1 1 Acquire Sets the PLL bandwidth wide enough to allow a lock to the received

signal in less than 8 zero crossings. This mode will operate as long
as PLLacq is a logic “1”.

1 to 0 1 Medium Bandwidth The correction applied to the extracted clock is limited to a

maximum of ±1/16th bit-period for every two received zero­crossings. The PLL operates in this mode for a period of about 30
bits immediately following a 1 to 0 transition of the PLLacq input,

provided that the

HOLDRx

input is a logic 1.

0 1 Narrow Bandwidth

The correction applied to the extracted clock is limited to a
maximum of ±1/64th bit-period for every two received zero-

crossings. The PLL operates in this mode whenever the

HOLDRx

Input is a logic 1 and PLLacq has been a logic 0 for at least 30 bit
periods (after Medium Bandwidth operation for instance).

0 0 Hold The PLL feedback loop is broken, allowing the RX Clock to

freewheel during signal fade periods.

RxDCacq

HOLD Rx

Rx Level Measure Action

0 to 1 X Clamp Operates for one bit-time after a 0 to 1 transition of the RXDCacq

input. The external capacitors are rapidly charged towards a
voltage mid-way between the received signal input level and V

BIAS

,

with the charge time-constant being of the order of 0.5bit-time.

1 X Fast Peak Detect The voltage detectors act as peak-detectors, one capacitor is used

to capture the positive-going signal peaks of the RX Filter output
signal and the other capturing the negative-going peaks. The
detectors operate in this mode whenever the RXDCacq input is at a
logic 1, except for the initial 1-bit Clamp-mode time.

0 1 Averaging Peak Detect Provides a slower but more accurate measurement of the signal

peak amplitudes.

0 0 Hold The capacitor charging circuits are disabled so that the outputs of

the voltage detectors remain substantially at the last readings
(discharging very slowly [time-constant approx. 2,000 bits] towards
V

BIAS

).

X = Do not care

Table 5: PLL and Rx Level Measurement Operational Modes

4.2.3 Rx Clock Extraction

Synchronized by a PLL circuit to zero-crossings of the incoming data, the Rx Clock Extraction circuitry controls the Rx
Clock output. The Rx Clock is also used internally by the Data Extraction circuitry. The PLL parameters can be varied by

the Rx Circuit Control inputs PLLacq and

HOLDRx

to operate in one of four PLL modes as described in Table 5.

4.2.4 Rx Data Extraction

The RX Data Extraction circuit decides whether each received bit is a 1 or 0 by sampling the received signal, after
filtering, and comparing the sample values to an adaptive threshold derived from the Level Measuring circuit. This
threshold is adapted from bit to bit to compensate for intersymbol interference caused by the bandlimiting of the overall
transmission path and the Gaussian premodulation filter. Extracted data is output from the RX Data pin, and should be
sampled externally on the rising edge of the RX CLK.

4.2.5 Rx S/N Detection

The RX S/N Detector system classifies the incoming zero-crossings as GOOD or BAD depending upon the time when
each crossing actually occurs with respect to its expected time as determined by the Clock Extraction PLL. This
information is then processed to provide a logic level output at the RX S/N pin. A high level indicates a series of GOOD
crossings; a low level indicates a BAD crossing.

By averaging this output, it is possible to derive a measure of the Signal-to-Noise-Ratio and hence the Bit-Error-Rate of
the received signal.

High Speed GMSK Modem 4k to 64kbps 10 MX589

1998 MX-COM, Inc. www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: [phone] Doc. # 20480103.010

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

10

-6

10

-5

10

-4

10

-3

10

-2

10

-1

5

6

7

8910

11 12

13

14

15 16

17

18 19 20

S/N (dB) [Noise Bandwidth = Bit Rate]

BER

MX589 BT = 0.3

MX589 BT = 0.5

BT = 1.0 (Theoretical)

Figure 6: Typical Bit-Error-Rate Performance

4.2.6 Rx Signal Quality

The effect of input Rx Signal quality on the Rx S/N output is shown in Figure 7.

0

10

20

30

40

50

60

70

80

90

100

6

7

8910

11 12

13

S/N (dB)

% High Time

5

BT=0.5

BT = 0.3

Figure 7: Typical Rx S/N Output High time (%) vs. Input S/N

High Speed GMSK Modem 4k to 64kbps 11 MX589

1998 MX-COM, Inc. www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: [phone] Doc. # 20480103.010

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

4.3 Transmit

4.3.1 TX Signal Path Description

The binary data applied to the TX Data input is retimed within the chip on each rising edge of the TX Clock and then
converted to a 1-volt peak-to-peak binary signal centered at V

BIAS

(for VDD= 5.0V)

If the TX Enable input is high, then this internal binary signal will be connected to the input of the lowpass TX Filter, and
the output of the filter connected to the TX Out pin.

Tx Enable Tx Filter Input Tx Out Pin

1

V

DD

/5V

P-P

Data

Filtered Data

0

V

BIAS

V

BIAS

via 500k

Ω

A ‘low’ input to the TX Enable will connect the input of the TX Filter to V

BIAS

, and disconnect the TX Out pin from the filter,

connecting it instead to V

BIAS

through a high resistance (nominally 500kΩ).

The TX Filter has a lowpass frequency response, which is approximately gaussian in shape as shown in Figure 9, to
minimize amplitude and phase distortion of the binary signal while providing sufficient attenuation of the high frequency­components which would otherwise cause interference into adjacent radio channels. The actual filter bandwidth to be
used in any particular application will be determined by the overall system requirements. The attenuation-vs.-frequency
response of the transmit filtering provided by the MX589 has been designed to meet the specifications for most GMSK
modem systems that are -3dB bandwidth switchable between 0.3 and 0.5 times the data bit-rate (BT).

Note: An external RC network is required between the TX Out pin and the input to the Frequency Modulator (see Figure
2 and Figure 3). This network, which can form part of any DC level shifting and gain adjustment circuitry, forms an
important part of the transmit signal filtering. The ground connection to capacitor C1 should be positioned to give
maximum attenuation of high-frequency noise into the modulator.

The signal at Tx Out is centered around VBIAS, going positive for logic 1 (high)level inputs to the Tx Data input and
negative for logic 0 (low) inputs.

When the transmit circuits are put into a powersave mode (by a logic 1 to the Tx PS pin) the output voltage of the Tx Filter
will go to VSS. When power is subsequently restored to the Tx filter, its output will take several bit-times to settle. The Tx
Enable input can be used to prevent these abnormal voltages from appearing at the Tx Out pin.

1 BIT PERIOD

TX DATA SAMPLED BY

THE MX589 AT THESE

INSTANCES

TX Data

RX Data

RX CLK

TX CLK

DON'T CARE

DATA INVALID DAT AVALID

DATA MUST

BE VALID

EXTERNAL CIRCUITS SHOULD

SAMPLE RX DATA ATTHIS TIME

TX CLOCK AND RX CLOCK OUTPUTS
(MARK/SPACE) DUTY CYCLE NOMINALL Y 50%.

1.0 s Min.µ

1.0 s Max.µ 1.0 s Max.µ

1.0 s Min.µ

Figure 8: Rx and Tx Clock Data Timings

High Speed GMSK Modem 4k to 64kbps 12 MX589

1998 MX-COM, Inc. www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: [phone] Doc. # 20480103.010

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

.

.

BT = 0.3

BT = 0.5

0

-10

-20

-30

-40

-50

-60

-70

0.1 10

1

0.01

Frequency/Bitrate

Gain (dB)

Figure 9: Tx Filter Response

BT = 0.3 BT = 0.5

Figure 10: Typical Transmit Eye Patterns

High Speed GMSK Modem 4k to 64kbps 13 MX589

1998 MX-COM, Inc. www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: [phone] Doc. # 20480103.010

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

-70

-60

-50

-40

-30

-20

-10

0

01.0

2.0

Gain (dB)

Frequency/Bitrate

BT = 0.3 BT=0.5

Figure 11: Tx Output Spectrum (Random Data)

4.4 Data Formats

The receive section of the MX589 works best with data which has a reasonably random structure --the data should
contain approximately the same number of ‘ones’ as ‘zeroes’ with no long sequences (>100 bits) of consecutive ones or
zeroes. Also, long sequences (>100 bits) of 10101010 ... patterns should be avoided.

For this reason, it is recommended that data be made random in some manner before transmission, for example by
exclusive-ORing it with the output of a binary pseudo-random pattern generator.

Where data is transmitted in bursts, each burst should be preceded by a preamble designed to allow the receive modem
to establish timing and level lock as quickly as possible. This preamble for BT=0.3 should be at least 16 bits long, and

should preferably consist of alternating pairs of ones and zeros i.e. 110011001100....; the eye of pattern 10101010 .... has

the most gradual slope and will yield poor peak levels for the RX circuits. For BT=0.5 the eye pattern of 10101010... has
reduced intersymbol interference and may be used as the preamble (DC Acq pin should be held high during preamble).
See Fig. 6.

4.5 Acquisition and Hold Modes

The RXDCacq and PLLacq inputs must be pulsed High for about 16 bits at the start of reception to ensure that the DC
measurement and timing extraction circuits lock-on to the received signal correctly. Once lock has been achieved, the
above inputs should be taken Low again.

In most applications, there will be a DC step in the output voltage from the receiver FM discriminator due to carrier
frequency offsets as channels are changed or when the remote transmitter is turned on.

The MX589 can tolerate DC offsets in the received signal of at least ±0.5V with respect to V

BIAS

, (measured at the RX

Feedback pin). However, to ensure that the DC offset compensation circuit operates correctly and with minimum delay,
the Low to High transition of the RXDCacq and PLLacq inputs should occur after the mean input voltage to the MX589
has settled to within about 0.1V of its final value.

Note: This can place restrictions on the value of any series signal coupling capacitor.
As well as using the RX Hold input to freeze the Level Measuring and Clock Extraction circuits during a signal fade, it may

also be used in systems which use a continuously transmitting control channel to freeze the RX circuitry during
transmission of a data packet, allowing reception to resume afterwards without losing bit synchronization. To achieve this,
the MX589 Xtal clock needs to be accurate enough that the derived RXClock output does not drift by more than about 0.1
bit time from the actual received data-rate during the time that the RXHold input is ‘Low’.

However; the RXDCacq input may need to be pulsed High for 2 bit durations to re-establish the level measurements if the
RXHold input is Low for more that a few hundred bit-times (exact number depends on system crystal tolerances).

The voltages on the Doc1 and Doc2 pins reflect the average peak positive and negative excursions of the (filtered)
receive signal, and could therefore be used to derive a measure of the data signal amplitude.

Note: These pins are driven from very high-impedance circuits, so that the DC load presented by any external circuitry
should exceed 10MΩ to V

BIAS

.

High Speed GMSK Modem 4k to 64kbps 14 MX589

1998 MX-COM, Inc. www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: [phone] Doc. # 20480103.010

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

5 Application

5.1 Radio Channel Requirements

To achieve legal adjacent channel performance at high bit-rates, a radio with an accurate carrier frequency and an
accurate modulation index is required. For optimum channel utilization, (e.g. low BER and high data-rates) attention must
be paid to the phase and frequency response of both the IF and baseband circuitry.

5.1.1 Bit Rate, BT, and Bandwidth

The maximum data rate that can be transmitted over a radio channel depends on the following:

Channel spacing
Allowable adjacent channel interference
TX filter bandwidth
Peak carrier deviation (Modulation Index)
TX and RX carrier frequency accuracies
Modulator and Demodulator linearity
RX IF filter frequency and phase characteristics
Use of error correction techniques
Acceptable error-rate

As a guide to MOBITEX operation, a raw data-rate of 8kbps at 12.5kHz channel spacing may be achievable -depending
on local regulatory requirements- using a ±2kHz maximum deviation, a BT of 0.3, and no more than 1.5kHz discrepancy
between Tx & Rx carrier frequencies. Forward error correction (FEC) could then be used with interleaving to reduce the
effect of burst errors.

Reducing the data-rate to 4.8kbps would allow the BT to be increased to 0.5, improving the error-rate performance.

5.1.2 FM Modulator, Demodulator and IF

For optimum performance, the eye pattern of the received signal (when receiving random data) applied to the MX589
should be as close as possible to the Transmit eye pattern examples shown in Figure 10.

Of particular importance are general symmetry, cleanliness of the zero-crossings, and for a BT of 0.3, the relative
amplitude of the inner eye opening.

To achieve this, attention must be paid to:

Linearity and frequency/phase response of the Tx frequency modulator. Unless the transmit data is especially
encoded to remove low frequency components, the modulator frequency response should extend down to a few
hertz. This is because two-point modulation is necessary for synthesized radios.

Bandwidth & phase response of the RX IF filters.
Accuracy of the Tx and Rx carrier frequencies -any difference will shift the received signal towards one of the

skirts of the IF filter response.

Ideally, the Rx demodulator should be DC coupled to the MX589 RX Signal In pin (with a DC bias added to center the
signal at the RX Feedback pin at V

DD

/2 [V

BIAS

]). However, AC coupling can be used provided that:

The 3dB cut-off frequency is 20Hz or below (i.e. a 0.1µF capacitor in series with 100kΩ).
The data does not contain long sequences of consecutive ones or zeroes.
Sufficient time is allowed after a step change at the discriminator output (resulting from channel changing or the

appearance of a RF carrier) for the voltage into the MX589 to settle before the RXDCacq line is strobed.

High Speed GMSK Modem 4k to 64kbps 15 MX589

1998 MX-COM, Inc. www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: [phone] Doc. # 20480103.010

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

5.1.3 Two-Point Modulation

When designing the MX589 into a radio that uses a frequency synthesizer, a two-point modulation technique is
recommended. This is both to prevent the radio's PLL circuitry from counteracting the modulation process, and to provide
a clean flat modulation response down to DC.

Figure 12 shows a suggested basic configuration to provide a two-point modulation drive from the MX589 TX Output
using MX-COM's MX019 Digitally Controlled Quad Amplifier Array. The MX019 elements provide individual set-up,
calibration and dynamic control of modulation levels. Level setting control of the amplifiers/attenuators of the MX019 is
via an 8-bit data word.

With reference to Figure 12:

The buffer amplifier is required to prevent loading of the MX589 external RC circuit.
Stage B, with R1/R2, provides suitable signal and DC levels for the VCO varactor; C1 is RF decoupling. The

drive level should be adjusted (digitally) to provide the desired deviation.
Stage C, with R3/R4, provides the Reference Oscillator drive (application dependent). This parameter is set by

adjusting for minimum AC signal on the PLL control voltage with a low-frequency modulating signal (inside the
PLL bandwidth) applied.

Stage D could be used with the components shown if a negative reference drive is required.
Stage A provides buffering and overall level control.

MX589

TX OUT

+14dB to -14dB

Buffer

+3dB to -3dB

CONTROL

+3dB to -3dB

+3dB to -3dB

A

B

C

D

TX VCO

To TX

REF Osc (+)

To TX

REF Osc (-)

V

SS

V (-)

REF

R5

External RC
See Fig.3

R6

V

VCO

C1

R1

R2

V(+)

REF

R3

R4

With reference to the MX019 Data Sheet
Stage A = MX019 Channel 4
Stage B = MX019 Channel 1
Stage C = MX019 Channel 2
Stage D = MX019 Channel 3
Note:

1. All stages of the MX019 are 'inverting' stages.

2. Components R1-R6 should produce the proper output
signal levels for interface into the modulator.

Figure 12: An Example of Two-Point Modulation Drive with Individual Adjustment Using the MX019

High Speed GMSK Modem 4k to 64kbps 16 MX589

1998 MX-COM, Inc. www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: [phone] Doc. # 20480103.010

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

5.2 AC Coupling of Tx and Rx Signals

In practical applications, it is possible to arrange AC coupling between the MX589 Tx Output and the frequency modulator
to cut-off at a very low frequency, such as 5.0Hz. AC coupling between the receive discriminator and the input of the
MX589 may need a shorter time-constant to avoid problems from voltage steps at the output of the discriminator when
changing channels or when the distant transmitter turns on.

For these reasons, as well as to maintain reasonable BER, the optimum –3dB cut-off frequencies are around 5.0Hz in the
Tx path and 20.0Hz in the Rx path.

Figure 13 shows the typical static Bit-Error-Rate performance of the MX589 operating under nominal conditions for
various degrees of AC coupling at the Rx input and the Tx output.

Data Rate = 8kbps

V

DD

= 5.0V T

AMB

= 25C

Tx BT = 0.3

S/N (dB) (noise in 8kHz bandwidth)

10

-5

10

-4

10

-3

10

-2

10

-1

4

5678910111213

BER

TX and RX DC coupled
TX 5Hz, RX DC coupled

TX 5Hz, RX 10Hz
TX 5Hz, RX 30Hz

TX 5Hz, RX 100Hz

Figure 13: Effect of AC Coupling on Typical Bit-Error Rate

Any AC Coupling at the receive input will transform any step in the voltage at the discriminator output to a slowly decaying
pulse which can confuse the modem’s level measuring circuits. As illustrated in Figure 14, the time for this step to decay
to 37% of its original value is ‘RC’ where:

network) RC the offrequency cutoff 3dB (the2

1

RC

π

=

which is 32ms, or 256 bit times at 8kbps, for a 5Hz network.

Figure 14: Decay time-AC Coupling

High Speed GMSK Modem 4k to 64kbps 17 MX589

1998 MX-COM, Inc. www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: [phone] Doc. # 20480103.010

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

6 Performance Specifications

6.1 Electrical Specifications

6.1.1 Absolute Maximum Limits

Exceeding these maximum ratings can result in damage to the device.

General Notes Min. Typ. Max. Units

Supply (VDD-VSS)

-0.3 7.0 V

Voltage on any pin to V

SS

-0.3

V

DD

+ 0.3

V

Current

V

DD

-30 30 mA

V

SS

-30 30 mA

Any other pin -20 20 mA

DW / P Packages

Total allowable Power dissipation at T

AMB

= 25°C

800 mW

Derating above 25°C

13

mW/°C above 25°C

Operating Temperature -40 85

°

C

Storage Temperature -55 125

°

C

TN Package

Total allowable Power dissipation at T

AMB

= 25°C

550 mW

Derating above 25°C

9

mW/°C above 25°C

Operating Temperature -40 85

°

C

Storage Temperature -55 125

°

C

Table 6: Absolute Maximum Ratings

6.1.2 Operating Limits

Correct Operation of the device outside these limits is not implied.

Notes Min. Typ. Max. Units

Supply (VDD-VSS)

3.0 3.3/5.0 5.5 V

Operating Temperature -40 85

°

C

Rx and Tx Data Rate

VDD ≥ 3.0V

4 20 kbps

VDD ≥ 4.5V

4 64 kbps

Xtal Frequency

VDD ≥ 3.0V

1.0 5.0 MHz

VDD ≥ 4.5V

1.0 10.3 MHz

High Pulse Width 1 40 Ns
Low Pulse Width 1 40 ns

Table 7: Operating Limits

Operating Limits Notes

1. Timing for an external clock input to the Xtal/Clock pin.

High Speed GMSK Modem 4k to 64kbps 18 MX589

1998 MX-COM, Inc. www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: [phone] Doc. # 20480103.010

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

6.1.3 Operating Characteristics

For the following conditions unless otherwise specified.
V

DD

= 5.0V @ T

AMB

= 25°C

Xtal/Clock Frequency = 4.096MHz, Data Rate = 8kbps, Noise Bandwidth = Bit Rate

Static Values Notes Min. Typ. Max. Units

Supply Current Tx PS Rx PS 1

IDD (VDD = 3.0V)

11 0.5 mA
01 1.0 mA
10 1.0 mA
00 1.5 mA

IDD (VDD = 5.0V)

11 1.0 mA
01 2.0 mA
10 3.0 mA
00 4.0 mA

Input Logic Level

Logic 1 Input Level 3.5 V
Logic 0 Input Level 1.5 V

Logic Input Current 2 -5.0 5.0

µ

A

Logic 1 Output Level (IOL = 120µA)

4.6 V

Logic 0 Output Level (IOL = -120µA)

0.4 V

Transmit Parameters

Tx OUT, Output Impedance 3 1.0

k

Ω

Tx Out, Level 4, 10 0.8 1.0 1.2

V

P-P

Output DC Offset 12 -0.125 0.125 V
Tx Data Delay

BT = 0.3 5 2.0 2.5 bit-

periods

BT = 0.5 5 1.5 2.0 bit-

periods

Tx PS to Output-Stable time 6 4.0

bit-

periods

Receive Parameters

Rx Amplifier

Input Impedance 1.0

M

Ω

Output Impedance 7 10.0

K

Ω

Voltage Gain 50.0 dB

Rx Filter Signal Input Level 8, 10 0.7 1.0 1.3

V

P-P

Rx Time Delay 9 3.0

bit-

periods

High Speed GMSK Modem 4k to 64kbps 19 MX589

1998 MX-COM, Inc. www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: [phone] Doc. # 20480103.010

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

On-Chip Xtal Oscillator

R

IN

10.0

M

Ω

R

OUT

11 50.0

k

Ω

Voltage Gain 11 25.0 dB

Table 8: Operating Characteristics

Operating Characteristics Notes:

1. Not including current drawn from the MX589 pins by external circuitry. See Absolute Maximum Ratings.

2. For V

IN

in the range VSS to VDD.

3. For a load of 10KΩ or greater. Tx PS input at logic 0; Tx Enable = 1.

4. Data pattern of 1111000011110000…

5. Measured between the rising edge of Tx Clock and the center of the corresponding bit at Tx Out.

6. Time between the falling edge of the Tx PS and the Tx Out voltage stabilizing to normal output levels.

7. For a load of 10kΩ or greater. Rx PS input at logic 0.

8. For optimum performance, Measured at the Rx Feedback pin for an 1111000011110000… pattern.

9. Measured between the center of bit at Rx Signal In and corresponding rising edge of the Rx Clock.

10. Levels are proportional to applied V

DD

11. Small signal measurement at 1.0kHz with no load on Xtal output.

12. (Tx OUT enabled DC level) – (Tx Out disabled DC level) when transmitting a repeating 11110000 bit pattern.

6.2 Packages

PIN 1

A

B

ALTERNATIVE

PIN

LOCA TION
MARKING

E

L

T

P

J

Y

C

H

0.303 (7.70)

Packa geTolerances

TYP. MAX.MIN.

A
B

C

E
H

DIM.

J
P
Y

T

L

0.047 (1.20)----------

0.256 (6.50)

0° 8°

0.030 (0.75)

0.311 (7.90)

0.177 (4.50)

0.0256 (0.65)

0.020 (0.50)

0.248 (6.30)

0.006 (0.15)0.002 (0.05)

0.003 (0.08) 0.008 (0.20)

0.007 (0.17) 0.012 (0.30)

0.169 (4.30)

NOTE: A lldimensions in inches (mm.)

Angles are in degrees

Figure 15: 24-pin TSSOP Mechanical Outline:

Order as part no. MX589TN

High Speed GMSK Modem 4k to 64kbps 20 MX589

1998 MX-COM, Inc. www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: [phone] Doc. # 20480103.010

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

0.597 (15.16)

Packa geTolerances

A
B
C
E

H

TYP. MAX.MIN.DIM.

J

P

X

W

T

Y

K
L

0.105 (2.67)

0.093 (2.36)

0.419 (10.64)

45°

7°

0°

10°

0.050 (1.27)

0.046 (1.17)

0.613 (15.57)

0.299 (7.59)

0.050 (1.27)

0.016 (0.41)

0.390 (9.90)

0.020 (0.51)0.003 (0.08)

0.009 (0.23)

0.0125 (0.32)

0.013 (0.33)

0.020 (0.51)

0.036 (0.91)

0.286 (7.26)

Z

NOTE: A lldimensions in inches (mm.)

Angles are in degrees

5°

5°

PIN 1

A

B

ALTERNATIVE

PIN

LOCA TION
MARKING

X

P

J

Y

C

H

K

E

L

T

W

Z

Figure 16: 24-pin SOIC Mechanical Outline:

Order as part no. MX589DW

NOTE: A lldimensions in inches (mm.)

Angles are in degrees

Packa geTolerances

A
B
C
E

E1

H

TYP. MAX.MIN.DIM.

J

J1

P
Y

T

K

L

0.220 (5.59)

0.555 (14.04)

0.670 (17.02)

7°

0.160 (4.05)

1.270 (32.26)

0.151 (3.84)

0.100 (2.54)

0.121 (3.07)

0.600 (15.24)

0.590 (14.99) 0.625 (15.88)

0.015 (0.38) 0.045 (1.14)

0.008 (0.20) 0.015 (0.38)

0.015 (0.38) 0.023 (0.58)

0.040 (1.02) 0.065 (1.65)

0.066 (1.67) 0.074 (1.88)

1.200 (30.48)

0.500 (12.70)

H

K
L

J1J1

JJ

PP

CC

BB

AA

PIN1PIN1

TT

EE

E1E1

Y

Figure 17: 24-pin PDIP Mechanical Outline:

Order as part no. MX589P