LA TCH
D5/SERIAL ENABLE 1
D4/SERIAL ENABLE 2
D3/SERIAL DAT A IN
D2/SERIAL CLOCK
D1
D0
RX/
TX
PTL
XT AL/CLK
XTAL
TONE IN
FILTER
TONE
+
-
CLKS
DIGITAL
INTERFACE
AND
CLOCK
GENERATION
CLKS
CLKS/XTAL
CLKS/XTAL
A0-A5
D0-D10
Mobile Radio Channel Sharing
Scan Trunking
Wireless Intercom Traffic Control
Hookswitch Supervision
Repeater Control
TONE DECODE
FILTER
TONE DETECT
TONE OUT FILTER
LOGIC
TONE
ROM
48 x 10
REFERENCE
VOLTAGE
+
RX TONE DETECT
TX TONE OUT
V
V
V
DD
SS
BIAS
TX AUDIO IN
RX AUDIO IN
DECODE COMPARA T OR REF .
DECODE COMPARA T OR IN
CLK
300Hz
AUDIO FILTER
+
-
TX AUDIO OUT
RX AUDIO OUT
RX TONE DECODE
The MX465 CTCSS Encoder/Decoder is a low voltage, CMOS device that meets TIA/EIA-603 Standards.
The MX465 will encode and decode the tones 159.8Hz, 183.5Hz, 189.9Hz, 196.6Hz, 199.5Hz, 206.5Hz,
229.1Hz, and 254.1Hz in addition to the 39 standard CTCSS tones, for a total of 47 CTCSS tones + Notone.
With the incorporation of the on-chip TX and RX speech filter, the MX465 enhances voice/tone multiplexing by
attenuating TX and RX speech 36dB at frequencies below 250Hz while passing signals > 300Hz with only
1dB of ripple. This not only minimizes CTCSS talk-off in the TX mode but also improves Hum and Noise
performance in the RX mode.
Available in the following package styles: 24-pin TSSOP (MX465TN), 24-pin SSOP (MX465DS),
24-pin SOIC (MX465DW), 24-pin PLCC (MX465LH), 24-pin PDIP (MX465P), and 24-pin CDIP (MX465J) the
MX465 requires a single 3.3V to 5.0V supply and a 4MHz clock or crystal.
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Page 4
Low Voltage CTCSS Encoder/Decoder4MX465
2 Signal List
Pin No.SignalTypeDescription
1V
DD
2XTAL/CLOCKinputInput to the on-chip inverter used with a 4 MHz Xtal or
3
4
XTAL
LATCH/LOAD
5D5 / SERIAL ENABLE 1inputData input D5 (Parallel Mode). A logic 1 applied to this
6
D4 / SERIAL ENABLE 2
7D3 / SERIAL DATA INinputData input D3 (Parallel Mode). In Serial Mode this pin
8D2 / SERIAL CLOCKinputData input D2 (Parallel Mode). In Serial Mode this pin
9D1inputData input D1 (Parallel Mode). Internally pulled to VDD.
10D0inputData input D0 (Parallel Mode). Internally pulled to VDD.
11V
SS
12DECODE COMPARATOR
REF.
13
RX TONE DECODE
14DECODE COMPARATOR INinputInverting input of the DECODE COMPARATOR. This pin
15RX TONE DETECToutput In RX mode this output will go to logic 1 during a
power Positive supply. This pin should be bypassed to VSS by
a capacitor mounted close to the device pins.
external clock source.
output Output of the on-chip inverter (clock output).
TX/RX
inputControls 8 on-chip latches. It is used to latch
,
PTL, and D0-D5. A logic 1 applied to this input places the
8 latches in the ‘transparent’ mode. A logic 0 applied to
this input places the 8 latches in the ‘latched’ mode. In
Parallel Mode, data is loaded and latched by a logic 1-0
transition (see Figure 4). In Serial Mode, data is loaded
and latched by a 0-1-0 strobe pulse on this pin (see
Figure 5). Internally pulled to V
DD
input together with a logic 0 applied to
D4/SERIAL ENABLE 2
Mode (see Figure 5). Internally pulled to V
will place the device in Serial
.
DD
inputData input D4 (Parallel Mode). A logic 0 applied to this
input together with a logic 1 applied to D5 / SERIAL
ENABLE 1 will place the device in Serial Mode
(see Figure 5). Internally pulled to V
becomes the serial data input for D5-D0,
DD
.
TXRX/
and PTL
(see Figure 5). D5 is clocked first and PTL last.
Internally pulled to V
DD
.
becomes the SERIAL CLOCK input. Data is clocked on
the positive going edge (see Figure 5). Internally pulled
to V
.
DD
power Negative supply.
inputInternally biased to VDD/3 or 2 VDD/3 via 1M resistors
depending on the logic state of the
RX TONE DECODE
bias this input 2 V
DD
RX TONE DECODE
pin.
= 1 will
/3; a logic 0 will bias this input VDD/3.
This input provides the DECODE COMPARATOR
REFERENCE voltage, and the switching of bias voltages
provides hysteresis to reduce ‘chatter’ under marginal
conditions.
output Gated output of the decode comparator. This output is
used to gate the RX Audio path. A logic 0 on this pin
indicates a successful decode and the DECODE
COMPARATOR IN pin is more positive than the
DECODE COMPARATOR REF. input (see Table 3).
is normally connected to the integrated output of the RX
TONE DETECT line.
successful decode. It must be externally integrated to
control response and deresponse times (see Table 3).
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Page 5
Low Voltage CTCSS Encoder/Decoder5MX465
Pin No.SignalTypeDescription
16TX TONE OUToutput The CTCSS sinewave output appears on this pin under
17
control of the
TX TONE OUT may be biased to V
TXRX/
input RX or TX modes selected in Parallel Mode (see Figure
pin. When not transmitting a tone,
TXRX/
/2. (see Table 3).
DD
4). In Serial Mode this function is serially loaded. This
pin is internally pulled to V
via a 1M resistor.
DD
18PTLinputIn RX mode this pin operates as a ‘Push To Listen’
function by enabling the RX audio path, thus overriding
the tone squelch function (Parallel Mode). In Serial Mode
this function is loaded serially. Internal pull-up to V
DD
19RX AUDIO OUToutput High pass filtered RX AUDIO OUT. This pin outputs
audio when
RX TONE DECODE
= logic 0, PTL = logic 1,
or when Notone is programmed (see Table 4). In TX
mode this pin is biased to V
DD
/2.
20TX AUDIO OUToutput High pass filtered TX AUDIO OUT pin. In TX mode this
pin outputs audio present at the TX AUDIO IN pin. In RX
21V
BIAS
mode this pin is biased to V
output Output of an internally generated VDD /2 bias level that
would normally be externally bypassed to V
DD
/2
SS
via
capacitor C6.
22TX AUDIO INinputIn TX mode TX AUDIO IN may be prefiltered, using the
TX Audio path, thus helping to avoid talk-off due to
intermodulation of speech frequencies with the
transmitted CTCSS tone. Internally biased to V
DD
/2.
23RX AUDIO INinputInput to the audio high pass filter in RX mode. Internally
biased to V
DD
/2.
24TONE INPUTinputInput to the CTCSS tone detector. Internally biased to
1. The values specified for R1, C2, and C3 have been found to be satisfactory when used with a crystal
(X1) whose equivalent series resistance is 1000. For best results, a crystal oscillator design should
drive the clock inverter input with signal levels of at least 40% of V
, peak to peak. Tuning fork
DD
crystals generally cannot meet this requirement. To obtain crystal oscillator design assistance, consult
your crystal manufacturer.
2. The 0.1F value for the DC Blocking capacitors, C4, C5, C7, C8, C9, C10, and C11 is not a
requirement. For the capacitors C4, C5, and C10, the input impedance is internal to the device and
specified typical as 550k. For the remaining capacitors external circuits will be important in
determining the input impedance.
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Page 7
Low Voltage CTCSS Encoder/Decoder7MX465
4 General Description
4.1 Description
Voice on shared radio channels are multiplexed with a subaudible CTCSS (Continuous Tone Controlled
Subaudible Squelch) tone as a means of directing messages among user groups sharing the same RF
frequencies. CTCSS modulates the transmitter with a discrete tone, from 39 standard CTCSS tones in the
range (67.0Hz to 250.0Hz) according to TIA/EIA-603. There are an additional eight CTCSS tones not
specified in TIA/EIA-603 that the MX465 will encode and decode. They are : 159.8Hz, 183.5Hz, 189.9Hz,
196.6Hz, 199.5Hz, 206.5Hz, 229.1Hz, and 254.1Hz, for a total of 47 CTCSS tones plus Notone.
The MX465 also incorporates TX/RX on chip speech filters. In early CTCSS designs, TX speech was not
filtered from the CTCSS tone, rather the filtering was dependent upon the host transmitter’s pre-emphasis
network. At only 6dB/octave, the attenuation of speech components at higher CTCSS tones was only a few
dB which resulted in talk-off (low frequency voice components unsquelching the receiver audio).
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Page 13
Low Voltage CTCSS Encoder/Decoder13MX465
NotesMin.Typ.Max.Units
Encoder
Tone output level12- 1.001.0dB
Tone Frequency Accuracy (f error)- 0.30.3%f
0
Risetime to 90% nominal output
f0>100Hz4,101575ms
f0<100Hz4,1045120ms
Total Harmonic Distortion191.52%
Decoder
Pure tone decode threshold19715mV
Composite signal decode threshold330mV
RMS
RMS
Decode input signal level16-203.5dB
Pure tone decode response time13,1495115140ms
Pure tone decode deresponse time13,1595130170ms
Decode response time3,6,10250ms
Deresponse time3,10180250ms
Decode selectivity:
Upper decode band edge3,11,19,201.005f
Lower decode band edge3,11,19,201.005f
0-1
1.015f
0
0.985f
0.995f
0
0
0.995f
0+1
0
Hz
Hz
Serial / Parallel Inputs
Parallel Set Up Time (tSP)400ns
Load / Latch Pulse Width (tL)400ns
Serial Clock Pulse Width (tC)400ns
Serial Data Set-Up Time (tSS)400ns
Serial Data Hold Time (tH)400ns
Serial Enable Time (t1)400ns
Serial Load / Latch Set-Up Time (t2)400ns
Serial Clock Frequency1MHz
Operating Characteristics Notes:
1. Refers to RX/TX, PTL, Decode Comparator Input, D0-D5.
2. All logic outputs.
3. Composite signal test condition.
4. Any programming tone and R
= 10k, CL = 15pF.
L
5. With an input level of 0dB @1kHz
6. f
>100Hz (for 100 Hz> f0>67Hz: t=100/ f0Hz x 250ms)
0
7. See Figure 3.
8. Measured in a 30kHz bandwidth.
9. With an input level of -3.5dB @1kHz
10. Per TIA/EIA-603.
11. Per TIA/EIA-603, device will not decode adjacent TIA/EIA-603 Tones.
12. Tone output level is proportional to V
=156.7Hz @ -20dB.