Datasheet MX375J, MX375LH, MX375LH8, MX375P Datasheet (MX COM)

DATA BULLETIN

MX375

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

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SQUELCHTM CTCSS

Encoder/Decoder

Features Applications

•

PRIVATE/CLEAR CAPABILITY

•

ON-CHIP TX AUDIO PRE/DEEMPHASIS

•

ALTERNATIVE TO STANDARD CTCSS “PARTY LINE”

•

POWERSAVE OPTION

•

MOBILE RADIOS

•

COMMUNITY REPEATERS

•

TELEPHONE/RADIO INTERCONNECT SYSTEMS

3333 Hz

CTCSS

T oneDetect

8-Bit Shift

Register

and

Latches

Logic

TXTone

Output

V

DD

BIAS

SS

PTL

Private

TX Path

RX Path

f

EMPH

CLK2

CLK1

CARRIER

NoTone Output

Control

LD5-LD0

Reference

Hysteresis

RXTone Decoder Output

Decode Comparator Input

RXTone Detect Output

Clocks

3333Hz

XT AL

RXTone Input Load/Latch

D5 or Serial Enable 1 D4 or Serial Enable 2 D3 or Serial Data Input D2 or Serial Clock Input

D1 Input D0 Input

RX/TX Control Private Enable Push-T o-Listen

BIAS

RX

TX

PVT

CLR

f

EMPH

CLK1

CARRIER

CLK2

TX Audio

Input

RX Audio

Input

Filter

Output

BIAS

RX

TX

RX Audio Output

TX Audio Output

Balanced Modulator Input

6dB/Octave

-6dB/Octave

Filters

The MX375 is a CMOS LSI microcircuit which combines CTCSS Encode/Decode operation with voice band frequency inversion. Frequency inversion is achieved by modulating the input audio with a 3333 Hz carrier frequency. Higher voice band frequencies are translated downward, and lower frequencies upward, resulting in a “mirror image” voice transmission.

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SQUELCH



combines CTCSS with inverted speech to prevent users from understanding each other’s communications unless the transmissions are accompanied by the group’s assigned tone. Its net effect is to eliminate casual eavesdropping and give mobile radio users a certain degree of privacy at a minimal price. Up to 38

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SQUELCH

user groups (one per CTCSS tone) can share a single radio channel. With

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SQUELCH, competing businesses can

share a radio channel without compromising communications security. Device features: 1) serial or parallel tone programming capability (serial or parallel offered on MX375J, P & LH8), 2) the

ability to operate under NOTONE conditions, 3) on-chip Tx and Rx audio filtering, 4) pin-selectable Private/Clear operation, and 5) pre/deemphasis filters in the Tx path, for optimal recovered audio quality.

A low-cost 4 MHz crystal/clock and a single 5V supply are required for operation. The MX375 is available in the following package styles: 28-pin PDIP (MX375P), 28-pin CDIP (MX375J) 28-pin PLCC (MX375LH8), and 24-pin PLCC (MX375LH).

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SQUELCHTM CTCSS Encoder/Decoder 2 MX375

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

CONTENTS

Section Page

1. Block Diagram.................................................................................................................................. 3

2. Signal List......................................................................................................................................... 4

3. External Components...................................................................................................................... 6

4. General Description......................................................................................................................... 7

4.1.1 Pre- and De-emphasis.......................................................................................................................................7

4.1.2 Functions and Outputs.......................................................................................................................................7

5. Application ....................................................................................................................................... 8

5.1.1 CTCSS Programming........................................................................................................................................8

6. Performance Specification.............................................................................................................. 9

6.1 Electrical Performance.............................................................................................................................. 9

6.2 Timing Information ................................................................................................................................... 12

6.2.1 Serial Loading...................................................................................................................................................12

6.2.2 Parallel Loading................................................................................................................................................13

6.3 Packaging ................................................................................................................................................ 13

MX•COM, Inc. reserves the right to change specifications at any time and without notice.

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SQUELCHTM CTCSS Encoder/Decoder 3 MX375

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

1. Block Diagram

3333 Hz

CTCSS

Tone Detect

8-Bit Shift

Register

and

Latches

Logic

TX Tone

Output

V

V V

DD

BIAS

SS

PTL

Private

TX Path

RX Path

f

EMPH

CLK2

CLK1

CARRIER

NoTone Output

Control

LD5-LD0

Reference

Hysteresis

RX Tone Decoder Output

Decode Comparator Input

RX Tone Detect Output

Clocks

3333Hz

XTAL

RX Tone Input Load/Latch

D5 or Serial Enable 1 D4 or Serial Enable 2 D3 or Serial Data Input D2 or Serial Clock Input

D1 Input D0 Input

RX/TX Control Private Enable Push-To-Listen

BIAS

RX

TX

PVT

CLR

f

EMPH

CLK1

CARRIER

CLK2

TX Audio

Input

RX Audio

Input

Filter

Output

BIAS

RX

TX

RX Audio Output

TX Audio Output

Balanced Modulator Input

6dB/Octave

-6dB/Octave

Filters

Figure 1: Device Block Diagram

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SQUELCHTM CTCSS Encoder/Decoder 4 MX375

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2. Signal List

Pin No. Name Type Description

LH J,P,LH8

128 VDDpower 5V supply pin. 2 1 XTAL/CLOCK input This is the input to the clock oscillator inverter. An external 4 MHz Xtal or

clock input should be applied to this pin.

32

XTAL

output This is the 4 MHz output of the clock oscillator inverter.

43

LOAD/

LATCH

input

This input controls the eight input latches: RX/

TX ,

PrivateEnable

, and

D0-D5, as detailed in Table 5. Alternatively, the RX/TX and

PrivateEnable

inputs can be addressed separately by setting the

Load/

Latch

and Control inputs as shown in Table 5. 1 MΩ pullup.

5-7 D4-D2 input

Programming Inputs (Serial Mode Only): These are the

RX/TX tone

programming and function inputs which enable the serial programming mode. With Load/

Latch

at logic “0” serial data is loaded in the following

sequence: D5, D4, D3, D2, D1, D0, RX/

TX ,

PrivateEnable

. When these

8 bits have been clocked in on the rising clock edge, data is latched by strobing the Load/

Latch

input “0 - 1 - 0” (See Figure 5).

Pin 5 (D4) =

Serial Enable2

Pin 6 (D3) = Serial Data Input Pin 7 (D2) = Serial Clock Input

4-9 D5-D0 input

Parallel Programming Inputs: These are the RX/

TX tone programming

and function inputs which select the CTCSS tone (See Table 4).

For both Serial and Parallel Modes:

In RX, a NOTONE program enables RX Audio Output and forces the RX Tone Decode Output to a logic “0”. In TX, a NOTONE program generates a constant V

BIAS

-0.7V condition at

the TX Tone Output pin. Each input has a 1 MΩ pullup resistor.

810

RX TONE DECODE

output The gated output of the decode comparator. In RX, a logic “0” indicates a

valid CTCSS tone decode condition, or the presence of NOTONE programming. A logic “0” enables the RX audio path. In TX, this output is held at logic “1”.

9 11 DECODE

COMPARATOR

input The voltage level at this pin is compared internally with a fixed reference

level. A greater input level compared to the reference will result in a logic “0” at the RX Tone Decode output. This input should be externally connected to the RX Tone Detect output via external integration components C10, R2, R3, and D1 (see Figure 2).

10 12 RX TONE

DETECT

output In RX, this pin outputs a logical “1” when a valid programmed CTCSS

tone is received at the RX TONE INPUT. This input should be externally connected to the Decode Comparator input via external integration components C10, R2, R3, and D1 (see Figure 2).

N/A 13 NOTONE output This pin outputs a logic “0” when a Notone CTCSS code has been

programmed in RX. It is typically used to enable carrier squelch circuits under Notone RX conditions.

11 14 V

SS

power The negative supply pin (ground).

12 15 TX TONE

OUTPUT

output The buffered CTCSS sinewave tone output appears on this pin. In TX

mode, the tone frequency is selected by program code (see Table 4); if NOTONE is programmed, the output is at Vbias-0.7V. In RX mode, the output goes open circuit. This is an emitter follower output with an internal 10 kΩ load.

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SQUELCHTM CTCSS Encoder/Decoder 5 MX375

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Pin No. Name Type Description

LH J,P,LH8

13 16 V

BIAS

This pin is set internally to VDD/2. It must be externally decoupled using a capacitor (C7) to V

SS

. See Figure 2.

14 17 FILTER

OUTPUT

output This is the output of the Input Audio Bandpass Filter. It must be A.C.

coupled to the Balanced Modulator Input via capacitor C4. See Figure 2.

15 18 BALANCED

MODULATOR

INPUT

input This is the input to the balanced modulator. Must be A.C. coupled to the

Filter Output via capacitor C4. See Figure 2.

16 19 RX AUDIO

OUTPUT

output Outputs the received audio from a buffered output stage and is held at

V

BIAS

when in TX.

17 20 TX AUDIO

OUTPUT

output Outputs the transmitted audio in TX. In RX, this pin is held at V

BIAS

.

18 21 RX AUDIO

INPUT

input The audio input for the RX mode. Input signals should be AC coupled via

external capacitor C6. See Figure 2

19 22 TX AUDIO

INPUT

input This is the TX Audio voice input. Signals should be AC coupled via

external capacitor C11. See Figure 2

20 23

PTL

input The “press to listen” function input. In RX mode, a logic “0” enables the

RX Audio Output directly, overriding tone squelch but not intercepting a private conversation; in TX mode, a logic “0” reverses the phase of the TX Tone Output for “squelch tail” reduction (see Table 5).

21 24 CONTROL

This input, together with Load/

Latch

, selects the operational mode of the

RX/

TX and

PrivateEnable

functions. See Table 5

22 25

RX/

TX

input This input selects the RX or TX mode (RX = 1, TX = 0). This can be

loaded in Serial or Parallel modes as described in Table 5

23 26

PRIVATE

ENABLE

This input selects either Private or Clear mode (Clear = 1, Private = 0), and can be loaded by Serial or Parallel modes as described in Table 5. This input has an internal 1 MΩ pullup resistor.

24 27 RX TONE

INPUT

input This is the received audio input to the on-chip CTCSS tone decoder. It

should be A.C. coupled via capacitor C5.

Note: The MX375LH package is available in serial mode only.

Table 1: Signal List

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SQUELCHTM CTCSS Encoder/Decoder 6 MX375

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3. External Components

XTAL

LOAD/ D5 D4 D3 D2 D1 D0

COMP IN DETECT NOTONE V

XTAL

LATCH

RX DECODE

RXTONE

RX/TX

CONTROL

TXIN

RXIN

TXOUT

RXOUT

BALMOD

FILTER

BIAS

TXTONE

PRIVEN

PTL

1 2 3 4 5 6 7 8

9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

MX375J/P/LH8

LOAD/LATCH

SS

DD

V

CTCSS TONE

DECODE OUTPUT

NOTONE

V

D5 D4 D3 D2 D1 D0

R1

X1

C1

C2

C3

C5

C6

C11

C12 C8

C9

C4

+

+5V

R3

R2

D1

C10

C7

C13

+

BIAS

CTCSS TONE OUTPUT (TX)

RX AUDIO OUT

TX AUDIO OUT

RX AUDIO IN

TX AUDIO IN

PUSH TO LISTEN

MODE SELECTION

PUSH TOTALK

PRIVACY ENABLE

CTCSS TONE IN (RX)

V

Figure 2: Recommended External Components

R1

1M

Ω

±10% C6

0.1µF

±20%

R2

560k

Ω

±10% C7

1.0µF

±20%

R3

820k

Ω

±10% C8

0.1µF

±20%

X1 Note 1, 2 4MHz C9

0.1µF

±20%

C1

1.0µF

±20% C10

0.1µF

±20%

C2 33pF ±20% C11

0.1µF

±20%

C3 33pF ±20% C12

0.1µF

±20%

C4

0.1µF

±20% C13

0.001µF

±20%

C5

0.1µF

±20% D1 small signal

Table 2: Recommended External Components

Recommended External Components Note:

1. For best results, a crystal oscillator design should drive the clock inverter input with signal levels of at least 40% of V

DD

, peak to peak. Tuning fork crystals generally cannot meet this requirement. To obtain crystal oscillator design

assistance, consult your crystal manufacturer.

2. XTAL - At cut, fundamental, parallel resonant 20pF load capacitance, 0.05% tolerance

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SQUELCHTM CTCSS Encoder/Decoder 7 MX375

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4. General Description

4.1.1 Pre- and De-emphasis

Pre- and De-emphasis (6dB/octave) filters are included on-chip in the transmit path, so that the use of this device will produce natural sounding audio (clear or private modes) when installed in modern radio communication transceivers, with or without existing audio processing circuitry. The recommended layout is shown in block form below.

From Receiver

Stages

Amplifier

Demodulator

Clear

De-emphasis

Amplifier

Modulator

To Transmitter

Stages

Pre-emphasis

Band Pass

Filter

Band Pass

Filter

Band Pass

Filter

Band Pass

Filter

De-emphasis Pre-emphasis

Figure 3: Transmit and Receive Paths

4.1.2 Functions and Outputs

D0-D5 Notone RX/TX PRIVATE

ENABLE

PTL RX TONE

DETECT

RX TONE

DECODER

TONE

OUTPUT

TONE

PHASETXPATHRXPATH

PATH

STATE

TONE

Tone 1 0 0 1 0 1 YES

0

°

OPEN BIAS INV TX, TONE

Tone 1 0 0 0 0 1 YES

180

°

OPEN BIAS INV TX, TONE REV

Notone 0 0 0 X 0 1 BIAS X OPEN BIAS CLR TX, NOTONE

Tone 1 1 0 1 0 1 BIAS X BIAS BIAS X INCOMPATIBLE Tone 1 1 0 0 0 1 BIAS X BIAS OPEN CLR INCOMPATIBLE Tone 1 1 0 X 1 0 BIAS X BIAS OPEN INV COMPATIBLE

Notone 0 1 0 X X 0 BIAS X BIAS OPEN CLR RX, NOTONE

Tone 1 0 1 1 0 1 YES

0

°

OPEN BIAS CLR TX, TONE

Tone 1 0 1 0 0 1 YES

180

°

OPEN BIAS CLR TX, TONE REV

Notone 0 0 1 X 0 1 BIAS X OPEN BIAS CLR TX, NOTONE

Tone 1 1 1 1 0 1 BIAS X BIAS BIAS X INCOMPATIBLE Tone 1 1 1 0 0 1 BIAS X BIAS OPEN CLR INCOMPATIBLE Tone 1 1 1 X 1 0 BIAS X BIAS OPEN CLR COMPATIBLE

Notone 0 1 1 X X 0 BIAS X BIAS OPEN CLR RX, NOTONE

Table 3: Functions and Outputs

Note:

1. Algebraic functions:

RX Path On = RX (PTL + RX Tone Decoder) Clear Path = Notone + Private Enable + (PTL RX RX Tone Decoder) Notone (D0- D5) = 000011 Carrier Frequency = 3333Hz Durin

g

inverted Path (TX or RX)

×

××

2. The Pre- and De-emphasis circuits remain in the transmit path in both the Clear and Invert Modes.

3. Power remains applied to the CTCSS tone decoder at all times.

4. During clear operation the carrier frequency is turned off to reduce spurious emissions.

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SQUELCHTM CTCSS Encoder/Decoder 8 MX375

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5. Application

5.1.1 CTCSS Programming

Nominal Frequency(Hz)

∆

F

0

(%)

Program Inputs

Frequency(Hz) D5 D4 D3 D2 D1 D0

67.0 67.05 +0.07 1 1 1 1 1 1

71.9 71.9 0 0 1 1 1 1 1

74.4 74.35 -0.07 1 1 1 1 1 0

77.0 76.96 -0.5 0 0 1 1 1 1

79.7 79.77 +0.09 1 1 1 1 0 1

82.5 82.59 +0.1 0 1 1 1 1 0

85.4 85.38 -0.2 1 1 1 1 0 0

88.5 88.61 +0.13 0 0 1 1 1 0

91.5 91.58 +0.09 1 1 1 0 1 1

94.8 94.76 -0.04 0 1 1 1 0 1

97.4 97.29 -0.11 1 1 1 0 1 0

100.0 99.96 -0.04 0 0 1 1 0 1

103.5 103.43 -0.07 0 1 1 1 0 0

107.2 107.15 -0.05 0 0 1 1 0 0

110.9 110.77 -0.12 0 1 1 0 1 1

114.8 114.64 -0.14 0 0 1 0 1 1

118.8 118.8 0 0 1 1 0 1 0

123.0 122.8 -0.17 0 0 1 0 1 0

127.3 127.08 -0.17 0 1 1 0 0 1

131.8 131.67 -0.10 0 0 1 0 0 1

136.5 136.61 +0.08 0 1 1 0 0 0

141.3 141.32 +0.02 0 0 1 0 0 0

146.2 146.37 +0.12 0 1 0 1 1 1

151.4 151.09 -0.2 0 0 0 1 1 1

156.7 156.88 +0.11 0 1 0 1 1 0

162.2 162.31 +0.07 0 0 0 1 1 0

167.9 168.14 +0.14 0 1 0 1 0 1

173.8 173.48 -0.19 0 0 0 1 0 1

179.9 180.15 +0.14 0 1 0 1 0 0

186.2 186.29 +0.05 0 0 0 1 0 0

192.8 192.86 +0.03 0 1 0 0 1 1

203.5 203.65 +0.07 0 0 0 0 1 1

210.7 210.17 -0.25 0 1 0 0 1 0

218.1 218.58 +0.22 0 0 0 0 1 0

225.7 226.12 +0.18 0 1 0 0 0 1

233.6 234.19 +0.25 0 0 0 0 0 1

241.8 241.08 -0.30 0 1 0 0 0 0

250.3 250.28 -0.01 0 0 0 0 0 0

Notone 110000

Table 4: CTCSS Programming

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SQUELCHTM CTCSS Encoder/Decoder 9 MX375

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(A) Explanation of Load/Latch function in Serial and Parallel Modes

Load Configuration

Load/

Latch

Result

Parallel 1 Transparent, the data acts directly Parallel 1 - 0 Latches present data in Parallel 0 No further changes except to allow serial mode selection

Serial (data loading) 0 No change while serial data train is loaded

Serial (data loaded) 0 - 1 - 0 Loaded serial data is latched

(B) Explanation of Control Input

Load Configuration

Load/

Latch

Control

RX/

TX ,

Private Enable

Parallel 0 0 Latched Parallel 1 0 Transparent Parallel X 1 Transparent

Serial 0 - 1 - 0 0 Serial Load Serial X 1 Transparent

Table 5: Load/

Latch

and Control Input Function

Notes:

1. “0 - 1 - 0” is a strobe pulse as shown in Figure 4 and Figure 5.

2. “X” denotes any logical state.

6. Performance Specification

6.1 Electrical Performance

Absolute Maximum Ratings

Exceeding these maximum ratings can result in damage to the device.

General Min. Typ. Max. Units

Supply Voltage -0.3 7.0 V Input Voltage at any pin -0.3 (VDD + 0.3) V

Current

V

DD

-30 30 mA

V

SS

-30 30 mA

Any other pin -20 20 mA

J / P / LH / LH8 Packages

Total Device Dissipation at T

AMB

25°C 800 mW

Derating above 25°C 10 mW/°C above 25°C Operating Temperature -40° 85° C Storage Temperature -55° 125° C

Table 6: Absolute Maximum Ratings

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SQUELCHTM CTCSS Encoder/Decoder 10 MX375

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Operating Limits

Correct operation of the device outside these limits is not implied.

Notes Min. Typ. Max. Units

Supply (VDD-VSS) 4.5 5.0 5.5 V Operating Temperature -40 85 °C

Xtal/Clock Frequency 4.0 MHz

Table 7: Operating Limits

Operating Characteristics

For the following conditions unless otherwise specified: V

DD

= 5.0V, T

AMB

= 25°C, XTAL = 4.0MHz, Audio level )dB ref. = 300mV

RMS

, Composite input signal = 0dB,

1 kHz tone in, -12dB (6kHz band limited) Gaussian white noise with a -20dB CTCSS tone.

Notes Min. Typ. Max Units

Static Values

Supply Voltage 4.5 5.0 5.5 V Supply Current

TX (Private) 15.0 mA TX (Operating) 12.0 mA RX (Operating) 7.0 mA

Analog Input Impedance 0.5

M

Ω

Analog Output Impedance 0.5

k

Ω

Tone Input Impedance 0.5

M

Ω

Input Logic “1” 3.5 V Input Logic “0” 1.5 V Output Logic “1” (I=-0.1mA) 4.0 V Output Logic “0” (I=-0.1mA) 1.0 V

Dynamic Values

Decoder

Input Signal Level 1,4 -20 dB Response Time 1,4,6 250 ms Deresponse Time 1,4,6 250 ms Selectivity 4 ±0.5 ±3.0 %f

0

Encoder

Tone Output Level (775mV

RMS

ref.) -3.0 0 3.0 dB

Tone Frequency Accuracy -0.3 0.3 %f

0

Tone Harmonic Distortion 2.0 5.0 % Tone Output Load Current 2 5.0 mA Output Level Variation between Tones 9 -1.0 1.0 dB Risetime (to 90% nominal level)

(f0>100 Hz) 5 15 ms (f0<100 Hz) 5 45 ms

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Notes Min. Typ. Max Units

RX Clear

Total Harmonic Distortion 3 2 5 % Output Noise Level 7 -43 dB Passband Gain (300-3033Hz) 3 -1 0 1 dB Passband Ripple (300-3033Hz) 3 3 dB Audio Stopband Attenuation

(fIN>3333Hz) 8 -20 dB (fIN>3633Hz) 8 -45 dB (fIN<250Hz) -42 dB

RX Invert

Total Harmonic Distortion 3,8 4 10 % Baseband Breakthrough 3 -40 dB Carrier Breakthrough -40 dB Output Noise Level 7,8 -37 dB Passband Ripple (300-3000Hz) 3 - 4 dB Audio Stopband Attenuation

(fIN>3333Hz) 8 -50 dB (fIN>3633Hz) 8 -60 dB (fIN<250Hz) -60 dB

TX Clear

Total Harmonic Distortion 3 3 5 % Output Noise Level 7 -43 dB Passband Gain (300-3033Hz) 3 0 dB Passband Ripple (300-3033Hz) 3 3 dB Audio Stopband Attenuation

(fIN>3333Hz) 8 -20 dB (fIN>3633Hz) 8 -45 dB (fIN<250Hz) -42 dB

TX Invert

Total Harmonic Distortion 3,8 4 10 % Baseband Breakthrough -40 dB Carrier Breakthrough -40 dB Output Noise Level 7,8 -37 dB Passband Ripple (300-3033Hz) 3,8 4 dB Audio Stopband Attenuation

(fIN>3333Hz) 8 -50 dB (fIN>3633Hz) 8 -60 dB (fIN<250Hz) 8 -60 dB

Table 8: Operating Characteristics

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Operating Characteristics Notes:

1. These values are obtained using the external integrating components given in Figure 2.

2. An emitter follower output

3. With an input signal of 1 kHz @ 0dB.

4. Under Composite Signal test conditions.

5. Any programmed tone with R

L

=600 Ω, CL=15pF, including any response to a phase reversal instruction.

6. f

0

> 100 Hz, (for 100Hz > f0 > 67Hz: t = [100/f0(Hz)] x 250ms).

7. Input ac short-circuit, audio path enabled.

8. Due to frequency inversion, these figures reflect the difference from the ideal response.

9. Reference 156.7 Hz (MX175 and MX275).

6.2 Timing Information

6.2.1 Serial Loading

Min. Typ. Max. Unit

Serial Mode Enable Set Up Time

(t

SMS

)

250 - - ns

Clock “High” Pulse Width (t

PWH

) 250 - - ns

Clock “Low” Pulse Width (t

PWL

) 250 - - ns

Data Set Up Time (tDS) 150 - - ns

Data Hold Time (tDH)50--ns

Load/Latch Set Up Time (tLL) 250 - - ns

Load/Latch Pulse Width (t

LLW

) 150 - - ns

Table 9: Serial Loading Timing Information

SERIAL MODE ENABLE

SERIAL CLOCK

SERIAL DATA INPUT

LOAD/LATCH

D4

D5

t

SMS

PWH

DH

DS

PWL

LL

LLW

Figure 4: Serial Loading Timing

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6.2.2 Parallel Loading

Min. Typ. Max. Unit

Data Valid Time (tVP) 200 ns Load Time (tL) 150 ns Fall Time (tF)50ns Data Hold Time (tH)50 ns

Table 10: Parallel Loading Timing Information

t

F

L

VP

H

LOAD DA TA

DAT A LATCHED

DAT A INPUTS

D0 - D5

RX/TX

PRIVATE ENABLE

LOAD/LATCH

Figure 5: Parallel Load Timing

6.3 Packaging

PackageTolerances

NOTE: All dimensions in inches (mm.)

Angles are in degrees

A B C D E

H

P

F G

TYP. MAX.MIN.DIM.

K

J

W

T Y

0.435 (11.05)

0.051 (1.30)

0.009 (0.22)

6°

30°

0.409 (10.40)

0.146 (3.70)

0.417 (10.60)

0.049 (1.24)

0.006 (0.152)

0.250 (6.35)

0.023 (0.58)

0.047 (1.19)

0.022 (0.55)0.018 (0.45)

0.380 (9.61)

0.128 (3.25)

0.048 (1.22)

45°

F

G

P

A

D

B

E

PIN 1

W

C

J

K

Y

W

H

T

Figure 6: 24-pin PLCC Mechanical Outline:

Order as part no. MX375LH

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A B C D E

MAX.MIN.DIM.

F

J

G H

.045x45

.453 (11.51)

.050 (1.27)

.165 (4.20) .026 (0.66)

.070 (1.78)

.017 (0.43) .410 (10.41)

.450 (11.43) .485 (12.32)

NOTE: All dimensions in inches (mm.)

Angles are in degrees

Packa geTolerances

F

E

G

D

A

pin 1

B

C

H

J

.495 (12.57)

typical .180 (4.57) .030 (0.76) .021 (0.53) .430 (10.92)

typical .085 (2.16)

Figure 7: 28-pin PLCC Mechanical Outline:

Order as part no. MX375LH8

NOTE: All dimensions in inches (mm.)

Angles are in degrees

Pac kageTolerances

A B C E

E1

H

TYP. MAX.MIN.DIM.

J

J1

P Y

T

K L

0.220 (5.59)

0.555 (14.04)

0.670 (17.02)

7°

0.160 (4.05)

1.47 (37.20)

0.160 (4.05)

0.100 (2.54)

0.125 (3.16)

0.600 (15.24)

0.590 (14.99) 0.625 (15.88)

0.015 (0.38) 0.045 (1.14)

0.010 (0.25)

0.013 (0.33) 0.021 (0.53)

0.060 (1.52)

0.066 (1.67) 0.074 (1.88)

1.440 (36.44)

0.530 (13.41)

B

A

PIN1

T

E

E1

Y

J1

P

C

H

K L

J

Figure 8: 28-pin PDIP Mechanical Outline:

Order as part no. MX375P

Pvt

SQUELCHTM CTCSS Encoder/Decoder 15 MX375

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

E

E1

T

B

A

PIN1

H

K

L

F

J1

J

C

K1

P

NOTE: All dimensions in inches (mm.)

Angles are in degrees

Pac kageTolerances

A B C

E

E1

F

H

TYP. MAX.

MIN.

DIM.

J

J1

P

T

K1

K

L

0.230 (5.84)

0.530 (13.45)

0.715 (18.14)

0.171 (4.34)

1.460 (37.08)

0.165 (4.19)

0.100 (2.54)

0.115 (2.92)

0.640 (16.26)

0.608 (15.43) 0.618 (15.70)

1.300 (33.02)

0.015 (0.38)

0.0102 (0.259)

0.018 (0.46)

0.050 (1.27)

0.075 (1.91)

0.080 (2.03)

1.440 (36.58)

0.510 (12.94)

0.050 (1.27)

0.055 (1.39)

0.0090 (0.228)

Figure 9: 28-pin CDIP Mechanical Outline:

Order as part no. MX375J

Datasheet MX375J, MX375LH, MX375LH8, MX375P Datasheet (MX COM)

Specifications and Main Features

Frequently Asked Questions

User Manual