Datasheet MX29LV040QC-55, MX29LV040QC-70, MX29LV040QC-90, MX29LV040QI-70, MX29LV040QI-90 Datasheet (MXIC)

FEA TURES

ADVANCE INFORMATION

MX29LV040

4M-BIT [512K x 8] CMOS SINGLE VOLTAGE

3V ONLY EQUAL SECTOR FLASH MEMORY

• Extended single - supply voltage range 2.7V to 3.6V

• 524,288 x 8 only

• Single power supply operation

- 3.0V only operation for read, erase and program
operation

• Fast access time: 55R/70/90ns

• Low power consumption

- 20mA maximum active current

- 0.2uA typical standby current

• Command register architecture

- 8 equal sector of 64K-Byte each

- Byte Programming (9us typical)

- Sector Erase (Sector structure 64K-Byte x8)

• Auto Erase (chip & sector) and Auto Program

- Automatically erase any combination of sectors with
Erase Suspend capability.

- Automatically program and verify data at specified
address

• Erase suspend/Erase Resume

- Suspends sector erase operation to read data from,
or program data to, any sector that is not being erased,

GENERAL DESCRIPTION

then resumes the erase.

• Status Reply

- Data polling & Toggle bit for detection of program and
erase operation completion.

• Sector protection

- Hardware method to disable any combination of
sectors from program or erase operations

- Any combination of sectors can be erased with erase
suspend/resume function.

- Tempoary sector unprotect allows code changes in
previously locked sectors.

• 100,000 minimum erase/program cycles

• Latch-up protected to 100mA from -1V to VCC+1V

• Low VCC write inhibit is equal to or less than 2.3V

• Package type:

- 32-pin PLCC

- 32-pin TSOP

• Compatibility with JEDEC standard

- Pinout and software compatible with single-power
supply Flash

The MX29LV040 is a 4-mega bit Flash memory orga­nized as 512K bytes of 8 bits. MXIC's Flash memories
offer the most cost-effective and reliable read/write non­volatile random access memory. The MX29LV040 is
packaged in 32-pin PLCC and TSOP. It is designed to
be reprogrammed and erased in system or in standard
EPROM programmers.

The standard MX29L V040 off ers access time as fast as
55ns, allowing operation of high-speed microprocessors
without wait states. To eliminate bus contention, the
MX29LV040 has separate chip enable (CE) and output
enable (OE) controls.

MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29LV040 uses a command register to manage this
functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels

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during erase and programming, while maintaining maxi­mum EPROM compatibility.

MXIC Flash technology reliably stores memory contents
even after 100,000 erase and prog ram cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy­cling. The MX29LV040 uses a 2.7V~3.6V VCC supply
to perform the High Reliability Erase and auto Program/
Erase algorithms.

The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro­tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.

1

PIN CONFIGURATIONS

MX29LV040

32 TSOP (Standard T ype) (8mm x 20mm)

A11

A13
A14
A17

WE

VCC

A18
A16
A15
A12

1
2

A9

3

A8

4
5
6
7
8
9
10
11
12
13

A7

14

A6

15

A5

16

A4

MX29LV040

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

SECTOR STRUCTURE

T able 1. MX29L V040 SECTOR ADDRESS T ABLE

Sector A1 8 A1 7 A1 6 Address Range

SA0 0 0 0 00000h-0FFFFh
SA1 0 0 1 10000h-1FFFFh
SA2 0 1 0 20000h-2FFFFh
SA3 0 1 1 30000h-3FFFFh
SA4 1 0 0 40000h-4FFFFh
SA5 1 0 1 50000h-5FFFFh
SA6 1 1 0 60000h-6FFFFh
SA7 1 1 1 70000h-7FFFFh

OE
A10
CE
Q7
Q6
Q5
Q4
Q3
GND
Q2
Q1
Q0
A0
A1
A2
A3

32 PLCC

A12

A15

A16

A18

VCCWEA17

4

5

A7
A6
A5
A4

9

A3
A2
A1
A0

13

Q0

14 17 20

Q1

1

32

MX29LV040

Q2

Q3Q4Q5

GND

30

29

25

21

Q6

PIN DESCRIPTION

SYMBOL PIN NAME

A0~A18 Address Input
Q0~Q7 Data Input/Output
CE Chip Enable Input
WE Write Enable Input
OE Output Enable Input
GN D Ground Pin
VC C +3.0V single power supply

A14
A13
A8
A9
A11
OE
A10
CE
Q7

Note:All sectors are 64 Kbytes in size.

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2

BLOCK DIAGRAM

MX29LV040

CE
OE

WE

A0-A18

CONTROL
INPUT

LOGIC

ADDRESS

LATCH

AND

BUFFER

PROGRAM/ERASE

HIGH VOLT A GE

X-DECODER

MX29L V040

FLASH
ARRA Y

Y-DECODER

Y-PASS GATE

SENSE

AMPLIFIER

PGM

DATA

ARRAY

SOURCE

HV

HV

WRITE

STATE

MACHINE

(WSM)

STATE

REGISTER

COMMAND
DATA

DECODER

COMMAND

DATA LATCH

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Q0-Q7

PROGRAM

DATA LATCH

I/O BUFFER

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3

MX29LV040

AUTOMATIC PROGRAMMING

The MX29L V040 is byte prog rammable using the A uto­matic Programming algorithm. The A utomatic Program­ming algorithm makes the external system do not need
to have time out sequence nor to verify the data pro­grammed. The typical chip programming time at room
temperature of the MX29L V040 is less than 10 seconds.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
T ypical erasure at room temper ature is accomplished in
less than 11 second. The Automatic Erase algorithm
automatically programs the entire array prior to electri­cal erase. The timing and v erification of electrical erase
are controlled internally within the device.

AUTOMATIC SECTOR ERASE

The MX29L V040 is sector(s) erasable using MXIC's A uto
Sector Erase algorithm. The Automatic Sector Erase
algorithm automatically programs the specified sector(s)
prior to electrical erase. The timing and verification of
electrical erase are controlled internally within the de­vice. An erase operation can erase one sector , multiple
sectors, or the entire device.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm requires the
user to only write program set-up commands (including
2 unlock write cycle and A0H) and a program command
(program data and address). The device automatically
times the programming pulse width, provides the pro­gram verification, and counts the number of sequences.
The device provides an unlock bypass mode with faster
programming. Only two write cycles are needed to pro­gram a word or byte, instead of f our . A status bit similar
to DATA polling and a status bit toggling between con­secutive read cycles, provide feedback to the user as
to the status of the programming operation. Refer to write
operation status-table6, for more information on these
status bits.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stan­dard microprocessor write timings. The device will auto­matically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecu­tive read cycles provides feedback to the user as to the
status of the erasing operation.

Register contents serve as inputs to an internal state­machine which controls the erase and programming cir­cuitry . During write cycles, the command register inter­nally latches address and data needed for the program­ming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of WE or CE, whichev er hap­pens first.

MXIC's Flash technology combines years of EPROM
experience to produce the highest lev els of quality, reli­ability, and cost effectiveness. The MX29LV040 electri­cally erases all bits simultaneously using Fowler­Nordheim tunneling. The bytes are prog rammed by us­ing the EPROM programming mechanism of hot elec­tron injection.

During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis­ter to respond to its full command set.

AUTOMATIC SELECT

The automatic select mode provides manufacturer and
device identification, and sector protection verification,
through identifier codes output on Q7~Q0. This mode is
mainly adapted for programming equipment on the de­vice to be programmed with its programming algorithm.
When programming by high voltage method, automatic
select mode requires VID (11.5V to 12.5V) on address
pin A9 and other address pin A6, A1, and A0 as referring
to Table 2. In addition, to access the automatic select
codes in-system, the host can issue the automatic se

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4

MX29LV040

lect command through the command register without
requiring VID , as sho wn in table 3.

T o v erify whether or not sector being protected, the sec­tor address must appear on the appropriate highest or­der address bit (see Table 1 and Table 2). The rest of
address bits, as shown in table3, are don't care. Once
all necessary bits have been set as required, the pro­gramming equipment may read the corresponding iden­tifier code on Q7~Q0.

T ABLE 2. MX29LV040 AUTOMA TIC SELECT MODE OPERA TION

A18 A15 A9 A8 A6 A5 A1 A0

Description CE OE WE | | | | Q7~Q0

A16 A10 A7 A2

Read Silicon ID L L H X X VID X L X L L C2H
Manfacturer Code
Read Silicon ID L L H X X VID X L X L H 4FH

01H

Sector Protection L L H SA X VID X L X H L (protected)
Verification 00H

(unprotected)

NOTE:SA=Sector Address, X=Don't Care, L=Logic Lo w , H=Logic High

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MX29LV040

T ABLE 3. MX29LV040 COMMAND DEFINITIONS

First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus

Command Bus Cycle Cycle Cycle Cycle Cycle Cycle

Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Reset 1 XXXH F0H
Read 1 RA RD
Read Manufacturer ID 4 555H AAH 2AAH 5 5H 555H 90H X00H C2H
Read Silicon ID 4 555H AAH 2AAH 55 H 555H 90H X01H 4FH
Sector Protect 4 555H AAH 2AAH 55H 555H 90H (SA) 00H
Verify x02H 01H
Porgram 4 555H AAH 2AAH 5 5 H 555H A0H PA PD
Chip Erase 6 555H AAH 2AAH 5 5H 555H 80H 555H AAH 2AAH 55H 555H 10H
Sector Erase 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H
Sector Erase Suspend 1 XXXH B 0H
Sector Erase Resume 1 XXXH 30 H

Note:

1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacturer code,A1=0, A0 = 1 for device code. A2-A18=do not care.
(Refer to table 2)
DDI = Data of Device identifier : C2H for manufacture code, 4FH for device code.
X = X can be VIL or VIH
RA=Address of memory location to be read.
RD=Data to be read at location RA.

2.PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA.
SA = Address of the sector to be erased.

3. For Sector Protect V erify operation:If read out data is 01H, it means the sector has been protected. If read out data is 00H, it
means the sector is still not being protected.

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6

COMMAND DEFINITIONS

MX29LV040

Device operations are selected by writing specific ad­dress and data sequences into the command register.
Writing incorrect address and data values or writing them

sequences. Note that the Erase Suspend (B0H) and
Erase Resume (30H) commands are valid only while the

Sector Erase operation is in progress.
in the improper sequence will reset the device to the
read mode. Table 3 defines the valid register command

T ABLE 4. MX29LV040 BUS OPERATION

ADDRESS

DESCRIPTION CE OE WE A18 A15 A9 A8 A6 A5 A1 A0 Q0~Q7

A16 A10 A7 A2

Read L L H AIN Dout
Write L H L AIN DIN(3)
Reset X X X X High Z
Output Disable L H H X High Z
Standby Vcc±0.3V X X X High Z
Sector Protect L H L SA X X X L X H L X
Chip Unprotect L H L X X X X H X H L X
Sector Protection Verify L L H SA X VID X L X H L CODE(5)

NOTES:

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3.

2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.

3. Refer to Table 3 for valid Data-In during a write operation.

4. X can be VIL or VIH, L=Logic Low=VIL, H=Logic High=VIH.

5. Code=00H/XX00H means unprotected.
Code=01H/XX01H means protected.

6. A18~A13=Sector address for sector protect.

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MX29LV040

REQUIREMENTS FOR READING ARRAY
DATA

To read array data from the outputs, the system must
drive the CE and OE pins to VIL. CE is the pow er control
and selects the device. OE is the output control and gates
array data to the output pins. WE should remain at VIH.

The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory contect
occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid address on
the device address inputs produce valid data on the device
data outputs. The device remains enab led for read access
until the command register contents are altered.

WRITE COMMANDS/COMMAND
SEQUENCES

T o program data to the de vice or erase sectors of memory
, the sysytem must drive WE and CE to VIL, and OE to
VIH.

Refer to the Autoselect Mode and Autoselect Command
Sequence section for more information.

ICC2 in the DC Characteristics table represents the
active current specification for the write mode. The "A C
Characteristics" section contains timing specification
table and timing diagrams for write operations.

STANDBY MODE

When the sysytem is not reading or writing to the de­vice, it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde­pendent of the OE input.

The device enters the CMOS standby mode when the
CE pin is both held at VCC±0.3V. (Note that this is a
more restricted voltage range than VIH.) If CE is held at
VIH, but not within VCC±0.3V, the device will be in the
standby mode, but the standby currect will be greater.
The device requires standard access time (tCE) for read
access when the device is in either of these standby
modes, before itis ready to read data.

The device features an Unlock Bypass mode to facilitate
faster programming. Once the device enters the Unlock
Bypass mode, only two write cycles are required to
program a byte, instead of four. The "byte Program
Command Sequence" section has details on
programming data to the device using both standard and
Unlock Bypass command sequences.

An erase operation can erase one sector , multiple sectors
, or the entire device. Table indicates the address space
that each sector occupies. A "sector address" consists
of the address bits required to uniquely select a sector.
The "Writing specific address and data commands or
sequences into the command register initiates device
operations. Table 3 defines the valid register command
sequences. Writing incorrect address and data values or
writing them in the improper sequence resets the device
to reading array data."section has details on erasing a
sector or the entire chip, or suspending/resuming the erase
operation.

After the system writes the autoselect command
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal
reqister (which is separate from the memory array) on
Q7-Q0. Standard read cycle timings apply in this mode.

If the device is deselected during erasure or program­ming, the device draws active current until the operation
is completed.

ICC3 in the DC Characteristicstable represents the
standby current specification.

OUTPUT DISABLE

With the OE input at a logic high level (VIH), output from
the devices are disabled. This will cause the output pins
to be in a high impedance state.

READ/RESET COMMAND

The read or reset operation is initiated by writing the
read/reset command sequence into the command reg­ister. Microprocessor read cycles retrieve array data.
The device remains enabled for reads until the command
register contents are altered.

If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid com­mand must then be written to place the device in the
desired state.

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8

MX29LV040

SILICON-ID-READ COMMAND

Flash memories are intended for use in applications where
the local CPU alters memory contents. As such, manu­facturer and device codes must be accessible while the
device resides in the target system. PROM program­mers typically access signature codes by raising A9 to
a high voltage(VID). Howev er, m ultiplexing high voltage
onto address lines is not generally desired system de­sign practice.

The MX29LV040 contains a Silicon-ID-Read operation
to supple traditional PROM programming methodology.
The operation is initiated by writing the read silicon ID
command sequence into the command register. Fol­lowing the command write, a read cycle with A1=VIL,
A0=VIL retrieves the manufacturer code of C2H. A read
cycle with A1=VIL, A0=VIH returns the device code of
4FH for MX29LV040.

SET-UP AUTOMATIC CHIP/SECTOR ERASE
COMMANDS

Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed b y writing the
"set-up" command 80H. Two more "unlock" write cy­cles are then followed by the chip erase command 10H.

The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the Au­tomatic Chip Erase. Upon executing the Automatic Chip
Erase, the device will automatically program and verify
the entire memory for an all-zero data pattern. When the
device is automatically verified to contain an all-zero
pattern, a self-timed chip erase and verify begin. The
erase and verify operations are completed when the data
on Q7 is "1" at which time the device returns to the
Read mode. The system is not required to pro vide any
control or timing during these operations.

When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array(no
erase verification command is required).

If the Erase operation was unsuccessful, the data on
Q5 is "1"(see Table 6), indicating the erase operation
exceed internal timing limit.

The automatic erase begins on the rising edge of the
last WE or CE pulse, whichever happens first in the
command sequence and terminates when the data on
Q7 is "1" and the data on Q6 stops toggling for two con­secutive read cycles, at which time the device returns
to the Read mode.

T ABLE 5. EXP ANDED SILICON ID CODE

Pins A0 A1 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code(Hex)
Manufacture code VIL VIL X 1 0 0 0 0 1 0 C2 H
Device code VIH VIL 0 1 0 0 1 1 1 1 4FH
Sector Protection Verification VIL VIH 0 0 0 0 0 0 0 0 00H (Unprotected)

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MX29LV040

READING ARRAY DATA

The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read arra y data
after completing an Automatic Program or Automatic
Erase algorithm.

After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys­tem can read array data using the standard read tim­ings, except that if it reads at an address within erase­suspended sectors, the device outputs status data. After
completing a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception. See rase Suspend/Erase
Resume Commands” for more infor-mation on this mode.
The system
able the device for reading array data if Q5 goes high, or
while in the autoselect mode. See the "Reset Command"
section, next.

must issue the reset command to re-en-

RESET COMMAND

Writing the reset command to the device resets the
device to reading array data. Address bits are don't care
for this command.

The reset command may be written between the se­quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ignores
reset commands until the operation is complete.

The reset command may be written between the se­quence cycles in a program command sequence be-fore
programming begins. This resets the device to reading
array data (also applies to programming in Erase
Suspend mode). Once prog ramming begins ,how ever, the
device ignores reset commands until the operation is
complete.

The reset command may be written between the se­quence cycles in an SILICON ID READ command
sequence. Once in the SILICON ID READ mode, the
reset command
data (also applies to SILICON ID READ during Erase
Suspend).

must be written to return to reading array

SECTOR ERASE COMMANDS

The Automatic Sector Erase does not require the de­vice to be entirely pre-programmed prior to executing
the Automatic Sector Erase Set-up command and Au­tomatic Sector Erase command. Upon executing the
Automatic Sector Erase command, the device will auto­matically program and verify the sector(s) memory for
an all-zero data pattern. The system is not required to
provide any control or timing during these operations.

When the sector(s) is automatically verified to contain
an all-zero pattern, a self-timed sector erase and verify
begin. The erase and verify operations are complete
when the data on Q7 is "1" and the data on Q6 stops
toggling for two consecutive read cycles, at which time
the device returns to the Read mode. The system is not
required to provide any control or timing during these
operations.

When using the Automatic sector Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verification command is required). Sector
erase is a six-bus cycle operation. There are two "un­lock" write cycles. These are followed by writing the
set-up command 80H. Two more "unlock" write cycles
are then followed by the sector erase command 30H.
The sector address is latched on the falling edge of WE
or CE, whichever happens later , while the command(data)
is latched on the rising edge of WE or CE, whichever
happens first. Sector addresses selected are loaded
into internal register on the sixth falling edge of WE or
CE, whichever happens later. Each successive sector
load cycle started by the falling edge of WE or CE,
whichever happens later must begin within 50us from
the rising edge of the preceding WE or CE, whichev er
happens first. Otherwise, the loading period ends and
internal auto sector erase cycle starts. (Monitor Q3 to
determine if the sector erase timer window is still open,
see section Q3, Sector Erase Timer .) Any command other
than Sector Erase(30H) or Erase Suspend(B0H) during
the time-out period resets the device to read mode.

If Q5 goes high during a program or erase operation,
writing the reset command returns the device to read­ing array data (also applies during Erase Suspend).

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T able 6. Write Operation Status

Status Q7 Q6 Q5 Q3 Q2

MX29LV040

(Note1) (Note2)

Byte Program in Auto Program Algorithm Q7 Toggle 0 N/A N o

Auto Erase Algorithm 0 Toggle 0 1 Toggle

Erase Suspend Read 1 No 0 N/A Toggle
(Erase Suspended Sector) Toggle

In Progress

Erase Suspended Mode Erase Suspend Read Data Data Data Data Data

(Non-Erase Suspended Sector)
Erase Suspend Program Q7 Toggle 0 N/A N/A

Byte Program in Auto Program Algorithm Q7 Toggle 1 N/A N o

Exceeded
Time Limits Auto Erase Algorithm 0 Toggle 1 1 Toggle

Erase Suspend Program Q7 Toggle 1 N/A N/A

Toggle

Toggle

Note:

1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.

2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.
See "Q5:Exceeded Timing Limits " for more information.

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MX29LV040

ERASE SUSPEND

This command only has meaning while the state ma­chine is executing Automatic Sector Erase operation,
and therefore will only be responded during Automatic
Sector Erase operation. When the Erase Suspend com­mand is written during a sector erase operation, the de­vice requires a maximum of 100us to suspend the erase
operations. However , When the Erase Suspend command
is written during the sector erase time-out, the device
immediately terminates the time-out period and suspends
the erase operation. After this command has been ex­ecuted, the command register will initiate erase suspend
mode. The state machine will return to read mode auto­matically after suspend is ready . At this time, state ma­chine only allows the command register to respond to
the Read Memory Array, Erase Resume and program
commands.

The system can determine the status of the program
operation using the Q7 or Q6 status bits, just as in the
standard program operation. After an erase-suspend pro­gram operation is complete, the system can once again
read array data within non-suspended sectors.

ERASE RESUME

This command will cause the command register to clear
the suspend state and return back to Sector Erase mode
but only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions. Another Erase Suspend command can
be written after the chip has resumed erasing.

AUTOMATIC PROGRAM COMMANDS

T o initiate Automatic Progr am mode, A three-cycle com­mand sequence is required. There are two "unlock" write
cycles. These are f ollowed by writing the Automatic Pro­gram command A0H.

Once the Automatic Program command is initiated, the
next WE pulse causes a tr ansition to an active program­ming operation. Addresses are latched on the falling
edge, and data are internally latched on the rising edge
of the WE or CE, whichever happens first. The rising
edge of WE or CE, whiche ver happens first, also begins
the programming operation. The system is not required
to provide further controls or timings. The device will
automatically provide an adequate internally generated

program pulse and verify margin.
The device provides Q2, Q3, Q5, Q6, Q7 to determine

the status of a write operation. If the program operation
was unsuccessful, the data on Q5 is "1"(see Table 7),
indicating the program operation exceed internal timing
limit. The automatic programming operation is completed
when the data read on Q6 stops toggling for two con­secutive read cycles and the data on Q7 and Q6 are
equivalent to data written to these two bits, at which
time the device returns to the Read mode(no program
verify command is required).

WORD/BYTE PROGRAM COMMAND SEQUENCE

The device programs one byte of data for each program
operation. The command sequence requires four bus
cycles, and is initiated by writing two unlock write cycles,
followed by the program set-up command. The program
address and data are written next, which in turn initiate
the Embedded Program algorithm. The system is
required to provide further controls or timings. The device
automatically generates the program pulses and verifies
the programmed cell margin. Table 3 shows the address
and data requirements for the byte program command
sequence.

When the Embedded Program algorithm is complete,
the device then returns to reading array data and
addresses are no longer latched. The system can
determine the status of the program operation by using
Q7, Q6, or RY/BY. See "Write Operation Status" for
information on these status bits.

Any commands written to the device during the Em­bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the programming
operat ion. The Byte Prog ram command sequence should
be reinitiated once the device has reset to reading array
data, to ensure data integrity.

Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed from a
"0" back to a "1". Attempting to do so may halt the
operation and set Q5 to "1" ,” or cause the Data Polling
algorithm to indicate the operation was successful.
However, a succeeding read will show that the data is
still "0". Only erase operations can convert a "0" to a
"1".

not

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12

MX29LV040

WRITE OPERSTION STATUS

The device provides several bits to determine the sta­tus of a write operation: Q2, Q3, Q5, Q6 and Q7. Table
10 and the following subsections describe the functions
of these bits. Q7 and Q6 each offer a method for deter­mining whether a program or erase operation is com­plete or in progress. These three bits are discussed first.

Q7: Data Polling

The Data Polling bit, Q7, indicates to the host sys-tem
whether an Automatic Algorithm is in progress or com­pleted, or whether the device is in Erase Suspend. Data
Polling is v alid after the rising edge of the final WE pulse
in the program or erase command sequence.

During the Automatic Program algorithm, the device out­puts on Q7 the complement of the datum programmed
to Q7. This Q7 status also applies to progr amming dur­ing Er ase Suspend. When the Automatic Program algo­rithm is complete, the device outputs the datum pro­grammed to Q7. The system must provide the progr am
address to read valid status information on Q7. If a pro­gram address falls within a protected sector, Data Poll­ing on Q7 is active for approximately 1 us, then the de­vice returns to reading array data.

on the following read cycles. This is because Q7 may
change asynchr onously with Q0-Q6 while Output En­able (OE) is asserted low.

Q6:Toggle BIT I

Toggle Bit I on Q6 indicates whether an Automatic Pro­gram or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address, and is valid
after the rising edge of the final WE or CE, whichever
happens first, in the command sequence(prior to the pro­gram or erase operation), and during the sector time­out.

During an Automatic Program or Erase algorithm opera­tion, successive read cycles to any address cause Q6
to toggle. The system may use either OE or CE to con­trol the read cycles. When the operation is complete , Q6
stops toggling.

After an erase command sequence is written, if all sec­tors selected for erasing are protected, Q6 toggles and
returns to reading array data. If not all selected sectors
are protected, the Automatic Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are protected.

During the Automatic Erase algorithm, Data Polling pro­duces a "0" on Q7. When the Automatic Erase algo­rithm is complete, or if the device enters the Erase Sus­pend mode, Data P olling produces a "1" on Q7. This is
analogous to the complement/true datum out-put de­scribed for the Automatic Program algorithm: the erase
function changes all the bits in a sector to "1" prior to
this, the device outputs the "complement,” or "0". ” The
system must provide an address within any of the sec­tors selected for erasure to read valid status information
on Q7.

After an erase command sequence is written, if all sec­tors selected for erasing are protected, Data P olling on
Q7 is active for approximately 100 us, then the device
returns to reading array data. If not all selected sectors
are protected, the Automatic Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are protected.

When the system detects Q7 has changed from the
complement to true data, it can read valid data at Q7-Q0

The system can use Q6 and Q2 together to determine
whether a sector is actively erasing or is erase sus­pended. When the de vice is actively erasing (that is, the
Automatic Erase algorithm is in progress), Q6 toggling.
When the device enters the Erase Suspend mode, Q6
stops toggling. Ho wever, the system must also use Q2
to determine which sectors are erasing or erase-sus­pended. Alternatively, the system can use Q7.

If a program address falls within a protected sector, Q6
toggles for approximately 2 us after the program com­mand sequence is written, then returns to reading array
data.

Q6 also toggles during the erase-suspend-program mode,
and stops toggling once the Automatic Program algo­rithm is complete.

Table 6 shows the outputs f or Toggle Bit I on Q6.

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13

MX29LV040

Q2:Toggle Bit II

The "T oggle Bit II" on Q2, when used with Q6, indicates
whether a particular sector is actively eraseing (that is,
the Automatic Erase alorithm is in process), or whether
that sector is erase-suspended. Toggle Bit II is valid
after the rising edge of the final WE or CE, whichever
happens first, in the command sequence.

Q2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use either OE or CE to control the read
cycles.) But Q2 cannot distinguish whether the sector
is actively erasing or is erase-suspended. Q6, by com­parison, indicates whether the device is actively eras­ing, or is in Erase Suspend, but cannot distinguish which
sectors are selected for erasure. Thus , both status bits
are required for sectors and mode information. Refer to
Table 6 to compare outputs for Q2 and Q6.

Reading Toggle Bits Q6/ Q2

Whenever the system initially begins reading toggle bit
status, it must read Q7-Q0 at least twice in a row to
determine whether a toggle bit is toggling. T ypically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system
can read array data on Q7-Q0 on the following read cycle.

Howe v e r, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys­tem also should note whether the value of Q5 is high
(see the section on Q5). If it is, the system should then
determine again whether the toggle bit is toggling, since
the toggle bit may have stopped toggling just as Q5 went
high. If the toggle bit is no longer toggling, the device
has successfuly completed the program or erase opera­tion. If it is still toggling, the device did not complete the
operation successfully, and the system must write the
reset command to return to reading array data.

The remaining scenario is that system initially determines
that the toggle bit is toggling and Q5 has not gone high.
The system may continue to monitor the toggle bit and
Q5 through successive read cycles, determining the sta­tus as described in the previous paragraph. Alterna­tively, it may choose to perform other system tasks. In

this case, the system must start at the beginning of the
algorithm when it returns to determine the status of the
operation.

Q5
Exceeded Timing Limits

Q5 will indicate if the program or erase time has ex­ceeded the specified limits(internal pulse count). Under
these conditions Q5 will produce a "1". This time-out
condition indicates that the program or erase cycle was
not successfully completed. Data Polling and Toggle Bit
are the only operating functions of the device under this
condition.

If this time-out condition occurs during sector erase op­eration, it specifies that a particular sector is bad and it
may not be reused. Howe ver , other sectors are still func­tional and may be used for the program or erase opera­tion. The device must be reset to use other sectors.
Write the Reset command sequence to the device, and
then execute prog ram or erase command sequence. This
allows the system to continue to use the other active
sectors in the device.

If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or com­bination of sectors are bad.

If this time-out condition occurs during the byte program­ming operation, it specifies that the entire sector con­taining that byte is bad and this sector maynot be re­used, (other sectors are still functional and can be re­used).

The time-out condition will not appear if a user tries to
program a non blank location without erasing. Please
note that this is not a device failure condition since the
device was incorrectly used.

Q3
Sector Erase Timer

After the completion of the initial sector erase command
sequence, the sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data Polling
and Toggle Bit are valid after the initial sector erase com­mand sequence.

P/N:PM0722

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14

MX29LV040

If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, Q3 may be
used to determine if the sector erase timer window is
still open. If Q3 is high ("1") the internally controlled
erase cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or
Toggle Bit. If Q3 is low ("0"), the device will accept
additional sector erase commands. To insure the com­mand has been accepted, the system software should
check the status of Q3 prior to and following each sub­sequent sector erase command. If Q3 were high on the
second status check, the command may not have been
accepted.

DATA PROTECTION

The MX29L V040 is designed to off er protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power transi­tion. During power up the device automatically resets
the state machine in the Read mode. In addition, with
its control register architecture, alteration of the memory
contents only occurs after successful completion of spe­cific command sequences. The device also incorpo­rates sever al features to prev ent inadvertent write cycles
resulting from VCC pow er-up and power-down transition
or system noise.

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns(typical) on CE or WE will
not initiate a write cycle.

POWER-UP SEQUENCE

The MX29LV040 powers up in the Read only mode. In
addition, the memory contents may only be altered after
successful completion of the predefined command se­quences.

SECTOR PROTECTION

The MX29LV040 features hardware sector protection.
This feature will disable both program and erase opera­tions for these sectors protected. T o activ ate this mode,
the programming equipment must force VID on address
pin A9 and OE (suggest VID = 12V). Programming of
the protection circuitry begins on the falling edge of the
WE pulse and is terminated on the rising edge. Please
refer to sector protect algorithm and waveform.

T o v erify programming of the protection circuitry , the pro­gramming equipment must force VID on address pin A9
( with CE and OE at VIL and WE at VIH). When A1=VIH,
A0=VIL, A6=VIL, it will produce a logical "1" code at
device output Q0 f or a protected sector . Otherwise the
device will produce 00H for the unprotected sector. In
this mode, the addresses,except for A1, are don't care.
Address locations with A1 = VIL are reserved to read
manufacturer and device codes.(Read Silicon ID)

It is also possible to determine if the sector is protected
in the system by writing a Read Silicon ID command.
Perf orming a read operation with A1=VIH, it will produce
a logical "1" at Q0 for the protected sector .

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE = VIL, CE
= VIH or WE = VIH. T o initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.

POWER SUPPLY DECOUPLING

In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected be­tween its VCC and GND .

P/N:PM0722

REV. 0.7, JUL. 12, 2001

15

CHIP UNPROTECT

The MX29LV040 also features the chip unprotect mode,
so that all sectors are unprotected after chip unprotect is
completed to incorporate any changes in the code. It is
recommended to protect all sectors before activating
chip unprotect mode.

To activate this mode, the programming equipment must
force VID on control pin OE and address pin A9. The CE
pins must be set at VIL. Pins A6 must be set to VIH.
Refer to chip unprotect algorithm and waveform for the
chip unprotect algorithm. The unprotection mechanism
begins on the falling edge of the WE pulse and is
terminated on the rising edge.

It is also possible to determine if the chip is unprotected
in the system by writing the Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
00H at data outputs(Q0-Q7) for an unprotected sector.

MX29LV040

It is noted that all sectors are unprotected after the chip
unprotect algorithm is completed.

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16

MX29LV040

ABSOLUTE MAXIMUM RATINGS

Storage T emperature

Plastic Packages . . . . . . . . . . . . . ..... -65oC to +150oC

Ambient T emperature

with Power Applied. . . . . . . . . . . . . ....-65oC to +125oC

V oltage with Respect to Ground

VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V

A9, OE, and

RESET (Note 2) . . . . . . . . . . . ....-0.5 V to +12.5 V

All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is -0.5 V.
During voltage transitions, input or I/O pins may over­shoot VSS to -2.0 V for periods of up to 20 ns. See
Figure 6. Maximum DC voltage on input or I/O pins is
VCC +0.5 V. During voltage transitions, input or I/O
pins may ov ershoot to VCC +2.0 V f or periods up to
20 ns.

2. Minimum DC input voltage on pins A9, OE, and
RESET is -0.5 V. During voltage transitions, A9, OE,
and RESET may ov ershoot VSS to -2.0 V for periods
of up to 20 ns. See Figure 6. Maximum DC input volt­age on pin A9 is +12.5 V which may overshoot to

14.0 V f or periods up to 20 ns.

3. No more than one output ma y be shorted to ground at
a time. Duration of the shor t circuit should not be
greater than one second.

OPERATING RATINGS

Commercial (C) Devices

Ambient Temperature (T

Industrial (I) Devices

Ambient Temperature (T

Extended (E) Devices

Ambient Temperature (T

V

CC Supply Voltages

V

CC for regulated voltage range . . . . . +3.0 V to 3.6 V

CC for full voltage range. . . . . . . . . . . +2.7 V to 3.6 V

V

Operating ranges define those limits between which the
functionality of the device is guaranteed.

A ) . . . . . . . . . . . . 0°C to +70°C

A ) . . . . . . . . . . -4 0 °C to +85°C

A ) . . . . . . . . . -5 5 °C to +125°C

Stresses above those listed under "Absolute Maximum
Rat-ings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device at these or any other conditions above those in­dicated in the operational sections of this data sheet is
not implied. Exposure of the device to absolute maxi­mum rating conditions for extended periods may affect
device reliability.

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17

MX29LV040

Table 8. CAPACITANCE TA = 25oC, f = 1.0 MHz

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS

CIN1 Input Capacitance 8 pF VIN = 0V
CIN2 Control Pin Capacitance 12 pF VIN = 0V
COUT Output Capacitance 12 pF VOUT = 0V

READ OPERATION

T able 9. DC CHARA CTERISTICS TA = 0oC T O 70oC, VCC = 2.7V to 3.6V

Symbol PARAMETER MIN. TYP MAX. UNIT CONDITIONS

ILI Input Leakage Current ± 1 uA VIN = VSS to VCC
ILIT A9 Input Leakage Current 35 uA VCC=VCC max; A9=12.5V
ILO Output Leakage Current ± 1 uA VOUT = VSS to VCC, VCC=VCC max
ICC1 VCC Active Read Currect 7 1 2 mA CE=VIL, OE=VIH @5MHz

2 4 mA @1MHz
ICC2 VCC Active write Currect 1 5 30 mA CE=VIL, OE=VIH
ICC3 VCC Standby Currect 0.2 5 uA CE;VCC ± 0.3V
ICC4 VCC Standby Currect 0.2 5 uA CE; VCC ± 0.3V

During Reset
ICC5 Automative sleep mode 0.2 5 uA VIH=VCC ± 0.3V;VIL=VSS ± 0.3V
VIL Input Low Voltage(Note 1) -0.5 0.8 V
VIH Input High Voltage 0.7xVCC VCC+ 0.3 V
VID Voltage for Auto

Select and Temporar y 11.5 12.5 V VCC=3.3V

Sector Unprotect
VOL Output Low Voltage 0.45 V IOL = 4.0mA, VCC= VCC min
VOH1 Output High Voltage(TTL) 0.85xVCC IOH = -2mA, VCC=VCC min
VOH2 Output High Voltage VCC-0.4 IOH = -100uA, VCC min

(CMOS)
VLKO Low VCC Lock-out 2.3 2.5 V

Voltage

NOTES:

1.VIL min. = -1.0V for pulse width is equal to or less than 50 ns.
VIL min. = -2.0V for pulse width is equal to or less than 20 ns.

2.VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns
If VIH is over the specified maximum value, read operation cannot be guaranteed.

3. Automatic sleep mode enable the low power mode when addresses remain stable for tACC +30ns.

P/N:PM0722

18

REV. 0.7, JUL. 12, 2001

MX29LV040

AC CHARACTERISTICS TA = -40oC to 85oC, VCC = 2.7V~3.6V

(TA = 0oC to 70oC, VCC = 3.3V

Table 11. READ OPERATIONS

29LV040-55R 29LV040-70 29LV040-90

SYMBOL PARAMETER MIN. MAX. MIN. MAX. MIN. MAX. UNIT CONDITIONS

tRC Read Cycle Time (Note 1) 55 70 90 ns
tACC Address to Output Delay 5 5 7 0 90 ns CE=OE=VIL
tCE CE to Output Delay 55 7 0 90 ns OE=VIL
tOE OE to Output Delay 30 30 35 ns CE=VIL
tDF OE High to Output Float (Note1) 0 25 0 25 0 30 ns CE=VIL
tOEH Output Enable Read 0 0 0 ns

Hold Time Toggle and 10 10 10 ns

Data Polling

tOH Address to Output hold 0 0 0 ns CE=OE=VIL

±±

±5% for MX29LV040-55R)

±±

TEST CONDITIONS:

• Input pulse levels: 0V/3.0V.

• Input rise and fall times is equal to or less than 5ns.

• Output load: 1 TTL gate + 100pF (Including scope and
jig), for 29LV040-90. 1 TTL gate + 30pF (Including
scope and jig) for 29LV040-70 & 29LV040-55R.

• Reference levels for measuring timing: 1.5V.

NOTE:

1. Not 100% tested.

2. tDF is defined as the time at which the output achieves
the open circuit condition and data is no longer driven.

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19

Figure 1. SWITCHING TEST CIRCUITS

MX29LV040

DEVICE UNDER

TEST

CL

CL=100pF Including jig capacitance
CL=30pF for MX29LV040-70 & MX29LV040-55R

Figure 2. SWITCHING TEST WAVEFORMS

3.0V

0V

INPUT

6.2K ohm

TEST POINTS

2.7K ohm

DIODES=IN3064

OR EQUIVALENT

OUTPUT

+3.3V

1.5V1.5V

P/N:PM0722

AC TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0".
Input pulse rise and fall times are < 5ns.

REV. 0.7, JUL. 12, 2001

20

Figure 3. READ TIMING WAVEFORMS

MX29LV040

tRC

Addresses

CE

WE

OE

Outputs

RESET

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VIH
VIL

HIGH Z

tOEH

tACC

tACC

ADD Valid

tCE

tOE

DAT A Valid

tDF

tOH

HIGH Z

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21

MX29LV040

AC CHARACTERISTICS TA = -40oC to 85oC, VCC = 2.7V~3.6V

(TA = 0oC to 70oC, VCC = 3.3V

Table 11. Erase/Program Operations

29LV040-55R 29LV040-70 29LV040-90

SYMBOL PARAMETER MIN. MAX. MIN. MAX. MIN. MAX. UNIT

tW C Write Cycle Time (Note 1) 5 5 70 9 0 ns
tAS Address Setup Time 0 0 0 ns
tAH Address Hold Time 45 4 5 4 5 ns
tDS Data Setup Time 3 5 3 5 45 ns
tD H Data Hold Time 0 0 0 ns
tOES Output Enable Setup Time 0 0 0 ns
tGHWL Read Recovery Time Before Write 0 0 0 ns

(OE High to WE Low)

tCS CE Setup Time 0 0 0 ns

±±

±5% for MX29LV040-55R)

±±

tC H CE Hold Time 0 0 0 ns
tWP Write Pulse Width 3 5 3 5 3 5 ns
tWPH Write Pulse Width High 3 0 30 3 0 ns
tWHWH1 Programming Operation (Note 2) 9(TYP.) 9(TYP.) 9(TYP.) us
tWHWH2 Sector Erase Operation (Note 2) 0.7(TYP.) 0.7(TYP.) 0.7(TYP.) sec
tVCS VCC Setup Time (Note 1) 5 0 5 0 5 0 us
tRB Recovery Time from RY/BY 0 0 0 ns
tBUSY Program/Erase Vaild to RY/BY Delay 90 9 0 9 0 us

NOTES:

1. Not 100% tested.

2. See the "Er ase and Programming P erformance" section for more information.

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22

MX29LV040

AC CHARACTERISTICS T A = -40

(T A = 0oC to 70oC, VCC = 3.3V

o

C to 85oC, VCC = 2.7V~3.6V

±±

±5% f or MX29LV004T/B-55R)

±±

Table 12. Alternate CE Controlled Erase/Program Operations

29LV040-55R 29LV040-70 29L V040-90

SYMBOL PARAMETER MIN. MAX. MIN. MAX. MIN. MAX. UNIT

tW C Write Cycle Time (Note 1) 5 5 70 70 ns
tAS Address Setup Time 0 0 0 ns
tAH Address Hold Time 45 45 45 ns
tDS Data Setup Time 35 35 45 ns
tDH Data Hold Time 0 0 0 ns
tOES Output Enable Setup Time 0 0 0 ns
tGHEL Read Recovery Time Before Write 0 0 0 ns
tWS WE Setup Time 0 0 0 ns
tWH WE Hold Time 0 0 0 ns
tCP CE Pulse Width 3 5 35 35 ns
tCPH CE Pulse Width High 30 30 30 ns
tWHWH1 Programming Operation(note2) 9(T yp.) 9(T yp .) 9(T yp .) us
tWHWH2 Sector Erase Operation (note2) 0.7(T yp .) 0.7(T yp .) 0.7(Typ .) sec

NOTE:

1. Not 100% tested.

2. See the "Er ase and Programming P erformance" section for more information.

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23

Figure 4. COMMAND WRITE TIMING WAVEFORM

MX29LV040

VCC

Addresses

WE

CE

OE

Data

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

3V

ADD Valid

tAS

tOES

tCS tCH

tWP

tDS

tAH

tWPH

tCWC

tDH

DIN

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24

AUTOMATIC PROGRAMMING TIMING
WAVEFORM

MX29LV040

One byte data is programmed. Verify in fast algorithm
and additional verification by external control are not re­quired because these operations are executed automati­cally by internal control circuit. Programming comple-

after automatic programming starts. Device outputs
DAT A during programming and DA TA after programming
on Q7.(Q6 is for toggle bit; see toggle bit, D ATA polling,
timing waveform)

tion can be verified by D A T A polling and toggle bit checking

Figure 5. AUTOMATIC PROGRAMMING TIMING WAVEFORM

Address

CE

OE

tWC

555h

tGHWL

tWP

tAS

PA

tAH

tCH

Read Status Data (last two cycle)Program Command Sequence(last two cycle)

PA PA

tWHWH1

WE

Data

RY/BY

VCC

tCS tWPH

tDS tDH

A0h

tVCS

NOTES:

1.PA=Program Address, PD=Program Data, DOUT is the true data the program address

PD

tBUSY

Status

DOUT

tRB

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25

Figure 6. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data A0H Address 555H

Write Program Data/Address

MX29LV040

Increment
Address

No

No

Verify Word Ok ?

Last Address ?

Auto Program Completed

Data Poll
from system

YES

YES

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26

Figure 7. CE CONTROLLED PR OGRAM TIMING W A VEFORM

MX29LV040

Address

WE

OE

CE

Data

555 for program
2AA for erase

tWC

tWH

tGHEL

tWS

tRH

tCP

tDS

tDH

PA for program
SA for sector erase
555 for chip erase

tAS

tAH

tCPH

A0 for program
55 for erase

Data Polling

tBUSY

PD for program
30 for sector erase
10 for chip erase

tWHWH1 or 2

PA

DQ7

DOUT

RESET

RY/BY

NOTES:

1.PA=Program Address, PD=Program Data, DOUT=Data Out, DQ7=complement of data written to device.

2.Figure indicates the last two bus cycles of the command sequence.

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27

AUTOMATIC CHIP ERASE TIMING WAVEFORM

MX29LV040

All data in chip are erased. External erase verification is
not required because data is verified automatically by
internal control circuit. Erasure completion can be veri-

matic erase starts. Device outputs 0 during erasure
and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle
bit, DATA polling, timing w avef orm)

fied by DAT A polling and toggle bit checking after auto-

Figure 8. AUTOMATIC CHIP ERASE TIMING WAVEFORM

Address

tWC

2AAh

CE

tGHWL

OE

tWP

tAS

555h

tAH

tCH

Read Status Data Erase Command Sequence(last two cycle)

VA VA

tWHWH2

WE

Data

RY/BY

VCC

tCS tWPH

tDS tDH

In

Progress

Complete

tRB

tVCS

55h

10h

tBUSY

NOTES:

SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").

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28

Figure 9. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 10H Address 555H

MX29LV040

NO

Data Pall from System

Data=FFh ?

YES

Auto Chip Erase Completed

P/N:PM0722

REV. 0.7, JUL. 12, 2001

29

AUTOMATIC SECTOR ERASE TIMING WAVEFORM

MX29LV040

Sector indicated by A13 to A18 are erased. External
erase verify is not required because data are verified
automatically by internal control circuit. Erasure comple-

ing after automatic erase starts. De vice outputs 0 dur­ing erasure and 1 after erasure on Q7.(Q6 is for toggle
bit; see toggle bit, D ATA polling, timing w avef orm)

tion can be verified by DAT A polling and toggle bit check-

Figure 10. AUTOMATIC SECTOR ERASE TIMING WAVEFORM

Read Status Data Erase Command Sequence(last two cycle)

Address

tWC

2AAh

CE

tGHWL

OE

tWP

tAS

SA

tAH

tCH

tWHWH2

VA VA

WE

Data

RY/BY

VCC

tCS tWPH

tDS tDH

In

Progress

Complete

tRB

tVCS

55h

30h

tBUSY

NOTES:

SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").

P/N:PM0722

REV. 0.7, JUL. 12, 2001

30

MX29LV040

Figure 11. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 30H Sector Address

Last Sector
to Erase

YES

Data Poll from System

Data=FFh

YES

Auto Sector Erase Completed

NO

NO

P/N:PM0722

REV. 0.7, JUL. 12, 2001

31

Figure 12. ERASE SUSPEND/ERASE RESUME FLOWCHART

START

Write Data B0H

MX29LV040

Toggle Bit checking Q6

not toggled

YES

Read Array or

Program

Reading or

Programming End

YES

Write Data 30H

Continue Erase

Another

Erase Suspend ?

YES

NO

NO

NO

ERASE SUSPEND

ERASE RESUME

P/N:PM0722

REV. 0.7, JUL. 12, 2001

32

MX29LV040

Figure 13. TIMING WAVEFORM FOR SECTOR PROTECT/UNPROTECT

VID

RESET

SA, A6

A1, A0

Data

CE

WE

OE

VIH

Valid*

Sector Protect or Sector Unprotect

Valid* Valid*

Verify

40h60h60h

1us

Sector Protect =150us
Sector Unprotect =15ms

Note: When sector protect, A6=0, A1=1, A0=0. When sector unprotect, A6=1, A1=1, A0=0.

Status

P/N:PM0722

REV. 0.7, JUL. 12, 2001

33

Figure 14. IN-SYSTEM SECTOR PROTECTION ALGORITHM

START

PLSCNT=1

RESET=VID

Wait 1us

MX29LV040

Increment PLSCNT

No

PLSCNT=25?

Yes

Device failed

First Write
Cycle=60H

Yes

Set up sector address

Write 60H to sector address

with A6=0, A1=1, A0=0

Wait 150us

Verify sector protect :

write 40H with A6=0,

A1=1, A0=0

Read from sector address

No

Data=01H

Yes

Protect another

sector?

No

?

Yes

Temporary Sector
Unprotect Mode

Reset PLSCNT=1

P/N:PM0722

No

Remove VID from RESET

Write reset command

Sector protect complete

REV. 0.7, JUL. 12, 2001

34

Figure 15. IN-SYSTEM SECTOR UNPROTECTION ALGORITHM

START

PLSCNT=1

RESET=VID

Wait 1us

MX29LV040

Increment PLSCNT

No

PLSCNT=1000?

First Write

Cycle=60H ?

All sector

protected?

Set up first sector address

Sector unprotect :

write 60H with

A6=1, A1=1, A0=0

Wait 50ms

Verify sector unprotect

write 40H to sector address

with A6=1, A1=1, A0=0

Read from sector address

with A6=1, A1=1, A0=0

No

Data=00H

Yes

Yes

No

No

?

Temporary Sector
Unprotect Mode

Protect all sectors

Set up next sector address

P/N:PM0722

Yes

Device failed

Yes

Last sector

verified?

No

Remove VID from RESET

Write reset command

Sector unprotect complete

35

Yes

REV. 0.7, JUL. 12, 2001

Figure 16. TIMING WAVEFORM FOR CHIP UNPROTECTION

A1

12V

3V

A9

tVLHT

A6

MX29LV040

12V

3V

OE

tVLHT

tWPP 2

WE

tOESP

CE

Data

A17-A12

Notes: tWPP1 (Write pulse width for sector protect)=100ns min.

tWPP2 (Write pulse width for sector unprotect)=100ns min.

tVLHT

tOE

Sector Address

Verify

00H

F0H

P/N:PM0722

REV. 0.7, JUL. 12, 2001

36

Figure 17. CHIP UNPROTECTION ALGORITHM

START

Protect All Sectors

PLSCNT=1

Set OE=A9=VID
CE=VIL,A6=1

Activate WE Pulse

MX29LV040

Increment

Sector Addr

Set Up First Sector Addr

Read Data from Device

No

Remove VID from A9

Write Reset Command

Time Out 50ms

Set OE=CE=VIL

A9=VID,A1=1

Data=00H?

Yes

All sectors have

been verified?

Yes

Chip Unprotect

Complete

No

Increment

PLSCNT

No

PLSCNT=1000?

Yes

Device Failed

P/N:PM0722

* It is recommended before unprotect whole chip, all sectors should be protected in advance.

REV. 0.7, JUL. 12, 2001

37

WRITE OPERATION STATUS

Figure 18. DATA POLLING ALGORITHM

Start

Read Q7~Q0

Add.=VA(1)

MX29LV040

Q7 = Data ?

No

No

NOTE : 1.VA=Valid address for programming

2.Q7 should be re-checked even Q5="1" because Q7 may change
simultaneously with Q5.

Q5 = 1 ?

Yes

Read Q7~Q0

Add.=VA

Q7 = Data ?

No

FAIL

(2)

Yes

Yes

Pass

P/N:PM0722

REV. 0.7, JUL. 12, 2001

38

Figure 19. TOGGLE BIT ALOGRITHM

Start

Read Q7-Q0

MX29LV040

Read Q7-Q0

Toggle Bit Q6 =

Toggle ?

YES

NO

Program/Erase Operation

Note:1.Read toggle bit twice to determine whether or not it is toggling.

2. Recheck toggle bit because it may stop toggling as Q5 change to "1".

Q5= 1?

YES

Read Q7~Q0 Twice

Toggle bit Q6=

Toggle?

YES

Not Complete,Write

Reset Command

(Note 1)

NO

(Note 1,2)

NO

Program/Erase

operation Complete

P/N:PM0722

REV. 0.7, JUL. 12, 2001

39

MX29LV040

Figure 20. DATA POLLING TIMINGS (DURING AUTOMATIC ALOGRITHMS)

tRC

Address

tACC

tCE

VAVAVA

CE

tCH

tOE

OE

tOEH

tDF

WE

tOH

DQ7

Q0-Q6

Complement

Status Data

tBUSY

Complement

Status Data

Valid DataTrue

Valid DataTrue

RY/BY

NOTES:

VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data read cycle.

High Z

High Z

P/N:PM0722

REV. 0.7, JUL. 12, 2001

40

MX29LV040

Figure 21. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALOGRITHMS)

tRC

Address

CE

OE

WE

Q6/Q2

RY/BY

tCH

tBUSY

tOEH

High Z

tACC

VA

tCE

tOE

tDF

tOH

Valid Status

(first raed)

VA

Valid Status

(second read) (stops toggling)

VA

Valid Data

VA

Valid Data

P/N:PM0722

NOTES:

VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle, and
array data read cycle.

REV. 0.7, JUL. 12, 2001

41

MX29LV040

Table 13. AC CHARACTERISTICS

Parameter Std Description Test Setup All Speed Options Unit

tREAD Y1 RESET PIN Low (During Automatic Algorithms) MAX 20 us

to Read or Write (See Note)

tREAD Y2 RESET PIN Low (NOT During Automatic MAX 5 00 ns

Algorithms) to Read or Write (See Note)
tRP RESET Pulse Width (During Automatic Algorithms) MIN 500 ns
tR H RESET High Time Before Read(See Note) MIN 50 ns
tRB RY/BY Recov ery Time(to CE, OE go lo w) MIN 0 ns

Note:Not 100% tested

Figure 22. RESET TIMING WAVFORM

RY/BY

CE, OE

RESET

RY/BY

CE, OE

tRH

tRP

tReady2

Reset Timing NOT during Automatic Algorithms

tReady1

tRB

RESET

P/N:PM0722

tRP

Reset Timing during Automatic Algorithms

REV. 0.7, JUL. 12, 2001

42

MX29LV040

Table 14. TEMPORARY SECTOR UNPROTECT

Parameter Std. Description T est Setup AllSpeed Options Unit
tVIDR VID Rise and Fall Time (See Note) Mi n 5 00 ns
tRSP RESET Setup Time for T empor ary Sector Unprotect Min 4 us

Note:
Not 100% tested

Figure 23. TEMPORARY SECTOR UNPROTECT TIMING DIAGRAM

12V

RESET

0 or Vcc

tVIDR

CE

WE

tRSP

RY/BY

Program or Erase Command Sequence

Figure 24. Q6 vs Q2 for Erase and Erase Suspend Operations

Enter Embedded

Erasing

WE

Q6

Erase

Erase

Suspend

Enter Erase

Suspend Program

Erase

Suspend

Program

Erase Suspend

Read

Erase

Resume

tVIDR

Erase

0 or Vcc

Erase

Complete

Q2

P/N:PM0722

NOTES:

The system can use OE or CE to toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended

REV. 0.7, JUL. 12, 2001

43

Figure 25. TEMPORAR Y SECT OR UNPROTECT ALGORITHM

Start

RESET = VID (Note 1)

Perform Erase or Program Operation

Operation Completed

RESET = VIH

Temporary Sector Unprotect Completed(Note 2)

MX29LV040

Note : 1. All protected sectors are temporary unprotected.

2. All previously protected sectors are protected again.

VID=11.5V~12.5V

P/N:PM0722

REV. 0.7, JUL. 12, 2001

44

Figure 26. ID CODE READ TIMING WAVEFORM

MX29LV040

VCC

ADD

A9

ADD

A0

A1

ADD

A2-A8

A10-A17

CE

WE

OE

VIH

VIL

VIH

VIL

VIH

VIH

VIH

VIL

VIL

VIL

VIH

VIL

3V

VID
VIH

VIL

tACC

tACC

tCE

tOE

tDF

DATA

Q0-Q15

VIH

VIL

DATA OUT

C2H/00C2H

tOH

tOH

DATA OUT

B9H/BAH (Byte)
22B9H/22BAH (Word)

P/N:PM0722

REV. 0.7, JUL. 12, 2001

45

MX29LV040

Table 15. ERASE AND PROGRAMMING PERFORMANCE(1)

LIMITS

PARAMETER MIN. TYP.(2) MAX.(3) UNITS

Sector Erase Time 0.7 15 sec
Chip Erase Time 11 sec
Byte Programming Time 9 30 0 us
Chip Programming Time 4.5 13.5 sec
Erase/Program Cycles 100,000 Cycles

Note: 1.Not 100% Tested, Excludes external system level o ver head.

2.Typical values measured at 25°C, 3V.

3.Maximum values measured at 25°C, 2.7V.

Table 16. LATCHUP CHARACTERISTICS

MIN. MAX.

Input Voltage with respect to GND on all pins except I/O pins -1.0V 12.5V
Input Voltage with respect to GND on all I/O pins -1.0V Vcc + 1.0V
Current -100mA +100mA
Includes all pins except Vcc. Test conditions: Vcc = 3.0V, one pin at a time.

P/N:PM0722

REV. 0.7, JUL. 12, 2001

46

MX29LV040

ORDERING INFORMATION

PLASTIC P ACKA GE

P ART NO . A CCESS TIME OPERA TING CURRENT ST ANDBY CURRENT P A CK AGE

(ns) MAX.(mA) MAX.(uA)

MX29L V040TC-55 55 3 0 5 32 Pin TSOP
MX29L V040TC-70 70 3 0 5 32 Pin TSOP
MX29L V040TC-90 90 3 0 5 32 Pin TSOP
MX29L V040QC-55 55 30 5 32 Pin PLCC
MX29L V040QC-70 70 3 0 5 32 Pin PLCC
MX29L V040QC-90 90 3 0 5 32 Pin PLCC
MX29L V040TI-70 70 30 5 32 Pin TSOP
MX29L V040TI-90 90 30 5 32 Pin TSOP
MX29L V040QI-70 70 30 5 32 Pin PLCC
MX29L V040QI-90 90 3 0 5 32 Pin PLCC

P/N:PM0722

REV. 0.7, JUL. 12, 2001

47

PACKAGE INFORMATION

32-PIN PLASTIC LEADED CHIP CARRIER (PLCC)

MX29LV040

P/N:PM0722

REV. 0.7, JUL. 12, 2001

48

32-PIN PLASTIC TSOP

MX29LV040

P/N:PM0722

REV. 0.7, JUL. 12, 2001

49

MX29LV040

Revision History

Revision No. Description Page Date

0.1 Added Read cycle time and Output enable hold time to READ P15 JUN/21/2000

Operation
Modify Erase/Program Operation table and timing waveform P17,21,23,25
Modify Program/Erase Algorithm flowchart P22,24,26
To added write operation status P 32

0.2 Modify Feature--10,000 minimum erase/program cycles-->100,000-- P1 JUL/18/2000

Modify General Description--even after 10,000 --->100,000 erase-- P1
Del Package type: 32-pin PDIP P1,2
Modify AC Characteristics tWHWH1 9/11(Typ.)-->9(Typ.) P21
Del Chip Programming Time--Word Mode P45
Modify Erase/Program Cycle:10,000-->100,000 P45

0.3 Delete Unlock Bypass Command Definitions P6 JAN/10/2001

Delete Unlock Bypass Command Sequence P13
Modify Table 10. DC Characteristics VCC=3V±10%-->2.7V to 3.6V P17

0.4 Modify Timing Waveform P25,27,28,30 FEB/07/2001

Modify Automatic Programming Algorithm Flowchart P26
Delete Figure 21. Toggle Bit Timings(During Embedded Algorithms) P4 1
Add Figure 19. Toggle Bit Alogrithm P39
Modify Absolute Maximum Ratings P17
Add Ordering Information--Industrial Grade P47

0.5 Change tBUSY spec. from 90ns to 90us P22 MAR/07/2001

0.6 Correct typing error P22 JUN/29/2001

Add tWPP1/tWPP2=100ns P36
To modify Package Information P48,49

0.7 Add 55ns spec P1,19,20,22 JUL/12/2001

P23,47

P/N:PM0722

REV. 0.7, JUL. 12, 2001

50

MX29LV040

MACRONIX INTERNATIONAL CO., LTD.

HEADQUARTERS:

TEL:[phone]
FAX:[phone]

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http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.

51