Datasheet MX29F400MT-B Datasheet (MXIC)

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FEA TURES

MX29F400T/B

4M-BIT [512Kx8/256Kx16] CMOS FLASH MEMORY

• 524,288 x 8/262,144 x 16 switchable

• Single power supply operation

- 5.0V only operation for read, erase and program operation

• Fast access time: 55/70/90/120ns

• Low power consumption

- 40mA maximum active current(5MHz)

- 1uA typical standby current

• Command register architecture

- Byte/word Programming (7us/12us typical)

- Sector Erase (Sector structure 16K-Bytex1, 8KBytex2, 32K-Bytex1, and 64K-Byte x7)

• Auto Erase (chip & sector) and Auto Program

- Automatically erase any combination of sectors with Erase Suspend capability.

- Automatically program and verify data at specified address

• Erase suspend/Erase Resume

- Suspends an erase operation to read data from, or program data to, another sector that is not being erased, then resumes the erase.

• Status Reply

- Data polling & Toggle bit for detection of program and

erase cycle completion.

• Ready/Busy pin (RY/BY)

- Provides a hardware method of detecting program or erase cycle completion.

- Sector protect/unprotect for 5V only system or 5V/ 12V system.

• Sector protection

- Hardware method to disable any combination of sectors from program or erase operations

• 100,000 minimum erase/program cycles

• Latch-up protected to 100mA from -1V to VCC+1V

• Boot Code Sector Architecture

- T = Top Boot Sector

- B = Bottom Boot Sector

• Low VCC write inhibit is equal to or less than 3.2V

• Package type:

- 44-pin SOP

- 48-pin TSOP

• Compatibility with JEDEC standard

- Pinout and software compatible with single-power supply Flash

• 20 years data retention

GENERAL DESCRIPTION

The MX29F400T/B is a 4-mega bit Flash memory organized as 512K bytes of 8 bits or 256K words of 16 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory . The MX29F400T/B is packaged in 44-pin SOP, 48-pin TSOP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers.

The standard MX29F400T/B offers access time as fast as 55ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX29F400T/B has separate chip enable (CE) and output enable (OE) controls.

MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29F400T/B uses a command register to manage this functionality. The command register allows for 100%

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TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility.

MXIC Flash technology reliably stores memory contents even after 100,000 erase and prog ram cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cycling. The MX29F400T/B uses a 5.0V±10% VCC sup- ply to perform the High Reliability Erase and auto Program/Erase algorithms.

The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.

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MX29F400T/B

PIN CONFIGURATIONS

44 SOP(500 mil)

RESET

RY/BY

A17

GND

OE Q0 Q8 Q1 Q9 Q2

Q10

Q11

2 3 4

12 13 14 15 16 17 18 19 20 21 22

A10

A11

A12

A13

A14

A15

A16

BYTE

GND

Q15/A-1

MX29F400T/B

Q14

Q13

Q12

VCC

48 TSOP (Standard Type) (12mm x 20mm)

PIN DESCRIPTION

SYMBOL PIN NAME

A0~A17 Address Input Q0~Q14 Data Input/Output Q15/A-1 Q15(Word mode)/LSB addr(Byte mode) CE Chip Enable Input WE Write Enable Input BYTE Word/Byte Selction input RESET Hardware Reset Pin/Sector Protect Unlock OE Output Enable Input RY/BY Ready/Busy Output VCC Power Supply Pin (+5V) GND Ground Pin

A15 A14 A13 A12 A11 A10

RESET

RY/BY

A17

1 2 3 4 5 6 7

12 13

15 16

17 18

MX29F400T/B

A16

BYTE

GND

Q15/A-1

Q14

Q13

Q12

VCC

Q11

Q10

GND

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MX29F400T/B

SECTOR STRUCTURE

MX29F400T TOP BOOT SECTOR ADDRESS TABLE

Sector Size Address Range (in hexadecimal) (Kbytes/ (x8) (x16)

Sector A17 A16 A15 A14 A13 A12 Kwords) Address Range Address Range

SA0 0 0 0 X X X 64/32 00000h-0FFFFh 00000h-07FFFh SA1 0 0 1 X X X 64/32 10000h-1FFFFh 08000h-0FFFFh SA2 0 1 0 X X X 64/32 20000h-2FFFFh 10000h-17FFFh SA3 0 1 1 X X X 64/32 30000h-3FFFFh 18000h-1FFFFh SA4 1 0 0 X X X 64/32 40000h-4FFFFh 20000h-27FFFh SA5 1 0 1 X X X 64/32 50000h-5FFFFh 28000h-2FFFFh SA6 1 1 0 X X X 64/32 60000h-6FFFFh 30000h-37FFFh SA7 1 1 1 0 X X 32/16 70000h-77FFFh 38000h-3BFFFh SA81111008/4 78000h-79FFFh 3C000h-3CFFFh SA91111018/4 7A000h-7BFFFh 3D000h-3DFFFh SA10 1 1111X16/8 7C000h-7FFFFh 3E000h-3FFFFh

MX29F400B BOTTOM BOOT SECTOR ADDRESS TABLE

Sector Size Address Range (in hexadecimal) (Kbytes/ (x8) (x16)

Sector A17 A16 A15 A14 A13 A12 Kwords) Address Range Address Range

SA000000X16/8 00000h-03FFFh 00000h-01FFFh SA10000108/4 04000h-05FFFh 02000h-02FFFh SA20000118/4 06000h-07FFFh 03000h-03FFFh SA3 0 0 0 1 X X 32/16 08000h-0FFFFh 04000h-07FFFh SA4 0 0 1 X X X 64/32 10000h-1FFFFh 08000h-0FFFFh SA5 0 1 0 X X X 64/32 20000h-2FFFFh 10000h-17FFFh SA6 0 1 1 X X X 64/32 30000h-3FFFFh 18000h-1FFFFh SA7 1 0 0 X X X 64/32 40000h-4FFFFh 20000h-27FFFh SA8 1 0 1 X X X 64/32 50000h-5FFFFh 28000h-2FFFFh SA9 1 1 0 X X X 64/32 60000h-6FFFFh 30000h-37FFFh SA10 1 1 1 X X X 64/32 70000h-7FFFFh 38000h-3FFFFh

Note: Address range is A17~A-1 in byte mode and A17~A0 in word mode.

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BLOCK DIAGRAM

MX29F400T/B

CE OE

A0-A17

CONTROL INPUT

LOGIC

ADDRESS

LATCH

AND

BUFFER

PROGRAM/ERASE

HIGH VOLTA GE

X-DECODER

MX29F400T/B

FLASH ARRA Y

Y-DECODER

Y-PASS GATE

SENSE

AMPLIFIER

PGM

DATA

ARRAY

SOURCE

WRITE

STATE

MACHINE

(WSM)

STATE

COMMAND

DATA DECODER

COMMAND

DATA LATCH

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Q0-Q15/A-1

PROGRAM

DATA LATCH

I/O BUFFER

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MX29F400T/B

AUTOMATIC PROGRAMMING

The MX29F400T/B is byte programmable using the Automatic Programming algorithm. The Automatic Programming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. The typical chip programming time at room temperature of the MX29F400T/B is less than 4 seconds.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase pulses according to MXIC's Automatic Chip Erase algorithm. T ypical erasure at room temper ature is accomplished in less than 4 second. The A utomatic Erase algorithm automatically programs the entire array prior to electrical erase. The timing and v erification of electrical erase are controlled internally within the device.

AUTOMATIC SECTOR ERASE

The MX29F400T/B is sector(s) erasable using MXIC's Auto Sector Erase algorithm. Sector erase modes allow sectors of the array to be erased in one erase cycle. The Automatic Sector Erase algorithm automatically programs the specified sector(s) prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm requires the user to only write program set-up commands (including 2 unlock write cycle and A0H) and a program command (program data and address). The de vice automatically times the programming pulse width, provides the program verification, and counts the number of sequences. A status bit similar to DAT A polling and a status bit toggling between consecutive read cycles, provide feedback to the user as to the status of the programming operation.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to write commands to the command register using standard microprocessor write timings. The device will automatically pre-program and verify the entire arra y. Then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. A status bit toggling between consecutive read cycles provides feedback to the user as to the status of the programming operation.

Register contents serve as inputs to an internal statemachine which controls the erase and programming circuitry . During write cycles, the command register internally latches address and data needed for the programming and erase operations. During a system write cycle, addresses are latched on the falling edge, and data are latched on the rising edge of WE or CE, whichev er happens first .

MXIC's Flash technology combines years of EPROM experience to produce the highest lev els of quality , reliability , and cost eff ectiveness. The MX29F400T/B electrically erases all bits simultaneously using FowlerNordheim tunneling. The bytes are programmed b y using the EPROM programming mechanism of hot electron injection.

During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. During a Sector Erase cycle, the command register will only respond to Erase Suspend command. After Erase Suspend is completed, the device stays in read mode. After the state machine has completed its task, it will allow the command register to respond to its full command set.

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MX29F400T/B

T ABLE1. SOFTW ARE COMMAND DEFINITIONS

First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus

Command Bus Cycle Cycle Cycle Cycle Cycle Cycle

Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Reset 1 XXXH F0H Read 1 RA RD Read Silicon ID Word 4 555H AAH 2AAH 55H 555H 90H ADI DDI

Byte 4 AAAH AAH 555H 55H AAAH 90H ADI DDI Sector Protect Word 4 555H AAH 2AAH 55H 555H 90H (SA) XX00H Verify x02H XX01H

Byte 4 AAAH AAH 555H 55H AAAH 90H (SA) 00H

x04H 01H

Porgram Word 4 555H AAH 2AAH 55H 555H A0H PA PD

Byte 4 AAAH AAH 555H 55H AAAH A0H PA PD Chip Erase Word 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55 H 555H 10H

Byte 6 AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H AAAH 10H Sector Erase Word 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55 H SA 30H

Byte 6 AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H SA 3 0H Sector Erase Suspend 1 XXXH B0H Sector Erase Resume 1 XXXH 30H Unlock for sector 6 555H AAH 2AAH 55 H 555H 8 0H 555H AAH 2AAH 55H 555H 20H protect/unprotect

Note:

1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacture code,A1=0, A0 = 1 for device code, A2~A17=do not care. (Refer to table 3) DDI = Data of Device identifier : C2H for manufacture code, 23H/ABH (x8) and 2223H/22ABH (x16) for device code. X = X can be VIL or VIH RA=Address of memory location to be read. RD=Data to be read at location RA.

2.PA = Address of memory location to be programmed. PD = Data to be programmed at location PA. SA = Address to the sector to be erased.

3.The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode/AAAH or 555H to Address A10~A-1 in byte mode.

Address bit A11~A17=X=Don't care for all address commands except for Program Address (PA) and Sector Address (SA). Write Sequence may be initiated with A11~A17 in either state.

4. For Sector Protect Verify operation:If read out data is 01H, it means the sector has been protected. If read out data is 00 H, it means the sector is still not being protected.

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COMMAND DEFINITIONS

MX29F400T/B

Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode.

Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Either of the two reset command sequences will reset the device(when applicable).

Table 1 defines the valid register command sequences.

T ABLE 2. MX29F400T/B BUS OPERATION

Pins CE OE WE A0 A1 A6 A9 Q0 ~ Q1 5 Mode Read Silicon ID L L H L L X VID(2) C2H (Byte mode) Manfacturer Code(1) 00C2H (Word mode) Read Silicon ID L L H H L X VID(2) 23H/ABH (Byte mode) Device Code(1) 2223H/22ABH (Word mode) Read L L H A0 A1 A6 A9 D Standby H XXXXXX HIGH Z Output Disable L H H XXXX HIGH Z Write L H L A0 A1 A6 A9 DIN(3) Sector Protect with 12V L VID(2) L X X L VID(2) X system(6) Chip Unprotect with 12V L VID(2) L X X H VID(2) X system(6) Verify Sector Protect L L H X H X VID(2) Code(5) with 12V system Sector Protect without 12V L H L X X L H X system (6) Chip Unprotect without 12V L H L X X H H X system (6) Verify Sector Protect/Unprotect L L H X H X H Code(5) without 12V system (7) Reset X XXXXXX HIGH Z

OUT

NOTES:

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.

2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.

3. Refer to Table 1 for valid Data-In during a write operation.

4. X can be VIL or VIH.

5. Code=00H/XX00H means unprotected. Code=01H/XX01H means protected. A17~A12=Sector address for sector protect.

6. Refer to sector protect/unprotect algorithm and waveform. Must issue "unlock for sector protect/unprotect" command before "sector protect/unprotect without 12V system" command.

7. The "verify sector protect/unprotect without 12V sysytem" is only following "Sector protect/unprotect without 12V system" command.

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MX29F400T/B

READ/RESET COMMAND

The read or reset operation is initiated by writing the read/reset command sequence into the command register. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the command register contents are altered.

If program-fail or erase-fail happen, the write of F0H will reset the device to abort the operation. A valid command must then be written to place the device in the desired state.

SILICON-ID-READ COMMAND

Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacturer and device codes must be accessible while the device resides in the target system. PROM programmers typically access signature codes by raising A9 to a high voltage. Howe ver , multiplexing high v oltage onto address lines is not generally desired system design practice.

The MX29F400T/B contains a Silicon-ID-Read operation to supplement traditional PROM programming methodology. The operation is initiated by writing the read silicon ID command sequence into the command register. Following the command write, a read cycle with A1=VIL,A0=VIL retrieves the manufacturer code of C2H/ 00C2H. A read cycle with A1=VIL, A0=VIH returns the device code of 23H/2223H for MX29F400T, ABH/22ABH for MX29F400B.

SET-UP AUTOMATIC CHIP/SECTOR ERASE COMMANDS

Chip erase is a six-bus cycle operation. There are tw o "unlock" write cycles. These are followed b y writing the "set-up" command 80H. Two more "unlock" write cycles are then followed by the chip erase command 10H.

The Automatic Chip Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Chip Erase. Upon executing the Automatic Chip Erase, the device will automatically program and verify the entire memory for an all-zero data pattern. When the device is automatically verified to contain an all-zero pattern, a self-timed chip erase and verify begin. The erase and verify operations are completed when the data on Q7 is "1" at which time the device returns to the Read mode. The system is not required to pro vide any control or timing during these operations.

When using the Automatic Chip Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array(no erase verification command is required).

If the Erase operation was unsuccessful, the data on Q5 is "1"(see Table 4), indicating the erase operation exceed internal timing limit.

The automatic erase begins on the rising edge of the last WE or CE, whichever happens later, pulse in the command sequence and terminates when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mode.

T ABLE 3. EXP ANDED SILICON ID CODE

Pins A0 A1 Q15~Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code(Hex) Manufacture code Word VIL VIL 0 0H 1 1 0 0 0 0 1 0 00C2H

Byte VIL VIL X 1 1 0 0 0 0 1 0 C2H Device code Word VIH VIL 22H 0 0 1 0 0 0 1 1 2223H for MX29F400T Byte VIH VIL X 0 0 1 0 0 0 1 1 2 3 H Device code Word VIH VIL 22H 1 0 1 0 1 0 1 1 22ABH for MX29F400B Byte VIH VIL X 1 0 1 0 1 0 1 1 A BH Sector Protection X VIH X 0 0 0 0 0 0 0 1 01H (Protected) Verification X VIH X 0 0 0 0 0 0 0 0 00H (Unprotected)

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SECTOR ERASE COMMANDS

MX29F400T/B

The Automatic Sector Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Set-up Sector Erase command and Automatic Sector Erase command. Upon executing the Automatic Sector Erase command, the device will automatically program and verify the sector(s) memory for an all-zero data pattern. The system is not required to provide any control or timing during these operations.

When the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verify begin. The erase and verify operations are complete when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations.

When using the Automatic Sector Erase algorithm, note that the erase automatically terminates when adequate

T able 4. Write Operation Status

Status Q7 Q6 Q 5 Q3 Q2 RY/BY

erase margin has been achieved for the memory array (no erase verification command is required). Sector erase is a six-bus cycle operation. There are two "unlock" write cycles. These are f ollowed by writing the setup command 80H. Two more "unlock" write cycles are then followed by the sector erase command 30H. The sector address is latched on the falling edge of WEor CE, whichever happens later , while the command(data) is latched on the rising edge of WE or CE, whichever happens first. Sector addresses selected are loaded into internal register on the sixth falling edge of WE or CE, whichever happens later. Each successive sector load cycle started by the falling edge of WE or CE, whichever happens later, must begin within 30us from the rising edge of the preceding WE or CE, whichev er happens First, otherwise, the loading period ends and internal auto sector erase cycle starts. (Monitor Q3 to determine if the sector erase timer window is still open, see section Q3, Sector Erase Timer.) Any command other than Sector Erase(30H) or Erase Suspend(B0H) during the time-out period resets the device to read mode.

Note1 Note2

Byte Program in Auto Program Algorithm Q7 Toggle 0 N/A No 0

Auto Erase Algorithm 0 Toggle 0 1 Toggle 0

Erase Suspend Read 1 No 0 N/A Toggle 1 (Erase Suspended Sector) Toggle

In Progress

Erase Suspended Mode Erase Suspend Read Data Data Data Data Data 1

(Non-Erase Suspended Sector) Erase Suspend Program Q7 Toggle 0 N/A N/A 0

Byte Program in Auto Program Algorithm Q7 Toggle 1 N/A No 0

Exceeded Time Limits Auto Erase Algorithm 0 Toggle 1 1 Toggle 0

Erase Suspend Program Q7 Toggle 1 N/A N/A 0

Toggle

Note:

1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits. See "Q5:Exceeded Timing Limits " for more information.

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MX29F400T/B

ERASE SUSPEND

This command only has meaning while the state machine is executing Automatic Sector Erase operation, and therefore will only be responded during Automatic Sector Erase operation. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 100us to suspend the erase operations. However , When the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After this command has been executed, the command register will initiate erase suspend mode. The state machine will return to read mode automatically after suspend is ready . At this time, state machine only allows the command register to respond to the Read Memory Array, Erase Resume and program commands.

The system can determine the status of the program operation using the Q7 or Q6 status bits, just as in the standard program operation. After an erase-suspend program operation is complete, the system can once again read array data within non-suspended sectors.

ERASE RESUME

This command will cause the command register to clear the suspend state and return back to Sector Erase mode but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in all other conditions.Another Erase Suspend command can be written after the chip has resumed erasing.

SET-UP AUTOMATIC PROGRAM

tem is not required to provide further controls or timings. The device will automatically provide an adequate internally generated program pulse and verify margin.

If the program opetation was unsuccessful, the data on Q5 is "1"(see Table 4), indicating the program operation exceed internal timing limit. The automatic programming operation is completed when the data read on Q6 stops toggling for two consecutive read cycles and the data on Q7 and Q6 are equivalent to data written to these two bits, at which time the device returns to the Read mode(no program verify command is required).

DATA POLLING-Q7

The MX29F400T/B also features Data Polling as a method to indicate to the host system that the Automatic Program or Erase algorithms are either in progress or completed.

While the Automatic Programming algorithm is in operation, an attempt to read the device will produce the complement data of the data last written to Q7. Upon completion of the Automatic Program Algorithm an attempt to read the device will produce the true data last written to Q7. The Data P olling f eature is valid after the rising edge of the fourth WEor CE, whichever happens first, pulse of the four write pulse sequences for automatic program.

While the Automatic Erase algorithm is in operation, Q7 will read "0" until the erase operation is competed. Upon completion of the erase operation, the data on Q7 will read "1". The Data P olling feature is valid after the rising edge of the sixth WE or CE, whichever happens first pulse of six write pulse sequences for automatic chip/ sector erase.

COMMANDS

T o initiate Automatic Progr am mode, A three-cycle command sequence is required. There are two "unlock" write cycles. These are f ollowed by writing the Automatic Program command A0H.

Once the Automatic Program command is initiated, the next WEor CE, pulse causes a transition to an active programming operation. Addresses are latched on the falling edge, and data are internally latched on the rising edge of the WE or CE, whichever happens first, pulse. The rising edge of WE or CE, whiche ver happens first, also begins the programming operation. The sys-

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The Data Polling f eature is active during Automatic Program/Erase algorithm or sector erase time-out.(see section Q3 Sector Erase Timer)

RY/BY :Read y/Busy

The RY/BY is a dedicated, open-drain output pin that indicates whether an Automatic Erase/Program algorithm is in progress or complete. The RY/BY status is valid after the rising edge of the final WE or CE, whichever happens first, pulse in the command sequence. Since RY/BY is an open-dr ain output, several R Y/BY pins can be tied together in parallel with a pull-up resistor to Vcc.

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MX29F400T/B

If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.)If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode.

Table 4 sho ws the outputs f or R Y/BY.

Q6:Toggle BIT I

Toggle Bit I on Q6 indicates whether an A utomatic Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE or CE, whichever happens first, pulse in the command sequence(prior to the program or erase operation), and during the sector time-out.

During an Automatic Program or Erase algorithm operation, successive read cycles to any address cause Q6 to toggle. The system may use either OE or CE to control the read cycles. When the operation is complete , Q6 stops toggling.

After an erase command sequence is written, if all sectors selected for erasing are protected, Q6 toggles and returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.

The system can use Q6 and Q2 together to determine whether a sector is actively erasing or is erase suspended. When the de vice is actively erasing (that is, the Automatic Erase algorithm is in progress), Q6 toggling. When the device enters the Erase Suspend mode, Q6 stops toggling. Ho wever , the system m ust also use Q2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use Q7.

If a program address falls within a protected sector, Q6 toggles for approximately 2 us after the program command sequence is written, then returns to reading array data.

Q6 also toggles during the erase-suspend-program mode, and stops toggling once the Automatic Program algorithm is complete.

Table 4 sho ws the outputs for Toggle Bit I on Q6.

Q2:Toggle Bit II

The "T oggle Bit II" on Q2, when used with Q6, indicates whether a particular sector is actively eraseing (that is, the Automatic Erase alorithm is in process), or whether that sector is erase-suspended. Toggle Bit I is valid after the rising edge of the final WE or CE, whichev er happens first, pulse in the command sequence.

Q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE or CE to control the read cycles.) But Q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. Q6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus , both status bits are required for sectors and mode information. Refer to Table 4 to compare outputs f or Q2 and Q6.

Reading Toggle Bits Q6/ Q2

Whenever the system initially begins reading toggle bit status, it must read Q7-Q0 at least twice in a row to determine whether a toggle bit is toggling. T ypically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on Q7-Q0 on the following read cycle.

Howe v e r, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of Q5 is high (see the section on Q5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as Q5 went high. If the toggle bit is no longer toggling, the device has successfuly completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data.

The remaining scenario is that system initially determines that the toggle bit is toggling and Q5 has not gone high. The system may continue to monitor the toggle bit and Q5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation.

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MX29F400T/B

Q5 Exceeded Timing Limits

Q5 will indicate if the program or erase time has exceeded the specified limits(internal pulse count). Under these conditions Q5 will produce a "1". This time-out condition indicates that the program or erase cycle was not successfully completed. Data Polling and Toggle Bit are the only operating functions of the device under this condition.

If this time-out condition occurs during sector erase operation, it specifies that a particular sector is bad and it may not be reused. Howe ver , other sectors are still functional and may be used for the program or erase operation. The device must be reset to use other sectors. Write the Reset command sequence to the device, and then execute prog ram or erase command sequence. This allows the system to continue to use the other active sectors in the device.

If this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination of sectors are bad.

If this time-out condition occurs during the byte programming operation, it specifies that the entire sector containing that byte is bad and this sector maynot be reused, (other sectors are still functional and can be reused).

The time-out condition may also appear if a user tries to program a non blank location without erasing. In this case the device locks out and never completes the Automatic Algorithm operation. Hence, the system never reads a valid data on Q7 bit and Q6 never stops toggling. Once the Device has exceeded timing limits, the Q5 bit will indicate a "1". Please note that this is not a device failure condition since the device was incorrectly used.

DATA PROTECTION

resulting from VCC pow er-up and power-down transition or system noise.

TEMPORARY SECT OR UNPROTECT

This feature allows temporary unprotection of previously protected sector to change data in-system. The T emporary Sector Unprotect mode is activated by setting the RESET pin to VID(11.5V-12.5V). During this mode, formerly protected sectors can be programmed or erased as un-protected sector. Once VID is remove from the RESET pin,all the previously protected sectors are protected again.

Q3 Sector Erase Timer

After the completion of the initial sector erase command sequence, the sector erase time-out will begin. Q3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase command sequence.

If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, Q3 may be used to determine if the sector erase timer window is still open. If Q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit. If Q3 is low ("0"), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of Q3 prior to and following each subsequent sector erase command. If Q3 were high on the second status check, the command may not have been accepted.

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns(typical) on CE or WE will not initiate a write cycle.

The MX29F400T/B is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates sever al features to prev ent inadvertent write cycles

P/N:PM0439

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. T o initiate a write cycle CE and WE must be a logical zero while OE is a logical one.

POWER SUPPLY DECOUPLING

In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected between its VCC and GND .

REV. 1.6, NOV. 12, 2001

Page 13

Temporary Sector Unprotect Operation

RESET = VID (Note 1)

Perform Erase or Program Operation

Temporary Sector Unprotect Completed(Note 2)

MX29F400T/B

Start

Operation Completed

RESET = VIH

Note :

1. All protected sectors are temporary unprotected. VID=11.5V~12.5V

2. All previously protected sectors are protected again.

P/N:PM0439

REV. 1.6, NOV. 12, 2001

Page 14

MX29F400T/B

TEMPORARY SECTOR UNPROTECT

Parameter Std. Description T est Setup AllSpeed Options Unit tVIDR VID Rise and Fall Time (See Note) Min 50 0 ns tRSP RESET Setup Time for Temporary Sector Unprotect Min 4 us

Note: Not 100% tested

Temporary Sector Unprotect Timing Diagram

12V

RESET

RY/BY

0 or 5V

tVIDR

tRSP

Program or Erase Command Sequence

0 or 5V

tVIDR

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REV. 1.6, NOV. 12, 2001

Page 15

MX29F400T/B

AC CHARACTERISTICS

Parameter Std Description T est Setup All Speed Options Unit tREAD Y1 RESET PIN Low (During Automatic Algorithms) MAX 20 us

to Read or Write (See Note)

tREAD Y2 RESET PIN Low (NOT During Automatic MAX 50 0 ns

Algorithms) to Read or Write (See Note) tRP1 RESET Pulse Width (During Automatic Algorithms) MIN 1 0 us tRP2 RESET Pulse Width (NO T During Automatic Algorithms) MIN 5 0 0 ns tR H RESET High Time Before Read(See Note) MIN 0 ns tRB1 RY/BY Recov ery Time(to CE, OE go low) MIN 0 ns tRB2 RY/BY Recovery Time(to WE go low) MIN 50 ns

Note:Not 100% tested

RESET TIMING WAVEFORM

RY/BY

CE, OE

RESET

RY/BY

CE, OE

tRH

tRP2

tReady2

Reset Timing NOT during Automatic Algorithms

tReady1

tRB1

tRB2

RESET

P/N:PM0439

tRP1

Reset Timing during Automatic Algorithms

REV. 1.6, NOV. 12, 2001

Page 16

MX29F400T/B

SECTOR PROTECTION WITH 12V SYSTEM

The MX29F400T/B features hardware sector protection. This feature will disable both program and erase operations for these sectors protected. T o activ ate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest VID = 12V) A6 = VIL and CE = VIL.(see Table 2) Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated on the rising edge. Please refer to sector protect algorithm and waveform.

T o v erify programming of the protection circuitry , the programming equipment must force VID on address pin A9 ( with CE and OE at VIL and WE at VIH). When A1=1, it will produce a logical "1" code at device output Q0 for a protected sector. Otherwise the device will produce 00H for the unprotected sector. In this mode, the addresses,except for A1, are don't care. Address locations with A1 = VIL are reserved to read manufacturer and device codes.(Read Silicon ID)

It is also possible to determine if the sector is protected in the system by writing a Read Silicon ID command. Perf orming a read operation with A1=VIH, it will produce a logical "1" at Q0 for the protected sector .

POWER-UP SEQUENCE

The MX29F400T/B powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of the predefined command sequences.

SECTOR PROTECTION WITHOUT 12V SYSTEM

The MX29F400T/B also feature a hardware sector protection method in a system without 12V power suppply. The programming equipment do not need to supply 12 volts to protect sectors. The details are shown in sector protect algorithm and waveform.

CHIP UNPROTECT WITHOUT 12V SYSTEM

The MX29F400T/B also feature a hardware chip unprotection method in a system without 12V power supply. The programming equipment do not need to supply 12 volts to unprotect all sectors. The details are shown in chip unprotect algorithm and waveform.

ABSOLUTE MAXIMUM RATINGS

CHIP UNPROTECT WITH 12V SYSTEM

The MX29F400T/B also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code. It is recommended to protect all sectors before activating chip unprotect mode.

To activate this mode, the programming equipment must force VID on control pin OE and address pin A9. The CE pins must be set at VIL. Pins A6 must be set to VIH.(see Table 2) Refer to chip unprotect algorithm and waveform for the chip unprotect algorithm. The unprotection mechanism begins on the falling edge of the WE pulse and is terminated on the rising edge.

It is also possible to determine if the chip is unprotected in the system by writing the Read Silicon ID command. Performing a read operation with A1=VIH, it will produce 00H at data outputs(Q0-Q7) for an unprotected sector. It is noted that all sectors are unprotected after the chip unprotect algorithm is completed.

RATING VALUE

Ambient Operating Temperature -40oC to 125oC Ambient Temperature with Power -55oC to 125oC Applied Storage T emperature -65oC to 125oC Applied Input Voltage -0.5V to 7.0V Applied Output Voltage -0.5V to 7.0V VCC to Ground Potential -0.5V to 7.0V A9 & OE -0.5V to 13.5V

NOTICE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability.

NOTICE: Specifications contained within the following tables are subject to change.

P/N:PM0439

REV. 1.6, NOV. 12, 2001

Page 17

MX29F400T/B

CAPACITANCE TA = 25oC, f = 1.0 MHz

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS

CIN1 Input Capacitance 8 pF VIN = 0V CIN2 Control Pin Capacitance 12 pF VIN = 0V COUT Output Capacitance 12 pF VOUT = 0V

READ OPERATION DC CHARACTERISTICS TA = 0oC to 70oC, -40oC to 125oC, VCC = 5V

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS

ILI Input Leakage Current 1 uA VIN = GND to VCC ILO Output Leakage Current 10 uA VOUT = GND to VCC ISB1 Standby VCC current 1 mA CE = VIH ISB2 1(Note3) 5(Note3) uA CE = VCC ± 0.3V ICC1 Operating VCC current 40 mA IOUT = 0mA, f=5MHz ICC2 50 mA IOUT= 0mA, f=10MHz VIL Input Low Voltage -0.3(NOTE 1) 0.8 V VIH Input High Voltage(NOTE 2) 2.0 VCC + 0.3 V VOL Output Low Voltage 0.45 V IOL = 2.1mA VOH1 Output High Voltage(TTL) 2.4 V IOH = -2mA VOH2 Output High Voltage(CMOS) VCC-0.4 V IOH = -100uA,VCC=VCC MIN

NOTES:

1.VIL min. = -1.0V for pulse width is equal to or less than 50 ns. VIL min. = -2.0V for pulse width is equal to or less than 20 ns.

2.VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns If VIH is over the specified maximum value, read operation cannot be guaranteed.

3.ISB2 20uA max. for Automotive grade.

±±

±10%

±±

P/N:PM0439

REV. 1.6, NOV. 12, 2001

Page 18

MX29F400T/B

AC CHARACTERISTICS TA = 0oC to 70oC, -40oC to 125oC, VCC = 5V

29F400T/B-55 (Note2) 29F400T/B-70

SYMBOL PARAMETER MIN. MAX. MIN. MAX. UNIT Conditions

tACC Address to Output Delay 55 7 0 ns CE=OE=VIL tCE CE to Output Delay 5 5 7 0 ns OE=VIL tOE OE to Output Delay 15 4 0 ns CE=VIL tDF OE High to Output Float (Note1) 0 20 0 30 ns CE=VIL tOH Address to Output hold 0 0 ns CE=OE=VIL

29F400T/B-90 (Note3) 29F400T/B-12(Note3)

SYMBOL PARAMETER MIN. MAX. MIN. MAX. UNIT Conditions

tACC Address to Output Delay 90 12 0 ns CE=OE=VIL tCE CE to Output Delay 9 0 1 2 0 ns OE=VIL tOE OE to Output Delay 40 50 ns CE=VIL tDF OE High to Output Float (Note1) 0 30 0 3 0 ns CE=VIL tOH Address to Output hold 0 0 ns CE=OE=VIL

TEST CONDITIONS:

• Input pulse levels: 0.45V/2.4V

• Input rise and fall times is equal to or less than 10ns

• Output load: 1 TTL gate + 100pF (Including scope and jig)

• Reference levels for measuring timing: 0.8V, 2.0V

NOTE:

1. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven.

2.VCC=5V±10%,CL=50pF,VIH/VIL=3.0V/0V,

V OH/V OL=1.5V/1.5V, IOL=2mA,IOH=-2mA.

3. Automotive grade is only provided for MX29F400T/B90 & MX29F400T/B-12

± ±

± 10%

± ±

P/N:PM0439

REV. 1.6, NOV. 12, 2001

Page 19

READ TIMING WAVEFORMS

MX29F400T/B

Addresses

Outputs

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

HIGH Z HIGH Z

VOH

VOL

tACC

ADD Valid

tCE

tOE

tDF

tOH

DATA Valid

COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION DC CHARACTERISTICS TA = 0oC to 70oC, -40oC to 125oC, VCC = 5V

±±

± 10%

±±

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS

ICC1 (Read) Operating VCC Current 40 mA IOUT=0mA, f=5MHz ICC2 50 mA IOUT=0mA, F=10MHz ICC3 (Program) 50 mA In Programming ICC4 (Erase) 50 mA In Erase ICCES VCC Erase Suspend Current 2 mA CE=VIH, Erase Suspended

NOTES:

1. VIL min. = -0.6V for pulse width is equal to or less than 20ns.

2. If VIH is ov er the specified maximum value, prog ramming operation cannot be guranteed.

3. ICCES is specified with the device de-selected. If the device is read during erase suspend mode, current draw is the sum of ICCES and ICC1 or ICC2.

4. All current are in RMS unless otherwise noted.

P/N:PM0439

REV. 1.6, NOV. 12, 2001

Page 20

MX29F400T/B

AC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V

29F400T/B-55(Note2) 29F400T/B-70

Symbol PARAMETER MIN. MAX. MIN. MAX. Unit

tOES OE setup time 50 5 0 ns tCWC Command programming cycle 7 0 7 0 ns tCEP WE programming pulse width 45 45 ns tCEPH1 WE programming pluse width High 2 0 2 0 ns tCEPH2 WE programming pluse width High 2 0 20 ns tAS Address setup time 0 0 ns tAH Address hold time 45 45 ns tDS Data setup time 30 3 0 ns tD H Data hold time 0 0 ns tCESC CE setup time before command write 0 0 ns tDF Output disable time (Note 1) 20 30 ns tAETC Total erase time in auto chip erase 4(TYP.) 3 2 4(TYP.) 32 s tAETB Total erase time in auto sector erase 1.3(TYP.) 10.4 1.3(TYP.) 10.4 s tAVT Total programming time in auto verify 7/12(TYP.) 210/360 7/12(TYP.) 210/360 us

(byte/ word program time) tBAL Sector address load time 1 0 0 1 0 0 u s tC H CE Hold Time 0 0 ns tCS CE setup to WE going low 0 0 ns tVLHT Voltge Transition Time 4 4 us tOESP OE Setup Time to WE Active 4 4 us tWPP1 Write pulse width for sector protect 10 10 us tWPP2 Write pulse width for sector unprotect 1 2 1 2 ms

±±

± 10%

±±

NOTES:

1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.

2. Under condition of VCC=5V± 10%, CL=50pF,VIH/VIL=3.0V/0V,VOH/VOL=1.5V/1.5V,IOL=2mA,IOH=-2mA.

P/N:PM0439

REV. 1.6, NOV. 12, 2001

Page 21

MX29F400T/B

AC CHARACTERISTICS TA = 0oC to 70oC, -40oC to 125oC, VCC = 5V

29F400T/B-90 29F400T/B-120

Symbol PARAMETER MIN. MAX. MIN. MAX. Unit

tOES OE setup time 5 0 50 ns tCWC Command programming cycle 9 0 120 ns tCEP WE programming pulse width 45 45 ns tCEPH1 WE programming pluse width High 20 20 ns tCEPH2 WE programming pluse width High 20 20 ns tAS Address setup time 0 0 ns tAH Address hold time 4 5 50 ns tDS Data setup time 45 5 0 ns tD H Data hold time 0 0 ns tCESC CE setup time before command write 0 0 ns tDF Output disable time (Note 1) 3 0 3 0 ns tAETC Total erase time in auto chip erase 4(TYP.) 3 2 4(TYP.) 32 s tAETB Total erase time in auto sector erase 1.3(TYP.) 10.4 1.3(TYP.) 10.4 s tAVT Total programming time in auto verify 7/12(TYP.) 210/360 7/12(TYP.) 210/360 us

(byte/ word program time) tBAL Sector address load time 10 0 100 us tC H CE Hold Time 0 0 ns tCS CE setup to WE going low 0 0 ns tVLHT Voltge Transition Time 4 4 us tOESP OE Setup Time to WE Active 4 4 us tWPP1 Write pulse width for sector protect 1 0 10 us tWPP2 Write pulse width for sector unprotect 12 12 ms

±±

± 10%

±±

NOTES:

1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.

2. Under condition of VCC=5V± 10%, CL=50pF,VIH/VIL=3.0V/0V,VOH/VOL=1.5V/1.5V,IOL=2mA,IOH=-2mA.

P/N:PM0439

REV. 1.6, NOV. 12, 2001

Page 22

SWITCHING TEST CIRCUITS

MX29F400T/B

DEVICE UNDER

TEST

SWITCHING TEST WAVEFORMS

2.4V

0.45V

AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0". Input pulse rise and fall time are < 20ns.(5ns for MX29F400T/B-55) Note:VIH/VIL=3.0V/0V, VOH/VOL=1.5V/1.5V, for MX29F400T/B-55.

CL=100pF Including jig capacitance, CL=50pF for MX29F400T/B-55

1.2K ohm

2.0V 2.0V

TEST POINTS

0.8V

INPUT

1.6K ohm

DIODES=IN3064

OR EQUIVALENT

0.8V OUTPUT

+5V

COMMAND WRITE TIMING WAVEFORM

VCC

Addresses

Data

P/N:PM0439

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

ADD Valid

tAS

tOES

tCS tCH

tCEP

tDS

tAH

tCEPH1

tCWC

tDH

DIN

REV. 1.6, NOV. 12, 2001

Page 23

AUTOMATIC PROGRAMMING TIMING WAVEFORM

MX29F400T/B

One byte data is programmed. Verify in fast algorithm and additional programming by external control are not required because these operations are executed automatically by internal control circuit. Programming

bit checking after automatic verification starts. Device outputs DAT A during programming and D AT A after programming on Q7.(Q6 is for toggle bit; see toggle bit, DAT A polling, timing wav eform)

completion can be verified by DATA polling and toggle

AUTOMATIC PROGRAMMING TIMING WAVEFORM (WORD MODE)

Vcc 5V

A11~A17

A0~A10

tAS

555H

tAH

tCEP

tDS tDH

2AAH

tCWC

tCEPH1

555H

ADD Valid

tAVT

tCESC

tDF

Q0,Q1,Q2

Q4(Note 1)

Command In

Command In Command InCommand In Data In

Command #AAH

(Q0~Q7)

Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit

Command #55H

Command InCommand In Data In

Command #A0H

DATA

DATA polling

DATADATA

tOE

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REV. 1.6, NOV. 12, 2001

Page 24

MX29F400T/B

AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART (WORD MODE)

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data A0H Address 555H

Write Program Data/Address

Invalid Command

Toggle Bit Checking Q6 not Toggled

Verify Word Ok

Auto Program Completed

YES

Q5 = 1

YES

Reset

Auto Program Exceed Timing Limit

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REV. 1.6, NOV. 12, 2001

Page 25

AUTOMATIC CHIP ERASE TIMING WAVEFORM

MX29F400T/B

All data in chip are erased. External erase verification is not required because data is erased automatically by internal control circuit. Erasure completion can be veri-

matic erase starts. Device outputs 0 during erasure and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle bit, DAT A polling, timing wav eform)

fied by DAT A polling and toggle bit chec king after auto-

AUTOMATIC CHIP ERASE TIMING WAVEFORM (WORD MODE)

Vcc 5V

A11~A17

A0~A10

555H

tAS

2AAH

tAH

555H

555H 2AAH

tCWC

tCEPH1

555H

tAETC

Q0,Q1,

Q4(Note 1)

tCEP

tDS tDH

Command In

Command In Command InCommand In

Command #AAH Command #55H

Command InCommand In

Command #80H

Command In

Command #AAH

(Q0~Q7)

Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

Command In

Command #55H

Command In

DATA polling

Command In

Command #10H

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REV. 1.6, NOV. 12, 2001

Page 26

MX29F400T/B

AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART (WORD MODE)

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 10H Address 555H

Invalid Command

Toggle Bit Checking

Q6 not Toggled

DATA Polling

Q7 = 1

Auto Chip Erase Completed

YES

Q5 = 1

YES

Reset

Auto Chip Erase Exceed Timing Limit

P/N:PM0439

REV. 1.6, NOV. 12, 2001

Page 27

AUTOMATIC SECTOR ERASE TIMING WAVEFORM

MX29F400T/B

Sector data indicated by A12 to A17 are erased. External erase verify is not required because data are erased automatically by internal control circuit. Erasure comple-

ing after automatic erase starts. De vice outputs 0 during erasure and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle bit, D AT A polling, timing wav eform)

tion can be verified by DAT A polling and toggle bit check-

AUTOMATIC SECTOR ERASE TIMING WAVEFORM (WORD MODE)

Vcc 5V

A12~A17

A0~A10

555H 2AAH 2AAH

tAS

tAH

555H 555H

Sector

Address0

tCWC

tCEPH1

Sector

Address1

Sector

Addressn

tBAL

tAETB

Q4(Note 1)

P/N:PM0439

Q0,Q1,

tCEP

tDS

tDH

Command InCommand

Command

(Q0~Q7)

Command InCommand

Command InCommand InCommand InCommand

Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

Command

Command #30HCommand #30HCommand #30HCommand #55HCommand #AAHCommand #80HCommand #55HCommand #AAH

REV. 1.6, NOV. 12, 2001

DATA polling

Page 28

MX29F400T/B

AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART (WORD MODE)

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 30H Sector Address

Toggle Bit Checking

Q6 T oggled ?

YES

Load Other Sector Addrss If Necessary (Load Other Sector Address)

Last Sector to Erase

Time-out Bit

Checking Q3=1 ?

YES

Toggle Bit Checking

Q6 not Toggled

YES

DATA Polling

Q7 = 1

YES

Invalid Command

Q5 = 1

YES

P/N:PM0439

Auto Sector Erase Completed

Reset

Auto Sector Erase Exceed Timing Limit

REV. 1.6, NOV. 12, 2001

Page 29

ERASE SUSPEND/ERASE RESUME FLOWCHART

START

Write Data B0H

MX29F400T/B

Toggle Bit checking Q6

not toggled

YES

Read Array or

Program

Reading or

Programming End

YES

Write Data 30H

Continue Erase

Another

Erase Suspend ?

YES

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REV. 1.6, NOV. 12, 2001

Page 30

MX29F400T/B

TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITH 12V

12V

tVLHT

Verify

tVLHT

tWPP 1

tOESP

Data

A17-A12 Sector Address

01H F0H

tOE

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REV. 1.6, NOV. 12, 2001

Page 31

MX29F400T/B

TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITH 12V

12V

tVLHT

12V

Data

tVLHT

tOESP

tWPP 2

tVLHT

tOE

Verify

00H

F0H

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REV. 1.6, NOV. 12, 2001

Page 32

SECTOR PROTECTION ALGORITHM FOR SYSTEM WITH 12V

START

Set Up Sector Addr

(A17,A16,A15,A14,A13,A12)

PLSCNT=1

OE=VID,A9=VID,CE=VIL

A6=VIL

Activate WE Pulse

Time Out 10us

MX29F400T/B

PLSCNT=32?

Yes

Device Failed

Set WE=VIH, CE=OE=VIL A9 should remain VID

Read from Sector

Addr=SA, A1=1

Data=01H?

Yes

Protect Another

Sector?

Remove VID from A9

Write Reset Command

Sector Protection

Complete

Yes

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REV. 1.6, NOV. 12, 2001

Page 33

CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITH 12V

START

Protect All Sectors

PLSCNT=1

Set OE=A9=VID CE=VIL,A6=1

Activate WE Pulse

MX29F400T/B

Increment

Sector Addr

Set Up First Sector Addr

Read Data from Device

Remove VID from A9

Write Reset Command

Time Out 12ms

Set OE=CE=VIL

A9=VID,A1=1

Data=00H?

Yes

All sectors have

been verified?

Yes

Chip Unprotect

Complete

Increment

PLSCNT

PLSCNT=1000?

Yes

Device Failed

P/N:PM0439

* It is recommended before unprotect whole chip, all sectors should be protected in advance.

REV. 1.6, NOV. 12, 2001

Page 34

MX29F400T/B

TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITHOUT 12V

Toggle bit polling

tCEP

* See the following Note!

Data

Don't care

(Note 2)

A18-A16 Sector Address

Note1: Must issue "unlock for sector protect/unprotect" command before sector protection for a system without 12V provided.

Note2: Except F0H

tOE

Verify

01H

F0H

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REV. 1.6, NOV. 12, 2001

Page 35

MX29F400T/B

TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITHOUT 12V

Data

Toggle bit polling

tCEP

* See the following Note!

Don't care

(Note 2)

Verify

00H

tOE

Note1: Must issue "unlock for sector protect/unprotect" command before sector unprotection for a system without 12V provided.

Note2: Except F0H

F0H

P/N:PM0439

REV. 1.6, NOV. 12, 2001

Page 36

SECTOR PROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V

ST ART

PLSCNT=1

MX29F400T/B

Increment PLSCNT

PLSCNT=32?

Write "unlock for sector protect/unprotect"

Command(Table1)

Set Up Sector Addr

(A17,A16,A15,A14,A13,A12)

OE=VIH,A9=VIH

CE=VIL,A6=VIL

Activate WE Pulse to start

Data don't care

Toggle bit checking

Q6 not Toggled

Yes

Set CE=OE=VIL

A9=VIH

Read from Sector

Addr=SA, A1=1

Data=01H?

P/N:PM0439

Yes

Device Failed

Protect Another

Write Reset Command

Sector Protection

Yes

Sector?

Complete

REV. 1.6, NOV. 12, 2001

Page 37

MX29F400T/B

CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V

START

Protect All Sectors

PLSCNT=1

Increment

Sector Addr

Write "unlock for sector protect/unprotect"

Command (Table 1)

Set OE=A9=VIH CE=VIL,A6=1

Activate WE Pulse to start

Data don't care

Toggle bit checking

Q6 not Toggled

Set OE=CE=VIL

A9=VIH,A1=1

Set Up First Sector Addr

Read Data from Device

Data=00H?

Yes

Increment

PLSCNT

PLSCNT=1000?

Yes

P/N:PM0439

* It is recommended before unprotect whole chip, all sectors should be protected in advance.

All sectors have

been verified?

Yes

Write Reset Command

Chip Unprotect

Complete

Device Failed

REV. 1.6, NOV. 12, 2001

Page 38

ID CODE READ TIMING WAVEFORM

MX29F400T/B

VCC

ADD

A1-A8

A10-A17

DATA

Q0-Q15

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VID VIH

VIL

tACC

tCE

tOE

DATA OUT

C2H/00C2H

tOH

tACC

tDF

tOH

DATA OUT

23H/ABH (Byte) 2223H/22ABH (Word)

P/N:PM0439

REV. 1.6, NOV. 12, 2001

Page 39

MX29F400T/B

ERASE AND PROGRAMMING PERFORMANCE(1)

LIMITS

PARAMETER MIN. TYP.(2) MAX.(3) UNITS

Sector Erase Time 1.3 10.4 sec Chip Erase Time 4 32 sec Byte Programming Time 7 21 0 us Word Programming Time 12 3 60 us Chip Programming Time 4 12 sec Erase/Program Cycles 100,000 Cycles

Note: 1.Not 100% Tested, Excludes external system level over head.

2.Typical values measured at 25°C,5V.

3.Maximum values measured at 25°C,4.5V.

LATCHUP CHARACTERISTICS

MIN. MAX.

Input Voltage with respect to GND on all pins except I/O pins -1.0V 13.5V Input Voltage with respect to GND on all I/O pins -1.0V Vcc + 1.0V Current -100mA +100mA Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.

DATA RETENTION

PARAMETER MIN. UNIT

Data Retention Time 20 Years

P/N:PM0439

REV. 1.6, NOV. 12, 2001

Page 40

MX29F400T/B

ORDERING INFORMATION

PLASTIC P A CKAGE (Top Boot Sector as an sample. For Bottom Boot Sector ones,MX29F400Txx will change to MX29F400Bxx)

P ART NO. Access Time Operating Current Standby Current Temperature P A CKA G E

(ns) MAX.(mA) MAX.(uA) Range

MX29F400TMC-55 55 40 5 0oC~70oC 44 Pin SOP MX29F400TMC-70 70 40 5 0oC~70oC 44 Pin SOP MX29F400TMC-90 90 40 5 0oC~70oC 44 Pin SOP MX29F400TMC-12 120 40 5 0oC~70oC 44 Pin SOP MX29F400TTC-55 5 5 40 5 0oC~70oC 48 Pin TSOP

(Normal T ype)

MX29F400TTC-70 70 40 5 0oC~70oC 48 Pin TSOP

(Normal T ype)

MX29F400TTC-90 90 40 5 0oC~70oC 48 Pin TSOP

(Normal T ype)

MX29F400TTC-12 120 4 0 5 0oC~70oC 48 Pin TSOP

(Normal T ype)

MX29F400TT A-90 90 40 20 -40oC~125oC 48 Pin TSOP

(Normal T ype)

MX29F400TT A-12 120 40 20 -40oC~125oC 48 Pin TSOP

(Normal T ype)

Note:MX29F400T/B-55 is supplied by request

P/N:PM0439

REV. 1.6, NOV. 12, 2001

Page 41

PACKAGE INFORMATION

48-PIN PLASTIC TSOP

MX29F400T/B

P/N:PM0439

REV. 1.6, NOV. 12, 2001

Page 42

44-PIN PLASTIC SOP

MX29F400T/B

P/N:PM0439

REV. 1.6, NOV. 12, 2001

Page 43

MX29F400T/B

REVISION HISTORY

Revision Description Page Date

1.0 T o remov e "Advanced Inf ormation" datasheet marking and P1 JUL/01/1999 contain information on products in full production.

1.1 T o correct the typing error on pac kage dimension. P41 SEP/01/1999 In fact,the physical packages are never changed,just correct the previously typing error.

1.2 To add the description for 100K endurance cycles P1,P40 SEP/17/1999 To modify timing of sector address loading period while P9 operating multi-sector erase from 80uS to 30uS To modify tBAL from 80uS to 100uS P20,P21

1.3 1.Program/erase cycle times:10K cycles-->100K cycles P1,34 DEC/20/1999

2.T o add data retention minimum 20 y ears P1,34

3.To remov e A9 from "timing wa v ef orm for sector protection f or P34 system without 12V" To remove A9 from "timing wav efo rm for chip unprotection f or P3 5 system without 12V"

1.4 Add erase suspend ready max. 100us in ERASE SUSPEND's P10 MA Y/29/2000 section at page10

1.5 T o modify "P ackage Inf ormation" P41~42 JUN/12/2001

1.6 Add automotive grade P16-20,40 NOV/12/2001

P/N:PM0439

REV. 1.6, NOV. 12, 2001

Page 44

MX29F400T/B

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