Datasheet MX29F200BTI-70, MX29F200BTI-90, MX29F200TMC-12, MX29F200TMC-55, MX29F200TMC-70 Datasheet (MXIC)

- Superior inadvertent write protection

• Sector protection

- Hardware method to disable any combination of
sectors from program or erase operations

- Sector protect/unprotect for 5V only system or 5V/
12V system

• 100,000 minimum erase/program cycles

• Latch-up protected to 100mA from -1V to VCC+1V

• Boot Code Sector Architecture

- T = Top Boot Sector

- B = Bottom Boot Sector

• Low VCC write inhibit is equal to or less than 3.2V

• Package type:

- 44-pin SOP

- 48-pin TSOP

• Erase suspend/ Erase Resume

- Suspends an erase operation to read data from, or
program data to a sector that is not being erased, then
resume the erase operation.

• Hardware RESET pin

- Resets internal state mechine to the read mode

• 20 years data retention

GENERAL DESCRIPTION

The MX29F200T/B is a 2-mega bit, single 5 Volt Flash
memory organized as 1M word x16 or 2M bytex8 MXIC's
Flash memories offer the most cost-effective and reli­able read/write non-volatile random access memory.
The MX29F200T/B is packaged in 44-pin SOP and 48­pin TSOP. It is designed to be reprogrammed and
erased in-system or in-standard EPROM programmers.

The standard MX29F200T/B offers access time as fast
as 55ns, allowing operation of high-speed microproces­sors without wait states. To eliminate bus contention, the
MX29F200T/B has separate chip enable (CE) and output
enable (OE ) controls.

MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F200T/B uses a command register to manage this
functionality. The command register allows for 100%

FEATURES

• 5.0V± 10% for read, erase and write operation

• 131072x16/262144x8 switchable

• Fast access time: 55/70/90/120ns

• Low power consumption

- 40mA maximum active current@5MHz

- 1uA typical standby current

• Command register architecture

- Byte/Word Programming (7us/12us typical)

- Erase (16K-Bytex1, 8K-Bytex2, 32K-Bytex1, and
64K-Byte x3)

• Auto Erase (chip) and Auto Program

- Automatically erase any combination of sectors or
the whole chip with Erase Suspend capability.

- Automatically program and verify data at specified
address

• Status Reply

- Data polling & Toggle bit for detection of program
and erase cycle completion.

• Ready/Busy pin(RY/BY)

- Provides a hardware method or detecting program
or erase cycle completion

• Compatibility with JEDEC standard

- Pinout and software compatible with single-power
supply Flash

TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi­mum EPROM compatibility.

MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields for
erase and programming operations produces reliable
cycling. The MX29F200T/B uses a 5.0V ± 10% VCC
supply to perform the High Reliability Erase and auto
Program/Erase algorithms.

The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up
protection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.

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MX29F200T/B

2M-BIT [256Kx8/128Kx16] CMOS FLASH MEMORY

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MX29F200T/B

PIN CONFIGURATIONS

44 SOP(500mil)

48 TSOP(TYPE I) (12mm x 20mm)

PIN DESCRIPTION

SYMBOL PIN NAME

A0-A16 Address Input
Q0-Q14 Data Input/Output
Q15/A-1 Q15(Word mode)/LSB addr.(Byte mode)
CE Chip Enable Input
OE Output Enable Input
RESET Hardware Reset Pin, Active low
WE Write Enable Input
RY/BY Read/Busy Output
BYTE Word/Byte Selection Input
VCC Power Supply Pin (+5V)
GND Ground Pin
NC Pin Not Connected Internally

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

NC

RY/BY

NC

A7
A6
A5
A4
A3
A2
A1
A0

CE

GND

OE
Q0
Q8
Q1
Q9
Q2

Q10

Q3

Q11

RESET
WE
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC

MX29F200T/B

A15
A14
A13
A12
A11
A10

A9

A8
NC
NC

WE

RESET

NC
NC

RY/BY

NC
NC

A7

A6

A5

A4

A3

A2

A1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

A16
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE
GND
CE
A0

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

MX29F200T/B

(NORMAL TYPE)

A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
NC
NC
A7
A6
A5
A4
A3
A2
A1

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

A16

BYTE

GND

Q15/A-1

Q7

Q14

Q6

Q13

Q5

Q12

Q4

VCC

Q11

Q3

Q10

Q2
Q9
Q1
Q8
Q0
OE

GND

CE
A0

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

MX29F200T/B

(REVERSE TYPE)

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MX29F200T/B

MX29F200T Top Boot Sector Addresses Tables

Sector Size Address Range (in hexadecimal)
(Kbytes/

A16 A15 A14 A13 A12 Kwords) (x8)Address Range (x16) Address Range

SA0 0 0 X X X 64/32 00000h-0FFFFh 00000h-07FFFh
SA1 0 1 X X X 64/32 10000h-1FFFFh 08000h-0FFFFh
SA2 1 0 X X X 64/32 20000h-2FFFFh 10000h-17FFFh
SA3 1 1 0 X X 32/16 30000h-37FFFh 18000h-1BFFFh
SA41 11008/4 38000h-39FFFh 1C000h-1CFFFh
SA51 11018/4 3A000h-3BFFFh 1D000h-1DFFFh
SA61 111X16/8 3C000h-3FFFFh 1E000h-1FFFFh

MX29F200B Bottom Boot Sector Addresses Tables

Sector Size Address Range (in hexadecimal)
(Kbytes/

A16 A15 A14 A13 A12 Kwords) (x8)Address Range (x16) Address Range

SA00000X16/8 00000h-03FFFh 00000h-01FFFh

SA1000108/4 04000h-05FFFh 02000h-02FFFh
SA2000118/4 06000h-07FFFh 03000h-03FFFh
SA3001XX32/16 08000h-0FFFFh 04000h-07FFFh
SA4 0 1 X X X 64/32 10000h-1FFFFh 08000h-0FFFFh
SA5 1 0 X X X 64/32 20000h-2FFFFh 10000h-17FFFh
SA6 1 1 X X X 64/32 30000h-3FFFFh 18000h-1FFFFh

SECTOR STRUCTURE

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MX29F200T/B

BLOCK DIAGRAM

CONTROL
INPUT

LOGIC

PROGRAM/ERASE

HIGH VOLT AGE

WRITE

STATE

MACHINE

(WSM)

STATE

REGISTER

MX29F200T/B

FLASH
ARRA Y

X-DECODER

ADDRESS

LA TCH

AND

BUFFER

Y-PASS GATE

Y-DECODER

ARRAY

SOURCE

HV

COMMAND

DATA
DECODER

COMMAND

DATA LATCH

I/O BUFFER

PGM

DATA

HV

PROGRAM

DATA LATCH

SENSE

AMPLIFIER

A-1/Q15

Q0-Q14

A0-A16

CE
OE

WE

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MX29F200T/B

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stand­ard microprocessor write timings. The device will auto­matically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
verifies the erase and counts the number of sequences.
A status bit toggling between consecutive read cycles
provides feedback to the user as to the status of the
programming operation.

Register contents serve as inputs to an internal state­machine which controls the erase and programming
circuitry. During write cycles, the command register
internally latches addresses and data needed for the
programming and erase operations. During a system
write cycle, addresses are latched on the falling edge,
and data are latched on the rising edge of WE .

MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality,
reliability, and cost effectiveness. The MX29F200T/B
electrically erases all bits simultaneously using Fowler­Nordheim tunneling. The bytes are programmed by
using the EPROM programming mechanism of hot
electron injection.

During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is complete,
the device stays in read mode. After the state machine
has completed its task, it will allow the command register
to respond to its full command set.

AUTOMATIC PROGRAMMING

The MX29F200T/B is byte programmable using the
Automatic Programming algorithm. The Automatic Pro­gramming algorithm does not require the system to time
out sequence or verify the data programmed. The
typical chip programming time of the MX29F200T/B at
room temperature is less than 2 seconds.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished in
less than two second. The Automatic Erase algorithm
automatically programs the entire array prior to electrical
erase. The timing and verification of electrical erase are
internally controlled by the device.

AUTOMATIC SECTOR ERASE

The MX29F200T/B is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. Sector erase modes allow
sectors of the array to be erased in one erase cycle. The
Automatic Sector Erase algorithm automatically pro­grams the specified sector(s) prior to electrical erase.
The timing and verification of electrical erase are inter­nally controlled by the device.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm requires the
user to only write program set-up commands (include 2
unlock write cycle and A0H) and a program command
(program data and address). The device automatically
times the programming pulse width, verifies the pro­gram, and counts the number of sequences. A status bit
similar to DATA polling and a status bit toggling between
consecutive read cycles, provides feedback to the user
as to the status of the programming operation.

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MX29F200T/B

TABLE1. SOFTWARE COMMAND DEFINITIONS

First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus

Command Bus Cycle Cycle Cycle Cycle Cycle Cycle

Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Reset 1 XXXH F0H
Read 1 RA RD
Read Silicon ID Word 4 555H AAH 2AAH 55H 555H 90H ADI DDI

Byte 4 AAAH AAH 555H 55H AAAH 90H AD I DDI
Sector Protect Word 4 555H AAH 2AAH 55H 555H 90H (SA) XX00H
Verify X02H XX01H

Byte 4 AAAH AAH 555H 55H AAAH 90H (SA) 00

X04H 01

Porgram Word 4 555H AAH 2AAH 55H 555H A0H PA PD

Byte 4 AAAH AAH 555H 55H AAAH A0H PA PD
Chip Erase Word 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H

Byte 6 AAAH AAH 555H 55H AAAH 8 0H AAAH AAH 555H 55H AAAH 10H
Sector Erase Word 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H

Byte 6 AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H SA 30H
Sector Erase Suspend 1 XXXH B0H
Sector Erase Resume 1 XXXH 30 H
Unlock for sector 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 20H
protect/unprotect

NOTE:

1. ADI = Address of Device identifier; A1=0, A0 =0 for manufacture code, A1=0, A0 =1 for device code.(Refer to Table 3)
DDI = Data of Device identifier : C2H for manufacture code,51H/57H(x8) and 2251H/2257H(x16) for device code.
X = X can be VIL or VIH
RA=Address of memory location to be read.
RD=Data to be read at location RA.

2. PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA.
SA = Address to the sector to be erased.

3. The system should generate the following address patterns: 555H or 2AAH to Address A0~A10.
Address bit A11~A16=X=Don't care for all address commands except for Program Address (PA) and Sector Address (SA).
Write Sequence may be initiated with A11~A16 in either state.

4. For Sector Protection Verify Operation : If read out data is 01H, it means the sector has been protected. If read out data is
00H, it means the sector is still not being protected.

COMMAND DEFINITIONS

Device operations are selected by writing specific ad­dress and data sequences into the command register.
Writing incorrect address and data values or writing
them in the improper sequence will reset the device to
the read mode. Table 1 defines the valid register

command sequences. Note that the Erase Suspend
(B0H) and Erase Resume (30H) commands are valid
only while the Sector Erase operation is in progress.
Either of the two reset command sequences will reset
the device(when applicable).

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MX29F200T/B

TABLE 2. MX29F200T/B BUS OPERATION

Pins CE OE WE A0 A1 A6 A9 Q0 ~ Q15
Mode
Read Silicon ID L L H L L X VID(2) C2H(Byte mode)
Manfacturer Code(1) 00C2H(Word mode)
Read Silicon ID L L H H L X VID(2) 51H/57H(Byte mode)
Device Code(1) 2251H/2257H(Word mode)
Read L L H A0 A1 A6 A9 D

OUT

Standby H X XXXX X HIGH Z
Output Disable L H H X X X X HIGH Z
Write L H L A0 A1 A6 A9 DIN(3)
Sector Protect with 12V L VID(2) L X X L VID(2) X
system(6)
Chip Unprotect with 12V L VID(2) L X X H VID(2) X
system(6)
Verify Sector Protect L L H X H X VID(2) Code(5)
with 12V system
Sector Protect without 12V L H L X X L H X
system (6)
Chip Unprotect without 12V L H L X X H H X
system (6)
Verify Sector Protect/ L L H X H X H Code(5)
Unprotect without 12V
system (7)
Reset X X XXXX X HIGH Z

NOTES:

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.

2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.

3. Refer to Table 1 for valid Data-In during a write operation.

4. X can be VIL or VIH.

5. Code=00H/0000H means unprotected.
Code=01H/0001H means protected.
A16~A12=Sector address for sector protect.

6. Refer to sector protect/unprotect algorithm and waveform.
Must issue "unlock for sector protect/unprotect" command before "sector protect/unprotect without 12V system"

command.

7. The "verify sector protect/unprotect without 12V sysytem" is only following "Sector protect/unprotect without 12V
system" command.

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MX29F200T/B

READ/RESET COMMAND

The read or reset operation is initiated by writing the
read/reset command sequence into the command reg­ister. Microprocessor read cycles retrieve array data.
The device remains enabled for reads until the com­mand register contents are altered.

If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid command
must then be written to place the device in the desired
state.

SILICON-ID-READ COMMAND

Flash memories are intended for use in applications
where the local CPU alters memory contents. As such,
manufacturer and device codes must be accessible
while the device resides in the target system. PROM
programmers typically access signature codes by rais­ing A9 to a high voltage. However, multiplexing high
voltage onto address lines is not generally desired
system design practice.

The MX29F200T/B contains a Silicon-ID-Read opera­tion to supplement traditional PROM programming meth­odology. The operation is initiated by writing the read
silicon ID command sequence into the command regis­ter. Following the command write, a read cycle with
A1=VIL,A0=VIL retrieves the manufacturer code of C2H/
00C2H. A read cycle with A1=VIL, A0=VIH returns the
device code of 51H/2251H for MX29F200T, 57H/2257H
for MX29F200B.

SET-UP AUTOMATIC CHIP/SECTOR ERASE
COMMANDS

Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cycles
are then followed by the chip erase command 10H.

The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the
Automatic Chip Erase. Upon executing the Automatic
Chip Erase, the device will automatically program and
verify the entire memory for an all-zero data pattern.
When the device is automatically verified to contain an
all-zero pattern, a self-timed chip erase and verify begin.
The erase and verify operations are completed when the
data on Q7 is "1" at which time the device returns to the
Read mode. The system does not require to provide
any control or timing during these operations.

When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array(no
erase-verified command is required).

If the Erase operation was unsuccessful, the data on Q5
is "1"(see Table 4), indicating an erase operation exceed
internal timing limit.

The automatic erase begins on the rising edge of the last
WE pulse in the command sequence and terminates
when the data on Q7 is "1" and the data on Q6 stops
toggling for two consecutive read cycles, at which time
the device returns to the Read mode.

TABLE 3. EXPANDED SILICON ID CODE

Pins A0 A1 Q15~Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code(Hex) Code
Manufacture code Word VIL VIL 00H 1100001000C2H

Byte VIL VIL X 11000010C2H
Device code Word VIH VIL 22H 010100012251H
for MX29F200T Byte VIH VIL X 0101000151H
Device code Word VIH VIL 22H 010101112257H
for MX29F200B Byte VIH VIL X 0101011157H
Sector Portection X VIH X 0000000101H(Protected)
Verification X VIH X 0000000000H(Unprotected)

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MX29F200T/B

SECTOR ERASE COMMANDS

The Automatic Sector Erase does not require the device
to be entirely pre-programmed prior to executing the
Automatic Set-up Sector Erase command and Automatic
Sector Erase command. Upon executing the Automatic
Sector Erase command, the device will automatically
program and verify the sector(s) memory for an all-zero
data pattern. The system does not require to provide
any control or timing during these operations.

When the sector(s) is automatically verified to contain an
all-zero pattern, a self-timed sector erase and verification
begin. The erase and verification operations are complete
when the data on Q7 is "1" and the data on Q6 stops
toggling for two consecutive read cycles, at which time
the device returns to the Read mode. The system does
not require to provide any control or timing during these
operations.

When using the Automatic Sector Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase-verified command is required). Sector erase
is a six-bus cycle operation. There are two "unlock" write
cycles. These are followed by writing the set-up command
80H. Two more "unlock" write cycles are then followed
by the sector erase command 30H. The sector address
is latched on the falling edge of WE, while the
command(data) is latched on the rising edge of WE.
Sector addresses selected are loaded into internal register
on the sixth falling edge of WE. Each successive sector
load cycle started by the falling edge of WE must begin
within 30us from the rising edge of the preceding WE.
Otherwise, the loading period ends and internal auto
sector erase cycle starts. (Monitor Q3 to determine if the
sector erase timer window is still open, see section Q3,
Sector Erase Timer.) Any command other than Sector
Erase (30H) or Erase Suspend (B0H) during the time­out period resets the derice to read mode.

ERASE SUSPEND

This command is only valid while the state machine is
executing Automatic Sector Erase operation, and
therefore will only be responded to period during Automatic
Sector Erase operation. Writing the Erase Suspend
command during the Sector Erase time-out immediately
terminates the time-out period and suspends the erase
operation. After this command has been executed, the
command register will initiate erase suspend mode. The
state machine will return to read mode automatically after
suspend is ready. At this time, state machine only allows
the command register to respond to the Read Memory
Array, Erase Resume and Program commands.

The system can determine the status of the program
operation using the Q7 or Q6 status bits, just as in the
standard program operation. After an erase-suspend
program operation is complete, the system can once
again read array data within non-suspended sectors.

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MX29F200T/B

Status Q7 Q6 Q5 Q3 Q2 RY/BY

Note1 Note2

Byte Program in Auto Program Algorithm Q7 Toggle 0 N/A No 0

Toggle

Auto Erase Algorithm 0 Toggle 0 1 Toggle 0

Erase Suspend Read 1 N o 0 N/A Toggle 1
(Erase Suspended Sector) Toggle

In Progress

Erase Suspended Mode Erase Suspend Read Data Data Data Data Data 1

(Non-Erase Suspended Sector)
Erase Suspend Program Q7 Toggle 0 N/A N/A 0

Byte Program in Auto Program Algorithm Q7 Toggle 1 N/A No 0

Toggle
Exceeded
Time Limits Auto Erase Algorithm 0 Toggle 1 1 Toggle 0

Erase Suspend Program Q7 Toggle 1 N/A N/A 0

Table 4. Write Operation Status

Note:

1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.

2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.
See "Q5:Exceeded Timing Limits " for more information.

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MX29F200T/B

ERASE RESUME

This command will cause the command register to clear
the suspend state and return back to Sector Erase mode
but only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions.Another Erase Suspend command can
be written after the chip has resumed erasing.

SET-UP AUTOMATIC PROGRAM
COMMANDS

To initiate Automatic Program mode, A three-cycle
command sequence is required. There are two "unlock"
write cycles. These are followed by writing the Automatic
Program command A0H.

Once the Automatic Program command is initiated, the
next WE pulse causes a transition to an active
programming operation. Addresses are latched on the
falling edge, and data are internally latched on the rising
edge of the WE pulse. The rising edge of WE also begins
the programming operation. The system does not
require to provide further controls or timings. The device
will automatically provide an adequate internally
generated program pulse and verify margin.

If the program opetation was unsuccessful, the data on
Q5 is "1"(see Table 4), indicating the program operation
exceed internal timing limit. The automatic programming
operation is completed when the data read on Q6 stops
toggling for two consecutive read cycles and the data on
Q7 and Q6 are equivalent to data written to these two
bits, at which time the device returns to the Read
mode(no program verify command is required).

WRITE OPERATION STATUS DATA
POLLING-Q7

The MX29F200T/B also features Data Polling as a
method to indicate to the host system that the Automatic
Program or Erase algorithms are either in progress or
completed.

While the Automatic Programming algorithm is in
operation, an attempt to read the device will produce the
complement data of the data last written to Q7. Upon
completion of the Automatic Program Algorithm an
attempt to read the device will produce the true data last
written to Q7. The Data Polling feature is valid after the
rising edge of the fourth WE pulse of the four write pulse
sequences for automatic program.

While the Automatic Erase algorithm is in operation, Q7
will read "0" until the erase operation is competed. Upon
completion of the erase operation, the data on Q7 will
read "1". The Data Polling feature is valid after the rising
edge of the sixth WE pulse of six write pulse sequences
for automatic chip/sector erase.

The Data Polling feature is active during Automatic
Program/Erase algorithm or sector erase time-out.(see
section Q3 Sector Erase Timer)

RY/BY:Ready/Busy

The RY/BY is a dedicated, open-drain output pin that
indicates whether an Automatic Erase/Program algorithm
is in progress or complete. The RY/BY status is valid
after the rising edge of the final WE pulse in the command
sequence. Since RY/BY is an open-drain output, several
RY/BY pins can be tied together in parallel with a pull-up
resistor to Vcc.

If the outputs is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready), the
device is ready to read array data (including during the
Erase Suspend mode), or is in the standby mode.

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MX29F200T/B

Q2:Toggle Bit II

The "Toggle Bit II" on Q2, when used with Q6, indicates
whether a particular sector is actively erasing (that is, the
Automatic Erase alorithm is in process), or whether that
sector is erase-suspended. Toggle Bit I is valid after the
rising edge of the final WE pulse in the command
sequence.

Q6:Toggle BIT I

Toggle Bit I on Q6 indicates whether an Automatic
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE pulse in the
command sequence(prior to the program or erase
operation), and during the sector time-out.

During an Automatic Program or Erase algorithm
operation, successive read cycles to any address cause
Q6 to toggle. The system may use either OE or CE to
control the read cycles. When the operation is complete,
Q6 stops toggling.

After an erase command sequence is written, if all
sectors selected for erasing are protected, Q6 toggles
and returns to reading array data. If not all selected
sectors are protected, the Automatic Erase algorithm
erases the unprotected sectors, and ignores the selected
sectors that are protected.

The system can use Q6 and Q2 together to determine
whether a sector is actively erasing or is erase suspended.
When the device is actively erasing (that is, the Automatic
Erase algorithm is in progress), Q6 toggling. When the
device enters the Erase Suspend mode, Q6 stops
toggling. However, the system must also use Q2 to
determine which sectors are erasing or erase-suspended.
Alternatively, the system can use Q7.

If a program address falls within a protected sector, Q6
toggles for approximately 2us after the program command
sequence is written, then returns to reading array data.

Q6 also toggles during the erase-suspend-program
mode, and stops toggling once the Automatic Program
algorithm is complete.

Table 4 shows the outputs for Toggle Bit I on Q6.

Q2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use either OE or CE to control the read
cycles.) But Q2 cannot distinguish whether the sector is
actively erasing or is erase-suspended. Q6, by
comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both
status bits are required for sectors and mode information.
Refer to Table 4 to compare outputs for Q2 and Q6.

Reading Toggle Bits Q6/ Q2

Whenever the system initially begins reading toggle bit
status, it must read Q7-Q0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system
can read array data on Q7-Q0 on the following read
cycle.

However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system
also should note whether the value of Q5 is high (see the
section on Q5). If it is, the system should then determine
again whether the toggle bit is toggling, since the toggle
bit may have stopped toggling just as Q5 went high. If
the toggle bit is no longer toggling, the device has
successfuly completed the program or erase operation.
If it is still toggling, the device did not complete the
operation successfully, and the system must write the
reset command to return to reading array data.

The remaining scenario is that system initially determines
that the toggle bit is toggling and Q5 has not gone high.
The system may continue to monitor the toggle bit and
Q5 through successive read cycles, determining the
status as described in the previous paragraph.
Alternatively, it may choose to perform other system
tasks. In this case, the system must start at the beginning
of the algorithm when it returns to determine the status
of the operation.

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MX29F200T/B

Exceeded Timing Limits

Q5 will indicate if the program or erase time has exceeded
the specified limits(internal pulse count). Under these
conditions Q5 will produce a "1". This time-out condition
which indicates that the program or erase cycle was not
successfully completed. Data Polling and Toggle Bit are
the only operating functions of the device under this
condition.

If this time-out condition occurs during sector erase
operation, it specifies that a particular sector is bad and
it may not be reused. However, other sectors are still
functional and may be used for the program or erase
operation. The device must be reset to use other
sectors. Write the Reset command sequence to the
device, and then execute program or erase command
sequence. This allows the system to continue to use the
other active sectors in the device.

If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or
combination of sectors are bad.

If this time-out condition occurs during the byte
programming operation, it specifies that the entire
sector containing that byte is bad and this sector maynot
be reused, (other sectors are still functional and can be
reused).

The time-out condition may also appear if a user tries to
program a non blank location without erasing. In this
case the device locks out and never completes the
Automatic Algorithm operation. Hence, the system
never reads a valid data on Q7 bit and Q6 never stops
toggling. Once the Device has exceeded timing limits,
the Q5 bit will indicate a "1". Please note that this is not
a device failure condition since the device was incorrectly
used.

Sector Erase Timer

After the completion of the initial sector erase command
sequence, the sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data Polling
and Toggle Bit are valid after the initial sector erase
command sequence.

If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, Q3 may be
used to determine if the sector erase timer window is still
open. If Q3 is high ("1") the internally controlled erase
cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or
Toggle Bit. If Q3 is low ("0"), the device will accept
additional sector erase commands. To insure the
command has been accepted, the system software
should check the status of Q3 prior to and following each
subsequent sector erase command. If Q3 were high on
the second status check, the command may not have
been accepted.

DATA PROTECTION

The MX29F200T/B is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power
transition. During power up the device automatically
resets the state machine in the Read mode. In addition,
with its control register architecture, alteration of the
memory contents only occurs after successful completion
of specific command sequences. The device also
incorporates several features to prevent inadvertent
write cycles resulting from VCC power-up and power­down transition or system noise.

TEMPORARY SECTOR UNPROTECT

This feature allows temporary unprotection of previously
protected sector to change data in-system. The Tempo­rary Sector Unprotect mode is activated by setting the
RESET pin to VID(11.5V-12.5V). During this mode,
formerly protected sectors can be programmed or erased
as un-protected sector. Once VID is remove from the
RESET pin,all the previously protected sectors are
protected again.

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns(typical) on CE or WE will
not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE = VIL, CE
= VIH or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.

Q3

Q5

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MX29F200T/B

SECTOR PROTECTION WITH 12V SYSTEM

The MX29F200T/B features hardware sector protection.
This feature will disable both program and erase
operations for these sectors protected. To activate this
mode, the programming equipment must force VID on
address pin A9 and control pin OE, (suggest VID = 12V)
A6 = VIL and CE = VIL.(see Table 2) Programming of
the protection circuitry begins on the falling edge of the
WE pulse and is terminated on the rising edge. Please
refer to sector protect algorithm and waveform.

To verify programming of the protection circuitry, the
programming equipment must force VID on address pin
A9 ( with CE and OE at VIL and WE at VIH. When A1=1,
it will produce a logical "1" code at device output Q0 for
a protected sector. Otherwise the device will produce
00H for the unprotected sector. In this mode, the
addresses,except for A1, are in "don't care" state.
Address locations with A1 = VIL are reserved to read
manufacturer and device codes.(Read Silicon ID)

It is also possible to determine if the sector is protected
in the system by writing a Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
a logical "1" at Q0 for the protected sector.

CHIP UNPROTECT WITH 12V SYSTEM

The MX29F200T/B also features the chip unprotect
mode, so that all sectors are unprotected after chip
unprotect is completed to incorporate any changes in
the code. It is recommended to protect all sectors before
activating chip unprotect mode.

To activate this mode, the programming equipment
must force VID on control pin OE and address pin A9.
The CE pins must be set at VIL. Pins A6 must be set to
VIH.(see Table 2) Refer to chip unprotect algorithm and
waveform for the chip unprotect algorithm. The
unprotection mechanism begins on the falling edge of
the WE pulse and is terminated on the rising edge .

It is also possible to determine if the chip is unprotected

SECTOR PROTECTION WITHOUT 12V
SYSTEM

The MX29F200T/B also feature a hardware sector
protection method in a system without 12V power suppply.
The programming equipment do not need to supply 12
volts to protect sectors. The details are shown in sector
protect algorithm and waveform.

CHIP UNPROTECT WITHOUT 12V SYSTEM

The MX29F200T/B also feature a hardware chip
unprotection method in a system without 12V power
supply. The programming equipment do not need to
supply 12 volts to unprotect all sectors. The details are
shown in chip unprotect algorithm and waveform.

POWER-UP SEQUENCE

The MX29F200T/B powers up in the Read only mode. In
addition, the memory contents may only be altered after
successful completion of the predefined command
sequences.

POWER SUPPLY DECOUPLING

In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected
between its VCC and GND.

in the system by writing the Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
00H at data outputs(Q0-Q7) for an unprotected sector.
It is noted that all sectors are unprotected after the chip
unprotect algorithm is completed.

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MX29F200T/B

Temporary Sector Unprotect Operation

Start

RESET = VID (Note 1)

Perform Erase or Program Operation

RESET = VIH

Temporary Sector Unprotect Completed(Note 2)

Operation Completed

2. All previously protected sectors are protected again.

Note :

1. All protected sectors are temporary unprotected.
VID=11.5V~12.5V

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MX29F200T/B

RESET

CE

WE

RY/BY

tVIDR

tVIDR

Program or Erase Command Sequence

12V

0 or 5V

0 or 5V

tRSP

TEMPORARY SECTOR UNPROTECT

Parameter Std. Description Test Setup AllSpeed Options Unit

tVIDR VID Rise and Fall Time (See Note) Min 50 0 ns
tRSP RESET Setup Time for Temporary Sector Unprotect Min 4 us

Note:
Not 100% tested

Temporary Sector Unprotect Timing Diagram

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MX29F200T/B

RESET TIMING WAVFORM

Parameter Std Description Test Setup All Speed Options Unit

tREADY1 RESET PIN Low (During Automatic Algorithms) MAX 20 us

to Read or Write (See Note)

tREADY2 RESET PIN Low (NOT During Automatic MAX 5 00 ns

Algorithms) to Read or Write (See Note)
tRP1 RESET Pulse Width (During Automatic Algorithms) MI N 10 us
tRP2 RESET Pulse Width (NOT During Automatic Algorithms) MIN 500 ns
tR H RESET High Time Before Read(See Note) MIN 0 n s
tRB1 RY/BY Recovery Time(to CE, OE go low) MIN 0 n s
tRB2 RY/BY Recovery Time(to WE go low) MIN 5 0 ns

Note:Not 100% tested

tRH

tRB1

tRB2

tReady1

tRP2

tRP1

tReady2

RY/BY

CE, OE

RESET

Reset Timing NOT during Automatic Algorithms

Reset Timing during Automatic Algorithms

RY/BY

CE, OE

RESET

WE

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REV. 1.3 , DEC. 24, 2001

MX29F200T/B

ABSOLUTE MAXIMUM RATINGS

RATING VALUE

Ambient Operating Temperature -40oC to 85oC
Ambient Temperature with Power -55oC to 125oC
Applied
Storage Temperature -65oC to 125oC
Applied Input Voltage -0.5V to 7.0V
Applied Output Voltage -0.5V to 7.0V
VCC to Ground Potential -0.5V to 7.0V
A9&OE -0.5V to 13.5V

NOTICE:

Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended period may affect reliability.

NOTICE:

Specifications contained within the following tables are
subject to change.

DC/AC Operating Conditions for Read Operation

MX29F200T/B

-55 -70 -90 -12

Operating Temperature Commercial 0oCto 70oC0oCto 70oC0oCto 70oC0oCto 70oC

Industrial -40oCto 85oC -40oCto 85oC -40oCto 85oC
Automotive -40oC to 125oC -40oC to 125oC

Vcc Power Supply 5V±5% 5V±10% 5V±10% 5V±10%

CAPACITANCE TA = 25oC, f = 1.0 MHz

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS

CIN1 Input Capacitance 8 pF VIN = 0V
CIN2 Control Pin Capacitance 12 pF VIN = 0V
COUT Output Capacitance 12 pF VOUT = 0V

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MX29F200T/B

DC CHARACTERISTICS

Symbol PARAMETER MIN. TYP MAX. UNIT CONDITIONS

ILI Input Leakage Current 1(Note3) uA VIN = GND to VCC
ILO Output Leakage Current 10 uA VOUT = GND to VCC
ISB1 Standby VCC current 1 mA CE = VIH
ISB2 1(Note5) 5(Note5) uA CE = VCC + 0.3V
ICC1 Operating VCC current 40(Note4) mA IOUT = 0mA, f=5MHz
ICC2 50 mA IOUT = 0mA, f=10MHz
VIL Input Low Voltage -0.3(Note1) 0.8 V
VIH Input High Voltage 2.0 VCC+0.3 V
VOL Output Low Voltage 0.45 V IOL = 2.1mA
VOH1 Output High Voltage(TTL) 2.4 V IOH = -2mA
VOH2 Output High Voltage(CMOS) VCC-0.4 V IOH = -100uA,VCC=VCC MIN

NOTES:

1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns.
VIL min. = -2.0V for pulse width is equal to ot less than 20 ns.

2. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns
If VIH is over the specified maximum value, read operation cannot be guaranteed.

3. ILI=10uA for Industrial Grade.

4. ICC1=45mA for Industrial Grade.

5. ISB2 maximum 20uA for automative grade.

READ OPERATION

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MX29F200T/B

AC CHARACTERISTICS

29F200T/B-55 29F200T/B-70

SYMBOL PARAMETER MIN. MAX. MIN. MAX. UNIT CONDITIONS

tACC Address to Output Delay 55 7 0 ns CE=OE=VIL
tCE CE to Output Delay 55 70 ns OE=VIL
tOE OE to Output Delay 20 40 ns CE=VIL
tDF OE High to Output Float (Note1) 0 20 0 20 ns CE=VIL
tOH Address to Output hold 0 0 ns CE=OE=VIL

NOTE:

1.tDF is defined as the time at which the output achieves the
open circuit condition and data is no longer driven.

TEST CONDITIONS:

• Input pulse levels: 0.45V/2.4V for 70ns max, 0V/3V for
55ns

• Input rise and fall times: is equal to or less than 10ns
for 70ns max,5ns for 55ns

• Output load: 1 TTL gate + 100pF (Including scope and
jig) for 70ns max.

:1TTLgate+30pF for 55ns max.

• Reference levels for measuring timing: 0.8V, 2.0V for
70ns max.;1.5V for 55ns

READ TIMING WAVEFORMS

A0~16

CE

OE

tACC

WE

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

HIGH Z HIGH Z

DATA V alid

tOE

tDF

tCE

DATA

Q0~7

tOH

ADD Valid

29F200T/B-90 29F200T/B-12

SYMBOL PARAMETER MIN. MAX. MIN. MAX. UNIT CONDITIONS

tACC Address to Output Delay 90 1 2 0 ns CE=OE=VIL
tCE CE to Output Delay 90 120 ns OE=VIL
tOE OE to Output Delay 40 50 ns CE=VIL
tDF OE High to Output Float (Note1) 0 30 0 30 ns CE=VIL
tOH Address to Output hold 0 0 ns CE=OE=VIL

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MX29F200T/B

DC CHARACTERISTICS

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS

ICC1 (Read) Operating VCC Current 40(Note5) mA IOUT=0mA, f=5MHz
ICC2 50 mA IOUT=0mA, F=10MHz
ICC3 (Program) 50 mA In Programming
ICC4 (Erase) 50 mA In Erase
ICCES VCC Erase Suspend Current 2 mA CE=VIH, Erase Suspended

NOTES:

1. VIL min. = -0.6V for pulse width is equal to or less than 20ns.

2. If VIH is over the specified maximum value, programming operation cannot be guranteed.

3. ICCES is specified with the device de-selected. If the device is read during erase suspend mode, current draw is

the sum of ICCES and ICC1 or ICC2.

4. All current are in RMS unless otherwise noted.

5. ICC1 (Read)=45mA for Industrial Grade.

DC/AC Operating Conditions for Programming/Erase Operation

MX29F200T/B

-55 -70 -90 -12

Operating Temperature Commercial 0oC to 70oC0oC to 70oC0oC to 70oC0oC to 70oC

Industrial -40oC to 85oC -40oC to 85oC -40oC to 85oC
Automotive -40oC to 125oC -40oC to 125oC

Vcc Power Supply 5V±5% 5V±10% 5V±10% 5V±10%

COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION

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MX29F200T/B

AC CHARACTERISTICS

29F200T/B-55(Note2) 29F200T/B-70

SYMBOL PARAMETER MIN. MAX. MIN. MAX. UNIT

tOES OE setup time 0 0 ns
tCWC Command programming cycle 70 70 ns
tCEP WE programming pulse width 45 45 ns
tCEPH1 WE programming pluse width High 20 20 ns
tCEPH2 WE programming pluse width High 20 20 ns
tAS Address setup time 0 0 ns
tAH Address hold time 45 45 ns
tDS Data setup time 20 30 ns
tDH Data hold time 0 0 n s
tCESC CE setup time before command write 0 0 ns
tDF Output disable time (Note 1) 20 30 ns
tAETC Total erase time in auto chip erase 3(TYP.) 2 4 3(TYP.) 24 s
tAETB Total erase time in auto sector erase 1(TYP.) 8 1(TYP.) 8 s
tAVT Total programming time in auto verify 7/12(TYP.) 210/360 7/12(TYP.) 210/360 us
tBAL Sector address load time 1 0 0 1 00 us
tCH CE Hold Time 0 0 ns
tCS CE setup to WE going low 0 0 ns
tVLHT Voltge Transition Time 4 4 us
tOESP OE Setup Time to WE Active 4 4 us
tWPP Write pulse width for sector protect 10 10 us
tWPP2 Write pulse width for sector unprotect 12 1 2 ms

NOTES:

1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.

2.Under condition of VCC=5V±5%,CL=30pF,VIH/VIL=3.0V/0V,VOH/VOL=1.5V/1.5V,IOL=2mA,IOH=2mA.

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MX29F200T/B

AC CHARACTERISTICS

29F200T/B-90 29F200T/B-120

SYMBOL PARAMETER MIN. MAX. MIN. MAX. UNIT

tOES OE setup time 0 0 ns
tCWC Command programming cycle 90 120 ns
tCEP WE programming pulse width 45 50 ns
tCEPH1 WE programming pluse width High 20 20 ns
tCEPH2 WE programming pluse width High 20 20 ns
tAS Address setup time 0 0 ns
tAH Address hold time 45 50 ns
tDS Data setup time 45 50 ns
tDH Data hold time 0 0 n s
tCESC CE setup time before command write 0 0 ns
tDF Output disable time (Note 1) 40 40 ns
tAETC Total erase time in auto chip erase 3(TYP.) 2 4 3(TYP.) 24 s
tAETB Total erase time in auto sector erase 1(TYP.) 8 1(TYP.) 8 s
tAVT Total programming time in auto verify 7/12(TYP.) 210/360 7/12(TYP.) 210/360 us
tBAL Sector address load time 1 0 0 1 00 us
tCH CE Hold Time 0 0 ns
tCS CE setup to WE going low 0 0 ns
tVLHT Voltge Transition Time 4 4 us
tOESP OE Setup Time to WE Active 4 4 us
tWPP Write pulse width for sector protect 10 10 us
tWPP2 Write pulse width for sector unprotect 12 1 2 ms

NOTES:

1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.

2.Under condition of VCC=5V±5%,CL=30pF,VIH/VIL=3.0V/0V,VOH/VOL=1.5V/1.5V,IOL=2mA,IOH=2mA.

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MX29F200T/B

SWITCHING TEST CIRCUITS

SWITCHING TEST WAVEFORMS(I) for 29F200T/B-70, 29F200T/B-90, 29F200T/B-12

SWITCHING TEST WAVEFORMS(II) for 29F200T/B-55

DEVICE UNDER

TEST

DIODES=IN3064

OR EQUIVALENT

CL

1.2K ohm

1.6K ohm
+5V

CL=100pF Including jig capacitance for 70ns max.

CL= 30pF Including jig capacitance for 55ns max.

2.0V 2.0V

0.8V

0.8V

TEST POINTS

2.4V

0.45V

AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".
Input pulse rise and fall times are < 10ns.

OUTPUT

INPUT

1.5V 1.5V

TEST POINTS

3.0V

0V

AC TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0".
Input pulse rise and fall times are < 5ns.

OUTPUT

INPUT

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MX29F200T/B

COMMAND WRITE TIMING WAVEFORM

ADDRESS

A0~16

CE

OE

WE

DIN

tDS

tAH

DATA

Q0-7

tDH

tCS tCH

tCWC

tCEPH1

tCEP

tOES

tAS

VCC

5V

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

ADD Valid

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MX29F200T/B

AUTOMATIC PROGRAMMING TIMING
WAVEFORM

One byte data is programmed. Verify in fast algorithm
and additional programming by external control are not
required because these operations are executed auto­matically by internal control circuit. Programming
completion can be verified by DATA polling and toggle

bit checking after automatic verification starts. Device
outputs DATA during programming and DATA after
programming on Q7.(Q6 is for toggle bit; see toggle bit,
DATA polling, timing waveform).

AUTOMATIC PROGRAMMING TIMING WAVEFORM (WORD MODE)

tCWC

tAS

tCEP

tDS tDH

tDF

Vcc 5V

CE

OE

Q0~Q2

,Q4(Note 1)

WE

A11~A16

tCEPH1

tAH

ADD Valid

tCESC

Q7

Command In

ADD Valid

A0~A10

Command InCommand In Data In

DATA

Command In Command InCommand In Data In

DATADATA

tAVT

tOE

DATA polling

2AAH

555H

555H

Command #AAH Command #55H

Command #A0H

(Q0~Q7)

Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit

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MX29F200T/B

AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART (WORD MODE)

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Program Data/Address

Write Data A0H Address 555H

YES

NO

Toggle Bit Checking
Q6 not Toggled

Verify Byte Ok

YES

Q5 = 1

Reset

Auto Program Completed

Auto Program Exceed
Timing Limit

NO

Invalid
Command

YES

NO

.

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MX29F200T/B

All data in chip are erased. External erase verification is
not required because data is erased automatically by
internal control circuit. Erasure completion can be
verified by DATA polling and toggle bit checking after

AUTOMATIC CHIP ERASE TIMING WAVEFORM (WORD MODE)

AUTOMATIC CHIP ERASE TIMING WAVEFORM

automatic erase starts. Device outputs 0 during erasure
and 1 after erasure 0n Q7.(Q6 is for toggle bit; see toggle
bit, DATA polling, timing waveform)

tCWC

tAS

tCEP

tDS tDH

Vcc 5V

CE

OE

Q0,Q1,

Q4(Note 1)

WE

A11~A16

tCEPH1

tAH

Q7

Command In

A0~A10

Command InCommand In

Command In Command InCommand In

tAETC

DATA polling

2AAH

555H

555H

Command #AAH Command #55H

Command #80H

(Q0~Q7)

Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

555H

2AAH 555H

Command In

Command In

Command #AAH

Command In

Command In

Command #55H

Command In

Command In

Command #10H

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MX29F200T/B

AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART (WORD MODE)

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data AAH Address 555H

Write Data 80H Address 555H

YES

NO

Toggle Bit Checking

Q6 not Toggled

Write Data 10H Address 555H

Write Data 55H Address 2AAH

Reset

Auto Chip Erase Exceed
Timing Limit

DATA Polling

Q7 = 1

YES

YES

Q5 = 1

Auto Chip Erase Completed

NO

.

NO

Invalid
Command

30

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REV. 1.3 , DEC. 24, 2001

MX29F200T/B

AUTOMATIC SECTOR ERASE TIMING WAVEFORM (WORD MODE)

AUTOMATIC SECTOR ERASE TIMING WAVEFORM

Sector data indicated by A12 to A16 are erased. External
erase verification is not required because data are
erased automatically by internal control circuit. Erasure
completion can be verified by DATA polling and toggle

bit checking after automatic erase starts. Device outputs
0 during erasure and 1 after erasure on Q7.(Q6 is for
toggle bit; see toggle bit, DATA polling, timing waveform)

tAH

Sector

Address0

555H 2AAH 2AAH

555H 555H

Sector

Address1

Sector

Addressn

Vcc 5V

CE

OE

Q0,Q1,

Q4(Note 1)

WE

A12~A16

Q7

A0~A10

Command

In

Command InCommand

In

Command InCommand

In

Command InCommand

In

Command InCommand

In

Command InCommand InCommand InCommand

In

Command

In

Command #30HCommand #30HCommand #30HCommand #55HCommand #AAHCommand #80HCommand #55HCommand #AAH

(Q0~Q7)

Command

In

Command

In

tDH

tDS

tCEP

tCWC

tAETB

tBAL

DATA polling

tCEPH1

tAS

Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

31

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REV. 1.3 , DEC. 24, 2001

MX29F200T/B

AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data AAH Address 555H

Write Data 80H Address 555H

YES

NO

Toggle Bit Checking

Q6 not Toggled

Write Data 30H Sector Address

Write Data 55H Address 2AAH

Reset

Auto Sector Erase Exceed
Timing Limit

DATA Polling

Q7 = 1

Q5 = 1

Auto Sector Erase Completed

Load Other Sector Addrss If Necessary
(Load Other Sector Address)

YES

NO

Last Sector
to Erase

Time-out Bit

Checking Q3=1 ?

Toggle Bit Checking

Q6 T oggled ?

Invalid Command

NO

YES

YES

NO

YES

NO

.

32

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

MX29F200T/B

ERASE SUSPEND/ERASE RESUME FLOWCHART

START

Write Data B0H

Toggle Bit checking Q6

not toggled

YES

NO

Write Data 30H

Continue Erase

Reading or

Programming End

Read Array or

Program

Another

Erase Suspend ?

NO

.

YES

YES

NO

33

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REV. 1.3 , DEC. 24, 2001

MX29F200T/B

TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITH 12V

TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITH 12V

tOE

Data

OE

WE

12V

5V

12V

5V

CE

A9

A1

A6

tOESP

tWPP 1

tVLHT

tVLHT

tVLHT

Verify

01H

A16-A12 Sector Address

tOE

Data

OE

WE

12V

5V

12V

5V

CE

A9

A1

tOESP

tWPP 2

tVLHT

tVLHT

tVLHT

Verify

00H

A6

Sector Address

A16-A12

34

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

MX29F200T/B

SECTOR PROTECTION ALGORITHM FOR SYSTEM WITH 12V

START

Set Up Sector Addr

(A16,A15,A14,A13,A12)

PLSCNT=1

Sector Protection

Complete

Data=01H?

Yes

.

OE=VID,A9=VID,CE=VIL

A6=VIL

Activate WE Pulse

Time Out 10us

Set WE=VIH, CE=OE=VIL
A9 should remain VID

Read from Sector

Addr=SA, A1=1

Protect Another

Sector?

Remove VID from A9

Write Reset Command

Device Failed

PLSCNT=32?

Yes

No

No

Yes

No

35

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

MX29F200T/B

CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITH 12V

START

Protect All Sectors

PLSCNT=1

Chip Unprotect

Complete

Data=00H?

Yes

Set OE=A9=VID
CE=VIL,A6=1

Activate WE Pulse

Time Out 12ms

Set OE=CE=VIL

A9=VID,A1=1

Set Up First Sector Addr

All sectors have

been verified?

Remove VID from A9

Write Reset Command

Device Failed

PLSCNT=1000?

No

Increment

PLSCNT

No

Read Data from Device

Yes

Yes

No

Increment

Sector Addr

* It is recommended before unprotect the whole chip, all sectors should be protected in advance.

36

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

MX29F200T/B

TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITHOUT 12V

tOE

Data

OE

WE

CE

A1

A6

* See the following Note!

Verify

01H

A16-A12 Sector Address

5V

Note1: Must issue "unlock for sector protect/unprotect" command before sector protection
for a system without 12V provided.

Note2: Except F0H

Toggle bit polling

Don't care

(Note 2)

tCEP

F0H

37

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

MX29F200T/B

TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITHOUT 12V

tOE

Data

WE

CE

A1

Verify

00H

A6

Note1: Must issue "unlock for sector protect/unprotect" command before sector unprotection
for a system without 12V provided.

OE

tCEP

5V

Toggle bit polling

Don't care

(Note 2)

* See the following Note!

F0H

Note2: Except F0H

38

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

MX29F200T/B

SECTOR PROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V

START

Set Up Sector Addr

(A16,A15,A14,A13,A12)

PLSCNT=1

Sector Protection

Complete

Data=01H?

Yes

.

OE=VIH,A9=VIH

CE=VIL,A6=VIL

Activate WE Pulse to start

Data don't care

Set CE=OE=VIL

A9=VIH

Read from Sector

Addr=SA, A1=1

Protect Another

Sector?

Write Reset Command

Device Failed

PLSCNT=32?

Yes

No

Increment PLSCNT

No

Write "unlock for sector protect/unprotect"

Command(Table1)

Toggle bit checking

DQ6 not Toggled

No

Yes

Yes

No

39

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

MX29F200T/B

SECTOR UNPROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V

START

Protect All Sectors

PLSCNT=1

Chip Unprotect

Complete

Data=00H?

Yes

Set OE=A9=VIH
CE=VIL,A6=1

Activate WE Pulse to start

Data don't care

Set OE=CE=VIL

A9=VIH,A1=1

Set Up First Sector Addr

All sectors have

been verified?

Write Reset Command

Device Failed

PLSCNT=1000?

No

Increment

PLSCNT

No

Read Data from Device

Yes

Yes

No

Increment

Sector Addr

* It is recommended before unprotect the whole chip, all sectors should be protected in advance.

Write "unlock for sector protect/unprotect"

Command (Table 1)

Toggle bit checking

DQ6 not Toggled

Yes

No

40

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

MX29F200T/B

ID CODE READ TIMING WAVEFORM

tACC

tCE

tACC

tOE

tOH

tOH

tDF

DATA OUT

C2H/00C2H

51H/57H (Byte mode)
2251H/2257H (Word mode)

VID
VIH

VIL

ADD

A9

ADD

A2-A8

A10-A17

CE

OE

WE

A1

DATA OUT

DATA

Q0-Q15

VCC

5V

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

41

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

MX29F200T/B

LIMITS

PARAMETER MIN. TYP.(2) MAX.(3) UNITS

Sector Erase Time 1 8 s
Chip Erase Time 3 2 4 s
Byte Programming Time 7 21 0 us
Word Programming Time 12 36 0 u s
Chip Programming Time 3.5 10.5 sec
Erase/Program Cycles 100,000 Cycles

MIN. MAX.

Input Voltage with respect to GND on all pins except I/O pins -1.0V 13.5V
Input Voltage with respect to GND on all I/O pins -1.0V Vcc + 1.0V
Current -100mA +100mA
Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.

LATCHUP CHARACTERISTICS

ERASE AND PROGRAMMING PERFORMANCE(1)

Note: 1.Not 100% Tested, Excludes external system level over head.

2.Typical values measured at 25°C,5V.

3.Maximum values measured at 25°C,4.5V.

PARAMETER MIN. UNIT

Data Retention Time 20 Years

DATA RETENTION

42

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

MX29F200T/B

PLASTIC PACKAGE

PART NO. Access Time Operating Current Standby Current Temperature PACKAGE

(ns) (mA) MAX.(uA) Range

MX29F200TMC-55 55 40 5 0oC~70oC 44 Pin SOP
MX29F200TMC-70 7 0 4 0 5 0oC~70oC 44 Pin SOP
MX29F200TMC-90 9 0 4 0 5 0oC~70oC 44 Pin SOP
MX29F200TMC-12 1 2 0 40 5 0oC~70oC 44 Pin SOP
MX29F200TTC-55 55 40 5 0oC~70oC 48 Pin TSOP

(Normal Type)

MX29F200TTC-70 7 0 40 5 0oC~70oC 48 Pin TSOP

(Normal Type)

MX29F200TTC-90 9 0 40 5 0oC~70oC 48 Pin TSOP

(Normal Type)

MX29F200TTC-12 120 4 0 5 0oC~70oC 48 Pin TSOP

(Normal Type)
MX29F200BMC-55 5 5 40 5 0oC~70oC 44 Pin SOP
MX29F200BMC-70 7 0 40 5 0oC~70oC 44 Pin SOP
MX29F200BMC-90 9 0 40 5 0oC~70oC 44 Pin SOP
MX29F200BMC-12 120 40 5 0oC~70oC 44 Pin SOP
MX29F200BTC-55 55 40 5 0oC~70oC 48 Pin TSOP

(Normal Type)
MX29F200BTC-70 70 40 5 0oC~70oC 48 Pin TSOP

(Normal Type)
MX29F200BTC-90 90 40 5 0oC~70oC 48 Pin TSOP

(Normal Type)
MX29F200BTC-12 120 4 0 5 0oC~70oC 48 Pin TSOP

(Normal Type)
MX29F200TMI-70 7 0 45 5 -40oC~85oC 44 Pin SOP
MX29F200TMI-90 90 45 5 - 4 0oC~85oC 44 Pin SOP
MX29F200TMI-12 12 0 45 5 -40oC~85oC 44 Pin SOP
MX29F200TTI-70 70 45 5 -40oC~85oC 48 Pin TSOP

(Normal Type)
MX29F200TTI-90 9 0 45 5 -40oC~85oC 48 Pin TSOP

(Normal Type)
MX29F200TTI-12 12 0 45 5 - 40oC~85oC 48 Pin TSOP

(Normal Type)
MX29F200BMI-70 70 45 5 -40oC~85oC 44 Pin SOP
MX29F200BMI-90 90 45 5 -40oC~85oC 44 Pin SOP
MX29F200BMI-12 12 0 45 5 -40oC~85oC 44 Pin SOP
MX29F200BTI-70 70 45 5 -40oC~85oC 48 Pin TSOP

(Normal Type)
MX29F200BTI-90 90 45 5 -40oC~85oC 48 Pin TSOP

(Normal Type)
MX29F200BTI-12 1 20 45 5 -40oC~85oC 48 Pin TSOP

(Normal Type)
MX29F200TTA-90 90 4 5 2 0 -40oC~125oC 48 Pin TSOP

(Normal Type)
MX29F200TTA-12 120 45 20 -40oC~125oC 48 Pin TSOP

(Normal Type)

ORDERING INFORMATION

43

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

MX29F200T/B

PACKAGE INFORMATION

48-PIN PLASTIC TSOP

44

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

MX29F200T/B

44-PIN PLASTIC SOP

45

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

MX29F200T/B

REVISION HISTORY

Revision Description Page Date

1.0 1.To remove "Advanced Information" datasheet marking and P1 DEC/20/1999

contain information on products in full production

2.The modification summary of Revision 0.9.9 to Revision 1.0:
2-1.Program/erase cycle times:10K cycles-->100K cycles P1,42
2-2.To add data retention 20 years P1,42
2-3.Industrial grade range from "Read Mode" to "Full Range" P20,21,22,40
2-4.To remove A9 from "timing waveform for sector protection for P35
system without 12V"
To remove A9 from "timing waveform for chip unprotection for P3 6
system without 12V"

1.1 To modify "Package Information" P42,43 JUN/15/2001

1.2 Add automotive Grade P18,19,21,41 NOV/12/2001

1.3 Correct sector address SA2 from 11XXX to 10XXX P3 DEC/24/2001

MX29F200T/B

MACRONIX INTERNATIONAL CO., LTD.

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MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.