Datasheet MX29F080TC-12, MX29F080TC-70, MX29F080TC-90, MX29F080MC-12, MX29F080MC-70 Datasheet (MXIC)

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FEA TURES

PRELIMINARY

MX29F080

8M-BIT [1024K x 8] CMOS EQUAL SECTOR FLASH MEMORY

• 1,048,576 x 8 byte mode only stuction

• Single power supply operation

- 5.0V only operation for read, erase and program operation

• Fast access time: 70/90/120ns

• Low power consumption

- 30mA maximum active current

- 0.2uA typical standby current

• Command register architecture

- Byte Programming (7us typical)

- Sector Erase of 16 equal sector with 64K-Byte each

• Auto Erase (chip & sector) and Auto Program

- Automatically erase any combination of sectors with Erase Suspend capability .

- Automatically program and verify data at specified address

• Erase suspend/Erase Resume

- Suspends sector erase operation to read data from, or program data to, another sector that is not being erased, then resumes the erase.

• Status Reply

- Data polling & Toggle bit for detection of program

and erase operation completion.

• Ready/Busy (RY/BY)

- Provides a hardware methed of detecting program and erase operation complation.

• Sector Group protect/chip unprotect for 5V/12V system.

• Sector Group protection

- Hardware protect method for each group which consists of two adjacent sectors

- Temporary sector group unprotect allows code changes in previously locked sectors

• 10,000 minimum erase/program cycles

• Latch-up protected to 100mA from -1V to VCC+1V

• Low VCC write inhibit is equal to or less than 3.2V

• Package type:

- 40-pin TSOP or 44-pin SOP

• Compatibility with JEDEC standard

- Pinout and software compatible with single-power supply Flash

GENERAL DESCRIPTION

The MX29F080 is a 8-mega bit Flash memory organized as 1024K bytes of 8 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29F080 is packaged in 40-pin TSOP or 44-pin SOP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers.

The standard MX29F080 offers access time as fast as 70ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX29F080 has separate chip enable (CE) and output enable (OE ) controls.

MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29F080 uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels

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during erase and programming, while maintaining maximum EPROM compatibility.

MXIC Flash technology reliably stores memory contents even after 10,000 erase and program cycles. The MXIC cell is designed to optimize the erase and program mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The MX29F080 uses a 5.0V±10% VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms.

The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.

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PIN CONFIGURATIONS

MX29F080

40 TSOP (Standard Type) (10mm x 20mm)

A19

A18

A17

A16

A15

A14

A13

A12

VCC

RESET

A11 A10

12 13 14 15

MX29F080

44 SOP

VCC

RESET

A11 A10

NC NC

Q0 Q1 Q2

Q3 VSS VSS

2 3 4 5

11 12 13

17 18 19 20 21 22

44 43 42 41 40 39 38 37 36 35 34 33 32

MX29F080

31 30 29 28 27 26 25 24 23

CE A12 A13 A14 A15 A16 A17 A18 A19 NC NC NC NC WE OE RY/BY Q7 Q6 Q5 Q4 VCC

LOGIC SYMBOL

RY/BY

VCC

VSS

A0-A19

CE OE WE RESET

Q0-Q7

RY/BY

PIN DESCRIPTION

SYMBOL PIN NAME

A0~A19 Address Input Q0~Q7 8 Data Inputs/Outputs CE Chip Enable Input WE Write Enable Input OE Output Enable Input RESET Hardware Reset Pin, Active Low RY/BY Read/Busy Output VC C +5.0V single power supply VSS Device Ground N C Pin Not Connected Internally

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MX29F080

SECTOR STRUCTURE

MX29F080 SECTOR ADDRESS T ABLE

Sector Group Sector A1 9 A1 8 A17 A16 Address Range

SGA0 SA0 0000 000000h-00FFFFh SGA0 SA1 0001 010000h-01FFFFh SGA1 SA2 0010 020000h-02FFFFh SGA1 SA3 0011 030000h-03FFFFh SGA2 SA4 0100 040000h-04FFFFh SGA2 SA5 0101 050000h-05FFFFh SGA3 SA6 0110 060000h-06FFFFh SGA3 SA7 0111 070000h-07FFFFh SGA4 SA8 1000 080000h-08FFFFh SGA4 SA9 1001 090000h-09FFFFh SGA5 SA10 1010 0A0000h-0AFFFFh SGA5 SA11 1011 0B0000h-0BFFFFh SGA6 SA12 1100 0C0000h-0CFFFFh SGA6 SA13 1101 0D0000h-0DFFFFh SGA7 SA14 1110 0E0000h-0EFFFFh SGA7 SA15 1111 0F0000h-0FFFFFh

Legend:SA=Sector Address ; SGA=Sector Group Addres Note:All sectors are 64 Kbytes in size.

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BLOCK DIAGRAM

CE OE WE

CONTROL INPUT

LOGIC

PROGRAM/ERASE

HIGH VOLT A GE

MX29F080

WRITE

STATE

MACHINE

(WSM)

A0-A19

ADDRESS

LA TCH

AND

BUFFER

X-DECODER

MX29F080

FLASH ARRA Y

Y-DECODER

Y-PASS GATE

SENSE

AMPLIFIER

STATE

ARRAY

SOURCE

COMMAND

DATA DECODER

PGM

DATA

COMMAND DATA LATCH

PROGRAM

DATA LATCH

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Q0-Q7

I/O BUFFER

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MX29F080

AUTOMATIC PROGRAMMING

The MX29F080 is byte programmable using the Automatic Programming algorithm. The Automatic Progr amming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. The typical chip programming time at room temperature of the MX29F080 is less than 8 seconds.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase pulses according to MXIC's Automatic Chip Erase algorithm. T ypical erasure at room temper ature is accomplished in less than 8 seconds. The Automatic Erase algorithm automatically programs the entire array prior to electrical erase. The timing and v erification of electrical erase are controlled internally within the device.

AUTOMATIC SECTOR ERASE

The MX29F080 is sector(s) erasable using MXIC's Auto Sector Erase algorithm. Sector erase modes allow sectors of the array to be erased in one erase cycle. The Automatic Sector Erase algorithm automatically programs the specified sector(s) prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm require the user to only write program set-up commands (including 2 unlock write cycle and A0H) and a program command (program data and address). The de vice automatically times the programming pulse width, provides the program verification, and counts the number of sequences. A status bit similar to DATA polling and a status bit toggling between consecutive read cycles, provide feedback to the user as to the status of the programming operation.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to write commands to the command register using standard microprocessor write timings. The de vice will automatically pre-program and verify the entire arra y. Then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. A status bit toggling between consecutive read cycles provides feedback to the user as to the status of the programming operation.

Register contents serve as inputs to an internal statemachine which controls the erase and programming circuitry . During write cycles, the command register internally latches address and data needed for the programming and erase operations. During a system write cycle, addresses are latched on the falling edge, and data are latched on the rising edge of WE or CE, whichev er happens first .

MXIC's Flash technology combines years of EPROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The MX29F080 electrically erases all bits simultaneously using Fowler-Nordheim tunneling. The bytes are programmed by using the EPROM programming mechanism of hot electron injection.

During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. During a Sector Erase cycle, the command register will only respond to Erase Suspend command. After Erase Suspend is completed, the device stays in read mode. After the state machine has completed its task, it will allow the command register to respond to its full command set.

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MX29F080

T ABLE1. SOFTW ARE COMMAND DEFINITIONS

First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus

Command Bus Cycle Cycle Cycle Cycle Cycle Cycle

Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Reset 1 XXXH F0H Read 1 RA RD Read Silicon ID 4 555H AAH 2AAH 55H 555H 90H ADI DDI Sector Group 4 555H AAH 2AAH 55H 555H 90H SGAx02 0 0 H Protect Verify 01H Porgram 4 555H AAH 2AAH 55H 555H A0H PA PD Chip Erase 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H Sector Erase 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H Sector Erase Suspend 1 XXXH B 0H Sector Erase Resume 1 XXXH 30 H

Note:

1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacture code,A1=0, A0 = 1 for device code. A2-A19=do not care. (Refer to Table 3)

DDI = Data of Device identifier : C2H for manufacture code, D5H for device code. X = X can be VIL or VIH RA=Address of memory location to be read. RD=Data to be read at location RA.

2.PA = Address of memory location to be programmed.

PD = Data to be programmed at location PA. SA = Address of the sector to be erased. Address A16-A19 select a unigue sector.

SGA=Address of the sector group. Address A17~A19 select a unigue sector group.

3.The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 . Address bit A11~A19=X=Don't care for all address commands except f or Program Address (PA) and Sector Address (SA). Write Sequence may be initiated with A11~A19 in either state .

4.For Sector Group Protect V erify Operation : If read out data is 01H, it means the sector has been protected.If read out data is 00H,it means the sector is still not being protected.

COMMAND DEFINITIONS

Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table 1 defines the valid register command sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Either of the two reset command sequences will reset the device(when applicable).

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MX29F080

T ABLE 2. MX29F080 BUS OPERATION

Pins Mode CE OE WE A0 A1 A6 A9 Q0 ~ Q 7 Read Silicon ID L L H L L X VID(2) C2H Manfacturer Code(1) Read Silicon ID L L H H L X VID(2) D5H Device Code(1) Read L L H A0 A1 A6 A9 D Standby H X X X X X X HIGH Z Output Disable L H H X X X X HIGH Z Write L H L A0 A1 A 6 A9 DIN(3) Sector Group Protect (6) L VID(2) L X X L VID(2) X Chip Unprotect(6) L VID(2) L X X H VID(2) X Verify Sector Protect L L H X H X VID(2) Code(5) Reset X X X X X X X HIGH Z

OUT

NOTES:

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.

2. VID is the Silicon-ID-Read high voltage, 11.5V to 13V.

3. Refer to Table 1 for valid Data-In during a write operation.

4. X can be VIL or VIH.

5. Code=00H means unprotected.

Code=01H means protected.

6. A19~A17=Sector group address for sector group protect.

Refer to sector group protect/chip unprotect algorithm and waveform.

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MX29F080

READ/RESET COMMAND

The read or reset operation is initiated by writing the read/reset command sequence into the command register. Microprocessor read cycles retr ieve array data. The device remains enabled for reads until the command register contents are altered.

If program-fail or erase-fail happen, the write of F0H will reset the device to abort the operation. A valid command must then be written to place the device in the desired state.

SILICON-ID-READ COMMAND

Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacturer and device codes must be accessible while the device resides in the target system. PROM programmers typically access signature codes by raising A9 to a high voltage. Howe ver , multiplexing high voltage onto address lines is not generally desired system design practice.

The MX29F080 contains a Silicon-ID-Read operation to supplement traditional PROM programming methodology . The operation is initiated b y writing the read silicon ID command sequence into the command register. Following the command write, a read cycle with A1=VIL,A0=VIL retrieves the manufacturer code of C2H. A read cycle with A1=VIL, A0=VIH returns the device code of D5H for MX29F080.

SET-UP AUTOMATIC CHIP/SECTOR ERASE

Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are f ollowed b y writing the "set-up" command 80H. Two more "unlock" write cycles are then followed by the chip erase command 10H.

The Automatic Chip Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Chip Erase. Upon executing the Automatic Chip Erase, the device will automatically program and verify the entire memory for an all-zero data pattern. When the device is automatically verified to contain an all-zero pattern, a self-timed chip erase and verify begin. The erase and verify operations are completed when the data on Q7 is "1" at which time the device returns to the Read mode. The system is not required to provide an y control or timing during these operations.

When using the Automatic Chip Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array(no erase verification command is required).

If the Erase operation was unsuccessful, the data on Q5 is "1"(see Table 4), indicating the erase operation exceed internal timing limit.

The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mode.

T ABLE 3. EXPANDED SILICON ID CODE

Pins A0 A1 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code(Hex) Manufacture code VIL VIL 11000010C2H Device code for MX29F080 VIH VIL 11010101D5H

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SECTOR ERASE COMMANDS

MX29F080

The Automatic Sector Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Set-up Sector Erase command and Automatic Sector Erase command. Upon executing the Automatic Sector Erase command, the device will automatically program and verify the sector(s) memory for an all-zero data pattern. The system is not required to provide any control or timing during these operations.

When the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verify begin. The erase and verify operations are complete when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations.

When using the Automatic Sector Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the

memory array (no erase verification command is required). Sector erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the set-up command 80H. Two more "unlock" write cycles are then followed by the sector erase command 30H. The sector address is latched on the falling edge of WE or CE, whichever happens later , while the command(data) is latched on the rising edge of WE o r CE, whichever happens first. Sector addresses selected are loaded into internal register on the sixth falling edge of WE or CE, whichever happens later. Each successive sector load cycle started by the falling edge of WE or CE, whichever happens later must begin within 80us from the rising edge of the preceding WE or CE, whichever happens first. Otherwise, the loading period ends and internal auto sector erase cycle starts. (Monitor Q3 to determine if the sector erase timer window is still open, see section Q3, Sector Erase Timer.) Any command other than Sector Erase(30H) or Erase Suspend(B0H) during the time-out period resets the device to read mode.

T able 4. Write Operation Status

Status Q7 Q6 Q5 Q3 Q2

Byte Program in Auto Program Algorithm Q7 Toggle 0 0 1 Auto Erase Algorithm 0 Toggle 0 1 Toggle

Erase Suspend Read 1 1 0 0 Toggle

In Progress (Erase Suspended Sector) (Note1)

Erase Suspended Mode Erase Suspend Read Data Data Data Data Data

(Non-Erase Suspended Sector) Erase Suspend Program Q7 Toggle 0 0 1 (Non-Erase Suspended Sector) (Note2) (Note3)

Byte Program in Auto Program Algorithm Q7 Toggle 1 0 1 Exceeded Program/Erase in Auto Erase Algorithm 0 Toggle 1 1 N/A Time Limits Erase Suspended Mode Erase Suspend Program Q7 Toggle 1 0 N/A

(Non-Erase Suspended Sector)

Notes:

1.Performing successive read operations from the erase-suspended sector will cause Q2 to toggle.

2.Performing successive read operations from any address will cause Q6 to toggle.

3.Reading the byte address being programmed while in the erase-suspend program mode will indicate logic "1" at the Q2 bit. However, successive reads from the erase-suspended sector will cause Q2 to toggle.

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MX29F080

ERASE SUSPEND

This command only has meaning while the state machine is executing Automatic Sector Erase operation, and therefore will only be responded during Automatic Sector Erase operation. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 100us to suspend the erase operations. However , When the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After this command has been executed, the command register will initiate erase suspend mode. The state machine will return to read mode automatically after suspend is ready . At this time, state machine only allows the command register to respond to the Read Memory Array, Erase Resume and program commands.

The system can determine the status of the program operation using the Q7 or Q6 status bits, just as in the standard program operation. After an erase-suspend program operation is complete, the system can once again read array data within non-suspended sector .

ERASE RESUME

This command will cause the command register to clear the suspend state and return back to Sector Erase mode but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in all other conditions.Another Erase Suspend command can be written after the chip has resumed erasing.

SET-UP AUTOMATIC PROGRAM

COMMANDS

required to provide further controls or timings. The device will automatically provide an adequate internally generated program pulse and verify margin.

If the program opetation was unsuccessful, the data on Q5 is "1"(see Table 4), indicating the program operation exceed internal timing limit. The automatic programming operation is completed when the data read on Q6 stops toggling for two consecutive read cycles and the data on Q7 and Q6 are equivalent to data written to these two bits, at which time the device returns to the Read mode(no program verify command is required).

DATA POLLING-Q7

The MX29F080 also features Data P olling as a method to indicate to the host system that the Automatic Program or Erase algorithms are either in progress or completed.

While the Automatic Programming algorithm is in operation, an attempt to read the device will produce the complement data of the data last written to Q7. Upon completion of the Automatic Program Algorithm an attempt to read the device will produce the true data last written to Q7. The Data P olling f eature is valid after the rising edge of the fourth WE or CE, whichever happens first, of the four write pulse sequences for automatic program.

While the Automatic Erase algorithm is in operation, Q7 will read "0" until the erase operation is competed. Upon completion of the erase operation, the data on Q7 will read "1". The Data P olling feature is valid after the rising edge of the sixth WE or CE, whiche ver happens first, of six write pulse sequences for automatic chip/sector erase.

T o initiate Automatic Progr am mode, A three-cycle command sequence is required. There are two "unlock" write cycles. These are follow ed by writing the Automatic Program command A0H.

Once the Automatic Program command is initiated, the next WE pulse causes a transition to an active programming operation. Addresses are latched on the falling edge, and data are internally latched on the rising edge of the WE or CE, whichever happens first pulse. The rising edge of WE or CE, whichever happens first also begins the programming operation. The system is not

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The Data Polling feature is activ e during Automatic Program/Erase algorithm or sector erase time-out.(see section Q3 Sector Erase Timer)

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Q6:Toggle BIT I

Toggle Bit I on Q6 indicates whether an Automatic Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE or CE, whichever happens first pulse in the command sequence(prior to the program or erase operation), and during the sector time-out.

During an Automatic Program or Erase algorithm operation, successive read cycles to any address cause Q6 to toggle. The system may use either OE or CE to control the read cycles. When the operation is complete, Q6 stops toggling.

After an erase command sequence is written, if all sectors selected for erasing are protected, Q6 toggles and returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.

MX29F080

Q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE or CE to control the read cycles.) But Q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. Q6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sectors and mode information. Refer to Table 4 to compare outputs for Q2 and Q6.

Reading Toggle Bits Q6/ Q2

Whenever the system initially begins reading toggle bit status, it must read Q7-Q0 at least twice in a row to determine whether a toggle bit is toggling. T ypically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on Q7-Q0 on the following read cycle.

The system can use Q6 and Q2 together to determine whether a sector is actively erasing or is erase suspended. When the de vice is actively erasing (that is, the Automatic Erase algorithm is in progress), Q6 toggling. When the device enters the Erase Suspend mode, Q6 stops toggling. However, the system must also use Q2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use Q7.

If a program address falls within a protected sector , Q6 toggles for approximately 2us after the program command sequence is written, then returns to reading array data.

Q6 also toggles during the erase-suspend-program mode, and stops toggling once the Automatic Program algorithm is complete.

Table 4 shows the outputs for Toggle Bit I on Q6.

Q2:Toggle Bit II

The "T oggle Bit II" on Q2, when used with Q6, indicates whether a particular sector is actively eraseing (that is, the Automatic Erase alorithm is in process), or whether that sector is erase-suspended. T oggle Bit I is v alid after the rising edge of the final WE or CE, whichev er happens first pulse in the command sequence.

However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of Q5 is high (see the section on Q5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as Q5 went high. If the toggle bit is no longer toggling, the device has successfuly completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data.

The remaining scenario is that system initially determines that the toggle bit is toggling and Q5 has not gone high. The system may continue to monitor the toggle bit and Q5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively , it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation.

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MX29F080

Q5 Exceeded Timing Limits

Q5 will indicate if the program or erase time has exceeded the specified limits(internal pulse count). Under these conditions Q5 will produce a "1". This time-out condition indicates that the program or erase cycle was not successfully completed. Data P olling and T oggle Bit are the only operating functions of the device under this condition.

If this time-out condition occurs during sector erase operation, it specifies that a particular sector is bad and it may not be reused. Howe ver , other sectors are still functional and may be used for the program or erase operation. The device must be reset to use other sectors. Write the Reset command sequence to the device, and then execute prog ram or erase command sequence. This allows the system to continue to use the other active sectors in the device.

If this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination of sectors are bad.

If this time-out condition occurs during the byte programming operation, it specifies that the entire sector containing that byte is bad and this sector maynot be reused, (other sectors are still functional and can be reused).

The time-out condition may also appear if a user tries to program a non blank location without erasing. In this case the device locks out and never completes the Automatic Algorithm operation. Hence, the system never reads a valid data on Q7 bit and Q6 never stops toggling. Once the Device has exceeded timing limits, the Q5 bit will indicate a "1". Please note that this is not a device failure condition since the device was incorrectly used.

TEMPORARY SECT OR GROUP UNPRO TECT

This feature allows temporary unprotection of previously protected sector group to change data in-system. The T emporary Sector group Unprotect mode is activated b y setting the RESET pin to VID(11.5V -12.5V). During this mode, formerly protected sectors can be programmed or erased as un-protected sector . Once VID is remove from the RESET pin,all the previously protected sector groups are protected again.

Q3 Sector Erase Timer

After the completion of the initial sector erase command sequence, the sector erase time-out will begin. Q3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase command sequence.

If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, Q3 may be used to determine if the sector erase timer window is still open. If Q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or T oggle Bit. If Q3 is low ("0"), the de vice will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of Q3 prior to and following each subsequent sector erase command. If Q3 were high on the second status check, the command may not have been accepted.

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns(typical) on CE or WE will not initiate a write cycle.

DATA PROTECTION

The MX29F080 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The de vice also incorporates several features to prevent inadvertent write cycles resulting from VCC pow er-up and power-down transition or system noise.

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LOGICAL INHIBIT

Writing is inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a wr ite cycle CE and WE must be a logical zero while OE is a logical one.

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MX29F080

POWER SUPPLY DECOUPLING

In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected between its VCC and GND .

SECTOR GROUP PROTECTION

The MX29F080 features hardware sector group protection. This feature will disable both program and erase operations for these group sector protected. To activate this mode, the programming equipment must f orce VID on address pin A9 and control pin OE, (suggest VID = 12V) A6 = VIL and CE = VIL.(see T able 2) Prog ramming of the protection circuitry begins on the falling edge of the WE or CE, whichever happens later pulse and is terminated on the rising edge. Please refer to group sector protect algorithm and waveform.

T o v erify programming of the protection circuitry, the programming equipment must force VID on address pin A9 ( with CE and OE at VIL and WE at VIH). When A1=1, it will produce a logical "1" code at device output Q0 for a protected sector. Otherwise the de vice will produce 00H for the unprotected sector . In this mode , the addresses, except for A1, are don't care. Address locations with A1 = VIL are reserved to read manufacturer and device codes.(Read Silicon ID)

It is also possible to determine if the chip is unprotected in the system by writing the Read Silicon ID command. Perf orming a read operation with A1=VIH, it will produce 00H at data outputs(Q0-Q7) for an unprotected sector . It is noted that all sectors are unprotected after the chip unprotect algorithm is completed.

POWER-UP SEQUENCE

The MX29F080 powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of the predefined command sequences.

It is also possible to determine if the group is protected in the system by writing a Read Silicon ID command. Perf orming a read operation with A1=VIH, it will produce a logical "1" at Q0 for the protected sector .

CHIP UNPROTECT

The MX29F080 also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code. It is recommended to protect all sectors before activating chip unprotect mode.

T o activ ate this mode, the programming equipment must force VID on control pin OE and address pin A9. The CE pins must be set at VIL. Pins A6 must be set to VIH.(see T able 2) Ref er to chip unprotect algorithm and wavef orm for the chip unprotect algorithm. The unprotection mechanism begins on the falling edge of the WE or CE, whichever happens laster pulse and is terminated on the rising edge.

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Page 14

MX29F080

CAPACITANCE (TA = 25oC, f = 1.0 MHz)

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS

CIN1 Input Capacitance 8 pF VIN = 0V CIN2 Control Pin Capacitance 12 pF VIN = 0V COUT Output Capacitance 12 pF VOUT = 0V

READ OPERATION

DC CHARACTERISTICS (TA = 0°C T O 70°C, VCC = 5V

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS

ILI Input Leakage Current ± 1 uA VIN = GND to VCC ILO Output Leakage Current ± 1 uA VOUT = GND to VCC ISB1 Standby VCC current 1 mA CE = VIH ISB2 0.2 5 uA CE = VCC + 0.3V ICC1 Operating VCC current 30 mA IOUT = 0mA, f=1MHz ICC2 50 mA IOUT = 0mA, f=10MHz VIL Input Low Voltage -0.3(NOTE 1) 0.8 V VIH Input High Voltage 2. 0 VCC + 0.3 V VOL Output Low Voltage 0.45 V IOL = 2.1mA VOH1 Output High Voltage(TTL) 2.4 V IOH = -2mA VOH2 Output High Voltage(CMOS) VCC-0.4 V IOH = -100uA,

NOTES:

1. VIL min. = -1.0V for pulse width < 50 ns. VIL min. = -2.0V for pulse width < 20 ns.

±±

±10%)

±±

VCC=VCC MIN

2. VIH max. = VCC + 1.5V for pulse width < 20 ns. If VIH is over the specified maximum value, read operation cannot be guaranteed.

AC CHARA CTERISTICS (T A = 0oC to 70oC, VCC = 5V

29F080-70* 29F080-90 29F080-12

SYMBOL PARAMETER MIN. MAX. MIN. MAX. MIN. MAX. UNIT CONDITIONS

tACC Address to Output Delay 70 9 0 12 0 ns CE=OE=VIL tCE CE to Output Delay 70 9 0 120 ns OE=VIL tOE OE to Output Delay 40 40 50 ns CE=VIL tDF OE High to Output Float (Note1) 0 20 0 30 0 30 ns CE=VIL tOH Address to Output hold 0 0 0 ns CE=OE=VIL

TEST CONDITIONS:

• Input pulse levels: 0.45V/2.4V*

• Input rise and fall times is equal to or less than 0ns

• Output load: 1 TTL gate + 100pF* (Including scope and jig)

• Reference levels for measuring timing: 0.8V, 2.0V

P/N:PM0579

±±

±10%)

±±

NOTE:

1. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven.

* For -70, the input levels : 0.0/3.0V, the output load : 1TTL

gate+30pF (including scope and jig)

REV. 1.4, JAN. 16, 2002

Page 15

ABSOLUTE MAXIMUM RATINGS

MX29F080

RATING VALUE

Ambient Operating Temperature 0oC to 70oC Storage Temperature -65oC to 125oC Applied Input Voltage -0.5V to 7.0V Applied Output Voltage -0.5V to 7.0V VCC to Ground Potential -0.5V to 7.0V A9 & OE -0.5V to 13.5V

READ TIMING WAVEFORMS

Addresses

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

NOTICE:

Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability.

NOTICE:

Specifications contained within the following tables are subject to change.

ADD Valid

tCE

tOE

tACC

tDF

tOH

HIGH Z HIGH Z

Outputs

VOH

VOL

DATA V alid

COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION

DC CHARACTERISTICS (T A = 0oC to 70oC, VCC = 5V

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS

ICC1 (Read) Operating VCC Current 30 mA IOUT=0mA, f=1MHz ICC2 50 mA IOUT=0mA, F=10MHz ICC3 (Program) 50 mA In Programming ICC4 (Erase) 50 mA In Erase ICCES VCC Erase Suspend Current 2 mA CE=VIH, Erase Suspended

NOTES:

1. VIL min. = -0.6V for pulse width is equal to or less than 20ns.

2. If VIH is over the specified maximum value, programming operation cannot be guranteed.

3. ICCES is specified with the device de-selected. If the

±±

±10%)

±±

device is read during erase suspend mode, current draw is the sum of ICCES and ICC1 or ICC2.

4. All current are in RMS unless otherwise noted.

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Page 16

MX29F080

AC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V

±±

± 10%

±±

29F080-70 29F080-90 29F080-12

SYMBOL PARAMETER MIN. MAX. MIN. MAX. MIN. MAX. UNIT

tOES OE setup time 50 50 50 ns tCWC Command programming cycle 70 90 120 ns tCEP WE programming pulse width 35 45 50 ns tCEPH1 WE programming pluse width High 20 20 20 n s tCEPH2 WE programming pluse width High 20 20 20 n s tAS Address setup time 0 0 0 ns tAH Address hold time 45 45 50 ns tDS Data setup time 30 4 5 50 n s tDH Data hold time 0 0 0 ns tCESC CE setup time before command write 0 0 0 n s tDF Output disable time (Note 1) 20 30 30 n s tAETC Total erase time in auto chip erase 8(TYP.) 64 8(TYP.) 64 8(TYP.) 64 s tAETB Total erase time in auto sector erase 1.3(TYP.) 10.4 1.3(TYP.) 10.4 1(TYP.) 10.4 s tAVT Total programming time in auto verify 7(TYP.) 210 7(TYP.) 210 7(TYP.) 210 u s tBAL Sector address load time 80 80 80 u s tCH CE Hold Time 0 0 0 ns tCS CE setup to WE going low 0 0 0 ns tVLHT Voltge Transition Time 4 4 4 us tOESP OE Setup Time to WE Active 4 4 4 us tWPP1 Write pulse width for sector protect 10 10 10 u s tWPP2 Write pulse width for sector unprotect 1 2 12 12 m s

NOTES:

1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.

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Page 17

SWITCHING TEST CIRCUITS

MX29F080

DEVICE UNDER

TEST

SWITCHING TEST WAVEFORMS

2.4V

0.45V

AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0". Input pulse rise and fall times are <20ns.

1.6K ohm

CL=30pF Including jig capacitance for -70 grade, CL=100pF for others

1.2K ohm

DIODES=IN3064

OR EQUIVALENT

2.0V 2.0V

TEST POINTS

0.8V

INPUT

0.8V OUTPUT

+5V

COMMAND WRITE TIMING WAVEFORM

VCC

Addresses

Data

P/N:PM0579

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

tAS

tOES

tCS tCH

tCEP

tDS

ADD Valid

tAH

tCEPH1

tCWC

tDH

DIN

REV. 1.4, JAN. 16, 2002

Page 18

AUTOMATIC PROGRAMMING TIMING WAVEFORM

MX29F080

One byte data is programmed. Verify in fast algorithm and additional programming by external control are not required because these operations are executed automatically by internal control circuit. Programming completion can be verified by DATA polling and toggle

Vcc 5V

A11~A19

A0~A10

Q0,Q1,

Q4(Note 1)

tAS

555H

tAH

tCEP

tDS tDH

Command In

2AAH

tCWC

tCEPH1

bit checking after automatic verification starts. Device outputs DATA during programming and DAT A after programming on Q7.(Q6 is for toggle bit; see toggle bit, DAT A polling, timing w avef orm)

ADD Valid

555H

Command InCommand In Data In

ADD Valid

tAVT

DATA polling

tCESC

tDF

DATA

Command In Command InCommand In Data In

Command #AAH

(Q0~Q7)

Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

Command #55H

Command #A0H

DATADATA

tOE

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REV. 1.4, JAN. 16, 2002

Page 19

AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data A0H Address 555H

Write Program Data/Address

MX29F080

Invalid Command

Toggle Bit Checking Q6 not Toggled

Verify Byte Ok

Auto Program Completed

YES

Q5 = 1

YES

Reset

Auto Program Exceed Timing Limit

P/N:PM0579

REV. 1.4, JAN. 16, 2002

Page 20

AUTOMATIC CHIP ERASE TIMING WAVEFORM

MX29F080

All data in chip are erased. External erase verification is not required because data is erased automatically by internal control circuit. Erasure completion can be verified by DATA polling and toggle bit checking after

AUTOMATIC CHIP ERASE TIMING WAVEFORM

Vcc 5V

A11~A19

A0~A10

555H

2AAH

555H

tAS

tAH

automatic erase starts. Device outputs 0 during erasure and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform)

555H 2AAH

555H

tCWC

tCEPH1

tAETC

Q0,Q1,

Q4(Note 1)

tCEP

tDS tDH

Command In

Command In Command InCommand In

Command #AAH Command #55H

Command InCommand In

Command #80H

Command In

Command #AAH

(Q0~Q7)

Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

Command In

Command #55H

Command In

DATA polling

Command In

Command #10H

P/N:PM0579

REV. 1.4, JAN. 16, 2002

Page 21

AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 10H Address 555H

MX29F080

Invalid Command

Toggle Bit Checking

Q6 not Toggled

YES

DATA Polling

Q7 = 1

YES

Auto Chip Erase Completed

Q5 = 1

YES

Reset

Auto Chip Erase Exceed Timing Limit

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REV. 1.4, JAN. 16, 2002

Page 22

AUTOMATIC SECTOR ERASE TIMING WAVEFORM

MX29F080

Block data indicated by A16 to A19 are erased. External erase verify is not required because data are erased automatically by internal control circuit. Erasure completion can be verified by DATA polling and toggle bit

AUTOMATIC SECTOR ERASE TIMING WAVEFORM

Vcc 5V

A16-A19

A0~A10

555H 2AAH 2AAH

tAS

tAH

555H 555H

checking after automatic erase starts. Device outputs 0 during erasure and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform)

Sector

Address0

tCWC

tCEPH1

Sector

Address1

Sector

Addressn

tBAL

tAETB

Q0,Q1,

Q4(Note 1)

P/N:PM0579

tCEP

tDS

tDH

Command InCommand

Command

(Q0~Q7)

Command InCommand

Command InCommand InCommand InCommand

Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

Command

Command #30HCommand #30HCommand #30HCommand #55HCommand #AAHCommand #80HCommand #55HCommand #AAH

DATA polling

REV. 1.4, JAN. 16, 2002

Page 23

AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 30H Sector Address

MX29F080

Toggle Bit Checking

Q6 T oggled ?

YES

Load Other Sector Addrss If Necessary (Load Other Sector Address)

Last Sector to Erase

Time-out Bit

Checking Q3=1 ?

YES

Toggle Bit Checking

Q6 not Toggled

DATA Polling

Q7 = 1

YES

Invalid Command

Q5 = 1

P/N:PM0579

Auto Sector Erase Completed

Reset

Auto Sector Erase Exceed Timing Limit

REV. 1.4, JAN. 16, 2002

Page 24

ERASE SUSPEND/ERASE RESUME FLOWCHART

START

Write Data B0H

MX29F080

Toggle Bit checking Q6

not toggled

YES

Read Array or

Program

Reading or

Programming End

YES

Write Data 30H

Continue Erase

Another

Erase Suspend ?

YES

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REV. 1.4, JAN. 16, 2002

Page 25

TIMING WAVEFORM FOR SECTOR GROUP PROTECTION

12V

tVLHT

12V

tVLHT

tWPP 1

MX29F080

Verify

tVLHT

tOESP

Data

A19-A17 Sector Address

01H F0H

tOE

P/N:PM0579

REV. 1.4, JAN. 16, 2002

Page 26

TIMING WAVEFORM FOR CHIP UNPROTECTION

12V

tVLHT

MX29F080

12V

Data

A19-A17

tVLHT

tOESP

tWPP 2

tVLHT

Verify

00H

tOE

Sector Address

F0H

P/N:PM0579

REV. 1.4, JAN. 16, 2002

Page 27

SECTOR GROUP PROTECTION ALGORITHM

Set Up Sector Group Addr

(A19, A18, A17)

OE=VID,A9=VID,CE=VIL

Activate WE Pulse

Time Out 10us

MX29F080

START

PLSCNT=1

A6=VIL

PLSCNT=32?

Yes

Device Failed

Set WE=VIH, CE=OE=VIL A9 should remain VID

Read from Sector Group

Addr=SGA, A1=1

Data=01H?

Protect Another

Sector Group?

Remove VID from A9

Write Reset Command

Sector Group Protection

Complete

Yes

P/N:PM0579

REV. 1.4, JAN. 16, 2002

Page 28

CHIP UNPROTECTION ALGORITHM

MX29F080

START

Protect All Sectors

PLSCNT=1

Set OE=A9=VID CE=VIL,A6=1

Activate WE Pulse

Increment

Sector Addr

Set Up First Sector Addr

Read Data from Device

Remove VID from A9

Write Reset Command

Time Out 12ms

Set OE=CE=VIL

A9=VID,A1=1

Data=00H?

Yes

All sectors have

been verified?

Yes

Chip Unprotect

Complete

Increment

PLSCNT

PLSCNT=1000?

Yes

Device Failed

P/N:PM0579

* It is recommended before unprotect the whole chip, all sectors should be protected in advance.

REV. 1.4, JAN. 16, 2002

Page 29

MX29F080

AC CHARACTERISTICS

Parameter Std Description T est Setup All Speed Options Unit tREAD Y1 RESET PIN Low (During Automatic Algorithms) MAX 20 us

to Read or Write (See Note)

tREAD Y2 RESET PIN Low (NOT During Automatic MAX 50 0 ns

Algorithms) to Read or Write (See Note) tRP1 RESET Pulse Width (During Automatic Algorithms) MIN 10 us tRP2 RESET Pulse Width (NO T During Automatic Algorithms) MIN 500 ns tR H RESET High Time Before Read(See Note) MIN 0 ns tRB1 RY/BY Recov ery Time(to CE, OE go low) MIN 0 ns tRB2 RY/BY Recovery Time(to WE go low) MI N 50 ns

Note:Not 100% tested

RESET TIMING WAVFORM

RY/BY

CE, OE

RESET

RY/BY

CE, OE

tRH

tRP2

tReady2

Reset Timing NOT during Automatic Algorithms

tReady1

tRB1

tRB2

RESET

P/N:PM0579

tRP1

Reset Timing during Automatic Algorithms

REV. 1.4, JAN. 16, 2002

Page 30

MX29F080

TEMPORARY SECTOR UNPROTECT

Parameter Std. Description T est Setup AllSpeed Options Unit tVIDR VID Rise and Fall Time (See Note) M in 500 ns tRSP RESET Setup Time for Temporary Sector Unprotect Min 4 us

Note: Not 100% tested

TEMPORARY SECTOR GROUP UNPROTECT TIMING WAVEFORM

12V

RESET

RY/BY

0 or 5V

tVIDR

tRSP

Program or Erase Command Sequence

0 or 5V

tVIDR

P/N:PM0579

REV. 1.4, JAN. 16, 2002

Page 31

TEMPORTRY SECTOR GROUP UNPROTECT ALGORITH

Start

RESET = VID (Note 1)

Perform Erase or Program Operation

Operation Completed

RESET = VIH

Temporary Sector Group Unprotect Completed(Note 2)

MX29F080

Note :

1. All protected sectors are temporary unprotected. VID=11.5V~12.5V

2. All previously protected sectors are protected again.

P/N:PM0579

REV. 1.4, JAN. 16, 2002

Page 32

ID CODE READ TIMING WAVEFORM

MX29F080

VCC

ADD

A2-A8

A10-A19

DATA

Q0-Q7

VID VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

tACC

tCE

tOE

DATA OUT

C2H

tOH

tACC

tDF

tOH

DATA OUT

D5H

P/N:PM0579

REV. 1.4, JAN. 16, 2002

Page 33

MX29F080

ERASE AND PROGRAMMING PERFORMANCE(1)

LIMITS

PARAMETER MIN. TYP.(2) MAX. UNITS

Sector Erase Time 1.3 10.4 sec Chip Erase Time 8 64 sec Byte Programming Time 7 21 0 us Chip Programming Time 8 24 sec Erase/Program Cycles 10,000 Cycles

Note: 1.Not 100% Tested, Excludes external system level ov er head.

2.T ypical v alues measured at 25°C,5V.

LATCHUP CHARACTERISTICS

MIN. MAX.

Input Voltage with respect to GND on all pins except I/O pins -1.0V 13.5V Input Voltage with respect to GND on all I/O pins -1.0V Vcc + 1.0V Current -100mA +100mA Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.

P/N:PM0579

REV. 1.4, JAN. 16, 2002

Page 34

MX29F080

ORDERING INFORMATION

PLASTIC P ACKA GE

PART NO. ACCESS TIME OPERATING CURRENT STANDBY CURRENT PACKAGE

(ns) MAX.(mA) MAX. (uA)

MX29F080TC-70 70 50 5 40 Pin TSOP

(Normal Type)

MX29F080TC-90 90 50 5 40 Pin TSOP

(Normal Type)

MX29F080TC-12 1 20 50 5 40 Pin TSOP

(Normal Type) MX29F080MC-70 70 50 5 44 Pin SOP MX29F080MC-90 90 50 5 44 Pin SOP MX29F080MC-12 12 0 50 5 44 Pin SOP

P/N:PM0579

REV. 1.4, JAN. 16, 2002

Page 35

PACKAGE INFORMATION

40-PIN PLASTIC TSOP

MX29F080

P/N:PM0579

REV. 1.4, JAN. 16, 2002

Page 36

44-PIN PLASTIC SOP

MX29F080

P/N:PM0579

REV. 1.4, JAN. 16, 2002

Page 37

MX29F080

REVISION HISTORY

Revision Description Page Date

1.1 Add erase suspend ready max. 100us in ERASE SUSPEND's P10 MA Y/29/2000

section at page10

1.2 Modify Pac kage Information 40-pin TSOP P35 A UG/10/2000

1.3 To modify "Paclage Information" P35~36 JUN/18/2001

Modify "Chip Unprotection Algorithm" P28

1.4 T o modify P ackage Information--40-TSOP(10x20mm) P35 JAN/16/2002

P/N:PM0579

REV. 1.4, JAN. 16, 2002

Page 38

MX29F080

MACRONIX INTERNATIONAL CO., LTD.

HEADQUARTERS:

TEL:+886-3-578-6688 FAX:+886-3-563-2888

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MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.