Datasheet MX29F040 Datasheet (MXIC)

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FEATURES

MX29F040

4M-BIT [512KX8] CMOS EQUAL SECTOR FLASH MEMORY

• 524,288 x 8 only

• Single power supply operation

- 5.0V only operation for read, erase and program operation

• Fast access time: 55/70/90/120ns

• Low power consumption

- 30mA maximum active current(5MHz)

- 1uA typical standby current

• Command register architecture

- Byte Programming (7us typical)

- Sector Erase 8 equal sectors of 64K-Byte each

• Auto Erase (chip & sector) and Auto Program

- Automatically erase any combination of sectors with Erase Suspend capability .

- Automatically program and verify data at specified address

• Erase suspend/Erase Resume

- Suspends an erase operation to read data from, or

program data to, another sector that is not being erased, then resumes the erase.

• Status Reply

- Data polling & Toggle bit for detection of program and erase cycle completion.

• Sector protect/unprotect for 5V only system or 5V/ 12V system.

• Sector protection

- Hardware method to disable any combination of sectors from program or erase operations

• 100,000 minimum erase/program cycles

• Latch-up protected to 100mA fro m -1V to VCC+1V

• Low VCC write inhibit is equal to o r less than 3.2V

• Package type:

- 32-pin PLCC, TSOP o r PDIP

• Compatibility with JEDEC standard

- Pinout and software compatible with single-power supply Flash

• 20 years data retention

GENERAL DESCRIPTION

The MX29F040 is a 4-mega bit Flash memory organized as 512K bytes of 8 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29F040 is packaged in 32-pin PLCC, TSOP, PDIP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers.

The standard MX29F040 offers access time as fast as 55ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX29F040 has separate chip enable (CE) and output enable (OE) controls.

MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and progr amming. The MX29F040 uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels

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during erase and programming, while maintaining maximum EPROM compatibility.

MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and program mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The MX29F040 uses a 5.0V±10% VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms.

The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.

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PIN CONFIGURATIONS

MX29F040

32 PDIP

A18 A16 A15 A12

GND

A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

MX29F040

VCC

A17

A14

A13

A11

A10

32 TSOP (Standard T ype) (8mm x 20mm)

A11

A13

A14

A17

A18 A16 A15 A12

8 9 10 11 12 13

MX29F040

VCC

32 PLCC

A12

A15

A16

A18

VCCWEA17

A7 A6 A5 A4

A3 A2 A1 A0

14 17 20

A10

GND

MX29F040

Q3Q4Q5

GND

A14 A13 A8 A9

A11 OE A10 CE

PIN DESCRIPTION

SYMBOL PIN NAME

A0~A18 Address Input Q0~Q7 Data Input/Output CE Chip Enable Input WE Write Enable Input OE Output Enable Input GN D Ground Pin VC C +5.0V single power supply

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SECTOR STRUCTURE

MX29F040 SECTOR ADDRESS TABLE

Sector A18 A17 A16 Address Range

SA0 0 0 0 00000h-0FFFFh SA1 0 0 1 10000h-1FFFFh SA2 0 1 0 20000h-2FFFFh SA3 0 1 1 30000h-3FFFFh SA4 1 0 0 40000h-4FFFFh SA5 1 0 1 50000h-5FFFFh SA6 1 1 0 60000h-6FFFFh SA7 1 1 1 70000h-7FFFFh

Note: All sectors are 64 Kbytes in size.

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BLOCK DIAGRAM

CONTROL INPUT

LOGIC

PROGRAM/ERASE

HIGH VOLT A GE

MX29F040

WRITE

STATE

MACHINE

(WSM)

A0-A18

ADDRESS

LATCH

AND

BUFFER

X-DECODER

MX29F040

FLASH ARRAY

Y-DECODER

Y-PASS GATE

SENSE

AMPLIFIER

DATA LATCH

STATE

ARRAY

SOURCE

COMMAND

DATA DECODER

PGM

DATA

COMMAND

DATA LATCH

PROGRAM

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Q0-Q7

I/O BUFFER

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MX29F040

AUTOMATIC PROGRAMMING

The MX29F040 is byte programmable using the Automatic Programming algo rithm. The Auto matic Pro gramming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. The typical chip programming time at room temperature of the MX29F040 is less than 4 seconds.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase pulses according to MXIC's Automatic Chip Erase algorithm. T ypical er asure at room temperature is accomplished in less than 4 second. The A uto matic Erase algorithm automatically programs the entire array prior to electrical erase. The timing and v erification o f electrical erase are controlled internally within the device.

AUTOMATIC SECTOR ERASE

The MX29F040 is sector(s) erasable using MXIC's Auto Sector Erase algorithm. Sector erase modes allow sectors of the array to be erased in one erase cycle. The Automatic Sector Erase algorithm automatically programs the specified sector(s) prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm require the user to only write program set-up commands (including 2 unlock write cycle and A0H) and a program command (program data and address). The de vice automatically times the programming pulse width, provides the program verification, and counts the number of sequences. A status bit similar to DATA polling and a status bit toggling between consecutive read cycles, provide feedback to the user as to the status of the programming operation.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to write commands to the command register using standard microprocessor write timings. The device will automatically pre-progr am and v erify the entire arra y. Then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. A status bit toggling between consecutive read cycles provides feedback to the user as to the status of the programming operation.

Register contents serve as inputs to an internal statemachine which controls the erase and programming circuitry . During write cycles, the co mmand register internally latches address and data needed for the programming and erase operations. During a system write cycle, addresses are latched on the f alling edge o f WE o r CE, whichever happens later, and data are latched on the rising edge of WE or CE, whichever happens first.

MXIC's Flash technology combines years of EPROM experience to pro duce the highest levels o f quality, reliability , and co st effectiveness. The MX29F040 electrically erases all bits simultaneously using Fowler-Nordheim tunneling. The bytes are programmed by using the EPROM programming mechanism of hot electron injection.

During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. During a Sector Erase cycle, the command register will only respond to Erase Suspend command. After Erase Suspend is completed, the device stays in read mode. After the state machine has completed its task, it will allow the command register to respond to its full command set.

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MX29F040

TABLE 1. SOFTWARE COMMAND DEFINITIONS

First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus

Command Bus Cycle Cycle Cycle Cycle Cycle Cycle

Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Reset 1 XXXH F0H Read 1 RA RD Read Silicon ID 4 555H AAH 2AAH 55H 555H 90H ADI DDI Sector Protect Verify 4 555H AAH 2AAH 55H 555H 90H (SA)X 00H

02 01H Program 4 555H AAH 2AAH 55H 555H A0H PA PD Chip Erase 6 555H AAH 2AAH 55H 555H 8 0H 555H AAH 2AAH 55H 555H 10H Sector Erase 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30 H Sector Erase Suspend 1 XXXH B0H Sector Erase Resume 1 XXXH 30H Unlock for sector 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 20H protect/unprotect

Note: 1 . ADI = Address of Device identifier; A1=0, A0 = 0 for manufacture code,A1=0, A0 = 1 for device code A2-A18=Do

not care. (Refer to table 3) DDI = Data of Device identifier : C2H for manufacture code, A4H for device code.

X = X can be VIL or VIH

RA=Address of memory location to be read.

RD=Data to be read at location RA.

2. PA = Address of memory location to be programmed.

PD = Data to be progr ammed at location PA.

SA = Address to the sector to be erased.

3. The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 .

Address bit A11~A18=X=Don't care for all address commands except for Program Address (PA) and Sector

Address (SA). Write Sequence ma y be initiated with A11~A18 in either state.

4. For Sector Protect Verify Operation : If read out data is 01H, it means the sector has been protected. If read ou t

data is 00H, it means the sector is still not being protected.

COMMAND DEFINITIONS

Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mod e. Table 1 defines the valid register co mmand sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Either of the two reset command sequences will reset the device (when applicable).

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MX29F040

TABLE 2. MX29F040 BUS OPERATION

Mode Pins

CE O E W E A0 A1 A6 A9 Q0 ~ Q7

Read Silicon ID L L H L L X VID(2) C 2H Manufacturer Code(1) Read Silicon ID L L H H L X VID(2) A4 H Device Code(1) Read L L H A0 A1 A6 A9 D Standby H X X X X X X HIGH Z Output Disable L H H X X X X HIGH Z Write L H L A0 A1 A6 A9 DIN(3) Sector Protect with 12V L VID(2) L X X L VID(2) X system(6) Chip Unprotect with 12V L VID(2) L X X H VID(2) X system(6) Verify Sector Protect L L H X H X VID(2) Code(5) with 12V system Sector Protect without 12V L H L X X L H X system (6) Chip Unprotect without 12V L H L X X H H X system (6) Verify Sector Protect/Unprotect L L H X H X H Code(5) without 12V system (7) Reset X X X X X X X HIGH Z

OUT

NOTES:

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.

2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.

3. Refer to Table 1 for valid Data-In during a write operation.

4. X can be VIL or VIH.

5. Code=00H means unprotected. Code=01H means protected. A18~A16=Sector address for sector protect.

6. Refer to sector protect/unprotect algorithm and waveform. Must issue "unlock for sector protect/unprotect" command before "sector protect/unprotect without 12V system" command.

7. The "verify sector protect/unprotect without 12V system" is only following "Sector protect/unprotect without 12V system"

command.

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MX29F040

READ/RESET COMMAND

The read or reset operation is initiated by writing the read/reset command sequence into the command register. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the command register contents are altered.

If program-fail or erase-fail happen, the write of F0H will reset the device to abort the operation. A valid command must then be written to place the device in the desired state.

SILICON-ID-READ COMMAND

Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacturer and device codes must be accessible while the device resides in the target system. PROM programmers typically access signature codes by raising A9 to a high vo ltage. Howe ver , multiplexing high v o ltage o nto address lines is not generally desired system design practice.

The MX29F040 contains a Silicon-ID-Read operation to supplement traditional PROM programming methodology. The o peratio n is initiated by writing the read silico n ID command sequence into the co mmand register . F o llowing the command write, a read cycle with A1=VIL,A0=VIL retrieves the manufacturer code of C2H. A read cycle with A1=VIL, A0=VIH returns the device code of A4H for MX29F040.

SET-UP AUTOMATIC CHIP/SECTOR ERASE

Chip erase is a six-bus cycle operation. There are two "unloc k" write cycles. These are f o llo wed by writing the "set-up" command 80H. Two more "unlock" write cycles are then followed by the chip erase command 10H.

The Automatic Chip Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Chip Erase. Upon executing the Automatic Chip Erase, the device will automatically program and verify the entire memory fo r an all-zero data pattern. When the device is automatically verified to contain an all-zero pattern, a self-timed chip erase and verify begin. The erase and verify operations are completed when the data on Q7 is "1" at which time the device returns to the Read mod e. The system is not required to provide any control or timing during these operations.

When using the Automatic Chip Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required).

If the Erase operation was unsuccessful, the data on Q5 is "1"(see Table 4), indicating the erase operation exceed internal timing limit.

The automatic erase begins on the rising edge of the last WE o r CE, whichev er happens first pulse in the command sequence and terminates when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mode.

TABLE 3. EXPANDED SILICON ID CODE

Pins A0 A 1 Q 7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code (Hex)

Manufacture code VIL VIL 1 1 0 0 0 0 1 0 C2 H Device code for MX29F040 VIH VIL 1 0 1 0 0 1 0 0 A4 H Sector Protection Verification X VIH 0 0 0 0 0 0 0 1 01H (Protected)

X VIH 0 0 0 0 0 0 0 0 00H(Unprotected)

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SECTOR ERASE COMMANDS

MX29F040

The Automatic Sector Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Set-up Sector Erase command and Automatic Sector Erase command. Upon executing the Automatic Sector Erase command, the device will automatically program and verify the sector(s) memory for an all-zero data pattern. The system is no t required to provide any control or timing during these operations.

When the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verify begin. The erase and verify operations are complete when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mod e. The system is no t required to provide any control or timing during these operations.

When using the Automatic Sector Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array

(no erase verification command is required). Sector erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the set-up command 80H. T w o more "unlo ck" write cycles are then fo llowed b y the sector er ase command 30H. The secto r address is latched on the f alling edge of WE or CE, whichever happens later , while the co mmand (data) is latched on the rising edge o f WE o r CE, whichev er happens first. Sector addresses selected are loaded into internal register on the sixth falling edge of WE or CE, whichever happens later. Each successive sector load cycle started by the falling edge of WE o r CE, whichev er happens later must begin within 30us from the rising edge of the preceding WE or CE, whichever happens first. Otherwise, the loading period ends and internal auto sector erase cycle starts. (Monitor Q3 to determine if the sector erase timer window is still open, see section Q3, Secto r Erase Timer .) Any co mmand other than Sector Erase (30H) or Erase Suspend (B0H) during the timeout period resets the device to read mode.

TABLE 4. Write Operation Status

Status Q7 Q6 Q5 Q3 Q2

Note1 Note2

Byte Program in Auto Program Algorithm Q7 Toggle 0 N/A No Toggle Auto Erase Algorithm 0 Toggle 0 1 Toggle

Erase Suspend Read 1 N o 0 N/A Toggle

In Progress (Erase Suspended Sector) Toggle

Erase Suspended Mode Erase Suspend Read Data Data Data Data Data

(Non-Erase Suspended Sector) Erase Suspend Program Q7 Toggle 0 N/A N/A

Byte Program in Auto Program Algorithm Q7 Toggle 1 N/A No Toggle Exceeded Auto Erase Algorithm 0 Toggle 1 1 Toggle Time Limits Erase Suspend Program Q7 Toggle 1 N/A N/A

Note:

1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits. See "Q5:Exceeded Timing Limits " for more information.

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MX29F040

ERASE SUSPEND

This command only has meaning while the state machine is executing Automatic Sector Erase operation, and therefore will only be responded during Automatic Sector Erase o peratio n. When the Erase Suspend co mmand is written during a sector erase operation, the device requires a maximum of 100us to suspend the erase operatio ns. Howev er, When the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After this command has been executed, the command register will initiate erase suspend mod e. The state machine will return to read mo de automatically after suspend is ready . At this time, state machine only allows the command register to respond to the Read Memory Array, Erase Resume and program commands.

The system can determine the status of the program operation using the Q7 or Q6 status bits, just as in the standard program operation. After an erase-suspend program operation is complete, the system can once again read array data within non-suspended sectors.

ERASE RESUME

This command will cause the command register to clear the suspend state and return back to Sector Erase mode but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in all other conditions. Another Erase Suspend command can be written after the chip has resumed erasing.

SET-UP AUTOMATIC PROGRAM COMMANDS

T o initiate A utomatic Pro gram mo de, A three-cycle co mmand sequence is required. There are two "unlo ck" write cycles. These are f ollow ed by writing the Auto matic Program command A0H.

tem is not required to pro vide further contro ls o r timings. The device will automatically provide an adequate internally generated program pulse and verify margin.

If the program operation was unsuccessful, the data on Q5 is "1"(see Table 4), indicating the program o peratio n exceed internal timing limit. The auto matic pro gramming operation is completed when the data read on Q6 stops toggling for two consecutive read cycles and the data on Q7 and Q6 are equivalent to data written to these two bits, at which time the device returns to the Read mode (no program verify command is required).

DATA POLLING-Q7

The MX29F040 also features Data P o lling as a metho d to indicate to the host system that the Automatic Program or Erase algorithms are either in progress or completed.

While the Automatic Programming algorithm is in operation, an attempt to read the device will produce the complement data of the data last written to Q7. Upon completion of the Automatic Program Algorithm an attempt to read the device will produce the true data last written to Q7. The Data P o lling f eature is valid after the rising edge of the fo urth WE o r CE, whichev er happens first pulse of the four write pulse sequences for automatic program.

While the Automatic Erase algorithm is in operation, Q7 will read "0" until the erase operation is competed. Upon completion of the erase operation, the data on Q7 will read "1". The Data P olling f eature is valid after the rising edge of the sixth WE or CE, whichever happens first pulse of six write pulse sequences for automatic chip/ sector erase.

The Data Po lling feature is activ e during Auto matic Program/Erase algorithm or sector erase time-out. (see section Q3 Sector Erase Timer)

Once the Automatic Program command is initiated, the next WE or CE pulse causes a transition to an active programming operation. Addresses are latched on the falling edge, and data are internally latched on the rising edge of the WE or CE, whichever happens first pulse. The rising edge of WE o r CE, whichever happens first also begins the programming operation. The sys-

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MX29F040

Q6:Toggle BIT I

Toggle Bit I o n Q6 indicates whether an A uto matic Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE or CE, whichever happens first pulse in the command sequence (prior to the program or erase operation), and during the sector time-out.

During an Automatic Program or Erase algorithm operation, successive read cycles to any address cause Q6 to toggle . The system may use either OE o r CE to control the read cycles . When the o peratio n is complete , Q6 stops toggling.

After an erase command sequence is written, if all sectors selected for erasing are protected, Q6 toggles and returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.

The system can use Q6 and Q2 together to determine whether a sector is actively erasing or is erase suspended. When the de vice is actively erasing (that is, the Automatic Erase algorithm is in progress), Q6 toggling. When the device enters the Erase Suspend mode, Q6 stops toggling. However, the system must also use Q2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use Q7.

If a progr am address falls within a protected sector, Q6 toggles for approximately 2us after the program command sequence is written, then returns to reading array data.

Q6 also toggles during the erase-suspend-program mode, and stops toggling once the Automatic Program algorithm is complete.

Table 4 shows the outputs for Toggle Bit I on Q6.

Q2:Toggle Bit II

The "T oggle Bit II" on Q2, when used with Q6, indicates whether a particular sector is actively erasing (that is, the Automatic Erase algorithm is in process), or whether

that sector is er ase-suspended. Toggle Bit I is valid after the rising edge of the final WE o r CE, whichever happens first pulse in the command sequence.

Q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE or CE to control the read cycles.) But Q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. Q6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected f or erasure. Thus , both status bits are required for sectors and mode information. Refer to Table 4 to compare o utputs f or Q2 and Q6.

Reading Toggle Bits Q6/ Q2

Whenever the system initially begins reading toggle bit status, it must read Q7-Q0 at least twice in a row to determine whether a toggle bit is to ggling. T ypically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the pro gr am o r erase o peratio n. The system can read array data on Q7-Q0 on the following read cycle.

Howe v e r, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of Q5 is high (see the section on Q5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as Q5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data.

The remaining scenario is that system initially determines that the toggle bit is toggling and Q5 has not gone high. The system may continue to monitor the toggle bit and Q5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation.

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MX29F040

Q5 Exceeded Timing Limits

Q5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions Q5 will produce a "1". This time-out condition indicates that the program or erase cycle was not successfully co mpleted. Data Po lling and Toggle Bit are the only operating functions of the device under this condition.

If this time-out condition occurs during sector erase operation, it specifies that a particular secto r is bad and it may no t be reused. Ho wev er, o ther secto rs are still functional and may be used for the program or erase operation. The device must be reset to use other sectors. Write the Reset command sequence to the device, and then execute pro gram o r erase co mmand sequence. This allows the system to continue to use the other active sectors in the device.

If this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination of sectors are bad.

If this time-out condition occurs during the byte programming operation, it specifies that the entire sector containing that byte is bad and this sector may not be reused, (other sectors are still functional and can be reused).

specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting fro m VCC power-up and pow er-down transition or system noise.

Q3 Sector Erase Timer

After the completion of the initial sector erase command sequence, the sector erase time-out will begin. Q3 will remain low until the time-out is complete. Data Polling and Toggle Bit are v alid after the initial sector er ase command sequence.

If Data Po lling o r the Toggle Bit indicates the de vice has been written with a valid erase command, Q3 may be used to determine if the sector erase timer window is still open. If Q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit. If Q3 is low ("0"), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of Q3 prior to and following each subsequent sector erase command. If Q3 were high on the second status check, the command may not have been accepted.

The time-out condition may also appear if a user tries to program a non blank location without erasing. In this case the device locks out and never completes the Automatic Algorithm operation. Hence, the system never reads a valid data on Q7 bit and Q6 never stops toggling. Once the Device has exceeded timing limits, the Q5 bit will indicate a "1". Please note that this is not a device failure condition since the device was incorrectly used.

DATA PROTECTION

The MX29F040 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of

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WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns (typical) on CE or WE will not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding an y one of OE = VIL, CE = VIH o r WE = VIH. T o initiate a write cycle CE and WE must be a logical zero while OE is a logical one.

POWER SUPPLY DECOUPLING

In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected between its VCC and GND .

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MX29F040

SECTOR PROTECTION WITH 12V SYSTEM

The MX29F040 features secto r pro tection. This f eature will disable both program and erase operations for these sectors protected. To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest VID = 12V) A6 = VIL and CE = VIL. (see Table 2) Programming of the protection circuitry begins on the falling edge o f the WE or CE, whichever happens later pulse and is terminated on the rising edge. Please refer to sector protect algorithm and waveform.

T o v erify programming o f the pro tectio n circuitry , the programming equipment must fo rce VID o n address pin A9 ( with CE and OE at VIL and WE at VIH). When A1=1, it will produce a logical "1" code at device output Q0 for a protected secto r . Otherwise the device will pro duce 00H fo r the unpro tected secto r . In this mo de, the addresses, except for A1, are don't care. Address locations with A1 = VIL are reserved to read manuf acturer and device co des. (Read Silicon ID)

It is also possible to determine if the sector is protected in the system by writing a Read Silicon ID command. Perf orming a read o peratio n with A1=VIH, it will pro duce a logical "1" at Q0 for the protected sector.

CHIP UNPROTECT WITH 12V SYSTEM

is noted that all sectors are unprotected after the chip unprotect algorithm is completed.

POWER-UP SEQUENCE

The MX29F040 powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of the predefined command sequences.

SECTOR PROTECTION WITHOUT 12V SYSTEM

The MX29F040 also feature a sector protection method in a system without 12V po wer supply . The programming equipment do not need to supply 12 volts to protect sectors. The details are shown in sector protect algorithm and waveform.

CHIP UNPROTECT WITHOUT 12V SYSTEM

The MX29F040 also feature a chip unprotection method in a system without 12V po wer supply . The programming equipment do not need to supply 12 volts to unprotect all sectors. The details are shown in chip unprotect algorithm and waveform.

The MX29F040 also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code. It is recommended to protect all sectors before activating chip unprotect mode.

T o activ ate this mode , the prog ramming equipment must fo rce VID on co ntro l pin OE and address pin A9. The CE pins must be set at VIL. Pins A6 must be set to VIH.(see Table 2) Refer to chip unprotect algor ithm and wavefo rm for the chip unprotect algorithm. The unprotectio n mechanism begins on the f alling edge o f the WE o r CE, whichever happens later , pulse and is terminated on the rising edge.

It is also possible to determine if the chip is unprotected in the system by writing the Read Silicon ID command. Perf orming a read o peratio n with A1=VIH, it will pro duce 00H at data o utputs(Q0-Q7) fo r an unpro tected sector . It

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REV. 2.3, DEC. 10, 2004

Page 13

MX29F040

CAPACITANCE (TA = 25oC, f = 1.0 MHz)

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS

CIN1 Input Capacitance 8 pF VIN = 0V CIN2 Control Pin Capacitance 12 pF VIN = 0V COUT Output Capacitance 12 pF VOUT = 0V

READ OPERATION

DC CHARACTERISTICS (TA = 0°C TO 70°C, -40oC to 85oC,VCC = 5V

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS

ILI Input Leakage Current 1 uA VIN = GND to VCC ILO Output Leakage Current 10 uA VOUT = GND to VCC ISB1 Standby VCC current 1 mA CE = VIH ISB2 1 5 uA CE = VCC + 0.3V ICC1 Operating VCC current 30 mA IOUT = 0mA, f=5MHz ICC2 50 mA IOUT = 0mA, f=10MHz VIL Input Low Voltage -0.3 (NOTE 1) 0.8 V VIH Input High Voltage 2 .0 VCC + 0.3 V VOL Output Low Voltage 0.45 V IOL = 2.1mA VOH1 Output High Voltage(TTL) 2.4 V IOH = -2mA VOH2 Output High Voltage(CMOS) VCC-0.4 V IOH = -100uA,VCC=VCC MIN

NOTES:

1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns.

VIL min. = -2.0V for pulse width is equal to or less than 20 ns.

2. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns. If VIH is over the specified maximum value, read operation cannot be guaranteed.

AC CHARA CTERISTICS (T A = 0oC to 70oC, -40oC to 85oC,VCC = 5V

±±

±10%)

±±

±10%)

±±

29F040-55(note2)29F040-70 29F040-90 29F040-12

Symbol PARAMETER MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Unit Conditions

tACC Address to Output Delay 5 5 70 90 120 ns CE=OE=VIL tCE CE to Output Delay 55 70 90 12 0 n s OE=VIL tOE OE to Output Delay 30 40 40 50 ns CE=VIL tDF OE High to Output Float (Note1)0 30 0 30 0 40 0 40 ns CE=VIL tOH Address to Output hold 0 0 0 0 ns CE=OE=VIL

TEST CONDITIONS:

• Input pulse levels: 0.45V/2.4V

• Input rise and fall times is equal to or less than 0ns

• Output load: 1 TTL gate + 100pF (Including scope and jig)

• Reference levels for measuring timing: 0.8V, 2.0V

P/N:PM0538

NOTE:

1. tDF is defined as the time at which the output achieves the

open circuit condition and data is no longer driven.

2. Under condition of VCC=5V±10%,CL=50pF,VIH/VIL=3.0/

0V,VOH/VOL=1.5/1.5V,IOL=2mA,IOH=-2mA.

REV. 2.3, DEC. 10, 2004

Page 14

MX29F040

ABSOLUTE MAXIMUM RATINGS

RATING VALUE

Ambient Operating Temperature -40oC to 85oC Storage Temperature -65oC to 125oC Ambient Temperature with Power -55oC to 125oC Applied Applied Input Voltage -0.5V to 7.0V Applied Output Voltage -0.5V to 7.0V VCC to Ground Potential -0.5V to 7.0V A9 & OE -0.5V to 13.5V

READ TIMING WAVEFORMS

Addresses

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

NOTICE:

Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability.

NOTICE:

Specifications contained within the following tables are subject to change.

ADD Valid

tCE

tOE

tACC

tDF

tOH

HIGH Z HIGH Z

Outputs

VOH

VOL

DATA V alid

COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION

DC CHARACTERISTICS (T A = 0oC to 70oC, -40oC to 85oC,VCC = 5V

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS

ICC1 (Read) Operating VCC Current 3 0 mA IOUT=0mA, f=5MHz ICC2 50 mA IOUT=0mA, F=10MHz ICC3 (Program) 50 mA In Programming ICC4 (Erase) 50 mA In Erase ICCES VCC Erase Suspend Current 2 mA CE=VIH, Erase Suspended

NOTES:

1. VIL min. = -0.6V for pulse width is equal to or less than 20ns.

2. If VIH is over the specified maximum value, programming operation cannot be guaranteed.

P/N:PM0538

3. ICCES is specified with the device de-selected. If the device is read during erase suspend mode, current draw is the sum of ICCES and ICC1 or ICC2.

4. All current are in RMS unless otherwise noted.

±±

±10%)

±±

REV. 2.3, DEC. 10, 2004

Page 15

MX29F040

AC CHARACTERISTICS TA = 0oC to 70oC, -40oC to 85oC,VCC = 5V

±±

± 10%

±±

29F040-55(Note2) 29F040-70 29F040-90 29F040-12

SYMBOL PARAMETER MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Unit

tOES OE setup time 50 50 50 50 ns tCWC Command programming cycle 70 70 90 120 n s tCEP WE programming pulse width 45 45 45 50 ns tCEPH1 WE programming pulse width High 20 20 20 20 ns tCEPH2 WE programming pulse width High 20 20 20 20 ns tAS Address setup time 0 0 0 0 ns tAH Address hold time 45 45 45 50 ns tDS Data setup time 30 30 45 50 ns tDH Data hold time 0 0 0 0 ns tCESC CE setup time before command write 0 0 0 0 ns tDF Output disable time (Note 1) 3 0 30 40 40 ns tAETC Total erase time in auto chip erase 4(TYP.) 32 4(TYP.) 32 4(TYP.) 32 4(TYP.) 32 s tAETB Total erase time in auto sector erase 1.3(TYP.)10.4 1.3(TYP.) 10.4 1.3(TYP.)10.4 1.3(TYP.)10.4 s tAVT Total programming time in auto verify 7 210 7 210 7 210 7 210 u s tBAL Sector address load time 100 100 100 100 us tCH CE Hold Time 0 0 0 0 ns tCS CE setup to WE going low 0 0 0 0 ns tVLHT Voltage Transition Time 4 4 4 4 us tOESP OE Setup Time to WE Active 4 4 4 4 us tWPP1 Write pulse width for sector protect 10 10 10 10 u s tWPP2 Write pulse width for sector unprotect 1 2 12 12 12 ms

NOTES:

1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.

2. Under conditions of VCC=5V±10%,CL=50pF,VIH/VIL=3.0/0V,VOL/VOH=1.5/1.5, IOL=2mA,IOH=-2mA.

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REV. 2.3, DEC. 10, 2004

Page 16

SWITCHING TEST CIRCUITS

MX29F040

DEVICE UNDER

TEST

SWITCHING TEST WAVEFORMS

2.4V

0.45V

AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0". Input pulse rise and fall times are < 20ns.(5ns for 29F040-55) Note:VIH/VIL=3.0/0V,VOH/VOL=1.5/1.5V for 29F040-55

INPUT

CL=100pF Including jig capacitance CL= 50pF for 29F040-55

1.2K ohm

2.0V 2.0V

TEST POINTS

0.8V

1.6K ohm

DIODES=IN3064

OR EQUIVALENT

0.8V OUTPUT

+5V

COMMAND WRITE TIMING WAVEFORM

VCC

Addresses

Data

P/N:PM0538

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

ADD Valid

tAS

tOES

tCS tCH

tCEP

tDS

tAH

tCEPH1

tCWC

tDH

DIN

REV. 2.3, DEC. 10, 2004

Page 17

AUTOMATIC PROGRAMMING TIMING WAVEFORM

MX29F040

One byte data is programmed. Verify in fast algorithm and additional programming by external control are not required because these operations are executed automatically by internal control circuit. Programming completion can be verified by DATA polling and toggle

AUTOMATIC PROGRAMMING TIMING WAVEFORM

Vcc 5V

A11~A18

A0~A10

555H

tAS

2AAH

tCWC

tAH

tCEPH1

555H

bit checking after automatic verification starts. Device outputs DAT A during pro g ramming and D AT A after programming on Q7.(Q6 is for toggle bit; see toggle bit, DAT A po lling, timing wa vef orm)

ADD V alid

tAVT

tCESC

Q0,Q1,Q2

Q4(Note 1)

tCEP

tDS tDH

Command In

Command In Command InCommand In Data In

Command #AAH

(Q0~Q7)

Command #55H

Command InCommand In Data In

Command #A0H

Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit

tDF

DATA

DATA polling

DATADATA

tOE

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REV. 2.3, DEC. 10, 2004

Page 18

AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data A0H Address 555H

Write Program Data/Address

MX29F040

Invalid Command

Toggle Bit Checking

Q6 not Toggled

Verify Byte Ok

Auto Program Completed

YES

Q5 = 1

YES

Reset

Auto Program Exceed Timing Limit

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REV. 2.3, DEC. 10, 2004

Page 19

AUTOMATIC CHIP ERASE TIMING WAVEFORM

MX29F040

All data in chip are erased. External erase verification is not required because data is erased automatically by internal control circuit. Erasure completion can be verified by DATA polling and toggle bit checking after

AUTOMATIC CHIP ERASE TIMING WAVEFORM

Vcc 5V

A11~A18

A0~A10

555H

2AAH

555H

tAS

tAH

automatic erase starts. Device outputs 0 during erasure and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform)

555H 2AAH

555H

tCWC

tCEPH1

tAETC

Q0,Q1,

Q4(Note 1)

tCEP

tDS tDH

Command In

Command In Command InCommand In

Command #AAH Command #55H

Command InCommand In

Command #80H

Command #AAH

Command In

(Q0~Q7)

Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

Command In

Command #55H

Command #10H

Command In

DATA polling

Command In

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REV. 2.3, DEC. 10, 2004

Page 20

AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 10H Address 555H

MX29F040

Invalid Command

Toggle Bit Checking

Q6 not Toggled

YES

DATA Polling

Q7 = 1

YES

Auto Chip Erase Completed

Q5 = 1

YES

Reset

Auto Chip Erase Exceed Timing Limit

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REV. 2.3, DEC. 10, 2004

Page 21

AUTOMATIC SECTOR ERASE TIMING WAVEFORM

MX29F040

Sector data indicated by A16 to A18 are erased. External erase verify is not required because data are erased automatically by internal control circuit. Erasure completion can be verified by DATA polling and toggle bit

AUTOMATIC SECTOR ERASE TIMING WAVEFORM

Vcc 5V

A16-A18

A0~A10

555H 2AAH 2AAH

tAS

tAH

555H 555H

checking after automatic erase starts. Device outputs 0 during erasure and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform)

Sector

Address0

tCWC

tCEPH1

Sector

Address1

Sector

Addressn

tBAL

tAETB

Q0,Q1,

Q4(Note 1)

P/N:PM0538

tCEP

tDS

tDH

Command InCommand

Command

(Q0~Q7)

Command InCommand

Command InCommand InCommand InCommand

Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

Command

Command #30HCommand #30HCommand #30HCommand #55HCommand #AAHCommand #80HCommand #55HCommand #AAH

DATA polling

REV. 2.3, DEC. 10, 2004

Page 22

AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 30H Sector Address

MX29F040

Toggle Bit Checking

Q6 T oggled ?

YES

Load Other Sector Addrss If Necessary (Load Other Sector Address)

Last Sector to Erase

Time-out Bit

Checking Q3=1 ?

YES

Toggle Bit Checking

Q6 not Toggled

DATA Polling

Q7 = 1

YES

Invalid Command

Q5 = 1

P/N:PM0538

Auto Sector Erase Completed

Reset

Auto Sector Erase Exceed

Timing Limit

REV. 2.3, DEC. 10, 2004

Page 23

ERASE SUSPEND/ERASE RESUME FLOWCHART

START

Write Data B0H

MX29F040

Toggle Bit checking Q6

not toggled

YES

Read Array or

Program

Reading or

Programming End

YES

Write Data 30H

Continue Erase

Another

Erase Suspend ?

YES

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REV. 2.3, DEC. 10, 2004

Page 24

MX29F040

TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITH 12V

12V

tVLHT

Verify

tVLHT

tWPP 1

tOESP

Data

A18-A16 Sector Address

01H F0H

tOE

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REV. 2.3, DEC. 10, 2004

Page 25

MX29F040

TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITH 12V

12V

tVLHT

12V

Data

tVLHT

tOESP

tWPP 2

tVLHT

tOE

Verify

00H

F0H

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REV. 2.3, DEC. 10, 2004

Page 26

SECTOR PROTECTION ALGORITHM FOR SYSTEM WITH 12V

START

Set Up Sector Addr

(A18, A17, A16)

PLSCNT=1

OE=VID,A9=VID,CE=VIL

A6=VIL

Activate WE Pulse

Time Out 10us

MX29F040

PLSCNT=32?

Device Failed

Yes

Set WE=VIH, CE=OE=VIL A9 should remain VID

Read from Sector

Addr=SA, A1=1

Data=01H?

Protect Another

Sector?

Remove VID from A9

Write Reset Command

Sector Protection

Complete

Yes

P/N:PM0538

REV. 2.3, DEC. 10, 2004

Page 27

CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITH 12V

START

Protect All Sectors

PLSCNT=1

Set OE=A9=VID CE=VIL,A6=1

Activate WE Pulse

MX29F040

Increment

Sector Addr

Set Up First Sector Addr

Read Data from Device

Remove VID from A9

Write Reset Command

Time Out 12ms

Set OE=CE=VIL

A9=VID,A1=1

Data=00H?

Yes

All sectors have

been verified?

Yes

Chip Unprotect

Complete

Increment

PLSCNT

PLSCNT=1000?

Yes

Device Failed

P/N:PM0538

* It is recommended before unprotect whole chip, all sectors should be protected in advance.

REV. 2.3, DEC. 10, 2004

Page 28

MX29F040

TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITHOUT 12V

Toggle bit polling

tCEP

* See the following Note!

Data

Don't care

(Note 2)

A18-A16 Sector Address

Note1: Must issue "unlock for sector protect/unprotect" command before sector protection for a system without 12V provided.

Note2: Except F0H

tOE

Verify

01H

F0H

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REV. 2.3, DEC. 10, 2004

Page 29

MX29F040

TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITHOUT 12V

Data

Toggle bit polling

tCEP

* See the following Note!

Don't care

(Note 2)

Verify

00H

tOE

Note1: Must issue "unlock for sector protect/unprotect" command before sector unprotection for a system without 12V provided.

Note2: Except F0H

F0H

P/N:PM0538

REV. 2.3, DEC. 10, 2004

Page 30

SECTOR PROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V

START

PLSCNT=1

MX29F040

Increment PLSCNT

PLSCNT=32?

Write "unlock for sector protect/unprotect"

Command(Table1)

Set Up Sector Addr

(A18, A17, A16)

OE=VIH,A9=VIH

CE=VIL,A6=VIL

Activate WE Pulse to start

Data don't care

Toggle bit checking

Q6 not Toggled

Yes

Set CE=OE=VIL

A9=VIH

Read from Sector

Addr=SA, A1=1

Data=01H?

P/N:PM0538

Yes

Device Failed

Protect Another

Sector?

Write Reset Command

Sector Protection

Complete

Yes

REV. 2.3, DEC. 10, 2004

Page 31

CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V

START

Protect All Sectors

PLSCNT=1

MX29F040

Increment

Sector Addr

Write "unlock for sector protect/unprotect"

Command (Table 1)

Set OE=A9=VIH CE=VIL,A6=1

Activate WE Pulse to start Data do'nt care

Toggle bit checking Q6 not Toggled

Set OE=CE=VIL

A9=VIH,A1=1

Set Up First Sector Addr

Read Data from Device

Data=00H?

Yes

Increment

PLSCNT

PLSCNT=1000?

Yes

P/N:PM0538

* It is recommended before unprotect whole chip, all sectors should be protected in advance.

All sectors have

been verified?

Yes

Write Reset Command

Chip Unprotect

Complete

Device Failed

REV. 2.3, DEC. 10, 2004

Page 32

ID CODE READ TIMING WAVEFORM

MX29F040

VCC

ADD

A2-A8

A10-A18

DATA

Q0-Q7

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VID VIH

VIL

tACC

tCE

tOE

DATA OUT

C2H

tOH

tACC

tDF

tOH

DATA OUT

A4H

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REV. 2.3, DEC. 10, 2004

Page 33

MX29F040

ERASE AND PROGRAMMING PERFORMANCE (1)

LIMITS

PARAMETER MIN. TYP.(2) MAX.(3) UNITS

Sector Erase Time 1.3 10.4 sec Chip Erase Time 4 32 sec Byte Programming Time 7 21 0 us Chip Programming Time 4 12 sec Erase/Program Cycles 100,000 Cycles

Note: 1.Not 100% Tested, Excludes external system level o v er head.

2.T ypical v alues measured at 25°C,5V.

3.Maximunm values measured at 25°C,4.5V.

LATCH-UP CHARACTERISTICS

MIN. MAX.

Input Voltage with respect to GND on all pins except I/O pins -1.0V 13.5V Input Voltage with respect to GND on all I/O pins -1.0V Vcc + 1.0V Current -100mA +100mA Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.

DATA RETENTION

PARAMETER MIN. UNIT

Data Retention Time 20 Years

P/N:PM0538

REV. 2.3, DEC. 10, 2004

Page 34

MX29F040

ORDERING INFORMATION

PLASTIC PACKAGE

P ART NO. Access Time Operating Current Standby Current T emperature P ACKAGE Remark

(ns) MAX.(mA) MAX.(uA) Range

MX29F040QC-55 55 30 5 0oC~70oC 32 Pin PLCC MX29F040QC-70 70 30 5 0oC~70oC 32 Pin PLCC MX29F040QC-90 90 30 5 0oC~70oC 32 Pin PLCC MX29F040QC-12 120 30 5 0oC~70oC 32 Pin PLCC MX29F040TC-55 55 30 5 0oC~70oC 32 Pin TSOP

(Normal Type)

MX29F040TC-70 70 30 5 0oC~70oC 32 Pin TSOP

(Normal Type)

MX29F040TC-90 90 30 5 0oC~70oC 32 Pin TSOP

(Normal Type)

MX29F040TC-12 120 30 5 0oC~70oC 32 Pin TSOP

(Normal Type) MX29F040PC-55 55 30 5 0oC~70oC 32 Pin PDIP MX29F040PC-70 70 30 5 0oC~70oC 32 Pin PDIP MX29F040PC-90 90 30 5 0oC~70oC 32 Pin PDIP MX29F040PC-12 120 30 5 0oC~70oC 32 Pin PDIP MX29F040QC-55G 55 30 5 0oC~70oC 32 pin PLCC PB free MX29F040QC-70G 70 30 5 0oC~70oC 32 pin PLCC PB free MX29F040QC-90G 90 30 5 0oC~70oC 32 pin PLCC PB free MX29F040TC-55G 55 30 5 0oC~70oC 32 pin TSOP PB free MX29F040TC-70G 70 30 5 0oC~70oC 32 pin TSOP PB free MX29F040TC-90G 90 30 5 0oC~70oC 32 pin TSOP PB free MX29F040TC-12G 120 30 5 0oC~70oC 32 pin TSOP PB free MX29F040PC-55G 55 30 5 0oC~70oC 32 pin PDIP PB free MX29F040PC-70G 70 30 5 0oC~70oC 32 pin PDIP PB free MX29F040PC-90G 90 30 5 0oC~70oC 32 pin PDIP PB free MX29F040QI-55 55 30 5 -40oC~85oC 32 Pin PLCC MX29F040QI-70 70 30 5 -40oC~85oC 32 Pin PLCC MX29F040QI-90 90 30 5 -40oC~85oC 32 Pin PLCC

P/N:PM0538

REV. 2.3, DEC. 10, 2004

Page 35

MX29F040

P ART NO. Access Time Operating Current Standby Current T emperature PACKAGE Remark

(ns) MAX.(mA) MAX.(uA) Range

MX29F040TI-55 55 30 5 -40oC~85oC 32 Pin TSOP

(Normal Type)

MX29F040TI-70 70 30 5 -40oC~85oC 32 Pin TSOP

(Normal Type)

MX29F040TI-90 90 30 5 -40oC~85oC 32 Pin TSOP

(Normal Type) MX29F040PI-55 55 30 5 -40oC~85oC 32 Pin PDIP MX29F040PI-70 70 30 5 -40oC~85oC 32 Pin PDIP MX29F040PI-90 90 30 5 -40oC~85oC 32 Pin PDIP MX29F040QI-55G 55 30 5 -40oC~85oC 32 Pin PLCC PB free MX29F040QI-70G 70 30 5 -40oC~85oC 32 Pin PLCC PB free MX29F040QI-90G 90 30 5 -40oC~85oC 32 Pin PLCC PB free MX29F040TI-55G 55 30 5 -40oC~85oC 32 Pin TSOP PB free

(Normal Type) MX29F040TI-70G 70 30 5 -40oC~85oC 32 Pin TSOP PB free

(Normal Type) MX29F040TI-90G 90 30 5 -40oC~85oC 32 Pin TSOP PB free

(Normal Type) MX29F040PI-55G 55 30 5 -40oC~85oC 32 Pin PDIP PB free MX29F040PI-70G 70 30 5 -40oC~85oC 32 Pin PDIP PB free MX29F040PI-90G 90 30 5 -40oC~85oC 32 Pin PDIP PB free

P/N:PM0538

REV. 2.3, DEC. 10, 2004

Page 36

PACKAGE INFORMATION

MX29F040

P/N:PM0538

REV. 2.3, DEC. 10, 2004

Page 37

MX29F040

P/N:PM0538

REV. 2.3, DEC. 10, 2004

Page 38

MX29F040

P/N:PM0538

REV. 2.3, DEC. 10, 2004

Page 39

MX29F040

REVISION HISTORY

Revision Description Page Date

1.0 To remove "Adv anced Info rmatio n" datasheet marking and P1 JUL/01/1999 contain information on products in full production.

1.1 To improve ICC1:fro m 40mA @5MHz to 30mA @5MHz P1,13,14,33 JUL/12/1999

1.2 To add the description fo r 100K endurance cycle P1,3 4 OCT/04/1999 To modify timing of sector address loading period while P8 operating multi-sector erase from 80us to 30us To modify tBAL from 80us to 100us P15

1.3 1.Program/erase cycle times:10K cycles-->100K cycles P1,34 DEC/17/1999

2.To remove A9 from "timing waveform for sector protection for P28 system without 12V" To remove A9 from "timing waveform for chip unprotection for P29 system without 12V"

3.T o add data retentio n minimum 20 y ears P1,34

1.4 Add erase suspend ready max. 100us in ERASE SUSPEND's P9 MA Y/29/2000 section at page 9

1.5 To modify "Pac kage Information" P35~37 JUN/12/2001

1.6 T o add "Ambient temperature with pow er applied" P14 AUG/08/2001

1.7 1. To corrected typing erro r All JUL/01/2002

1.8 1. Changed flow chart of chip unprotection algorithm for system P27,31 SEP/04/2002 with and without 12V

1.9 To modify Pac kage Inf ormation P35~37 NOV/21/2002

2.0 1. Add 32 pin TSOP PB free package P3 4 JAN/17/2003

2. To modify 32-PDIP & 32-PLCC package inf o rmation P35,36

2.1 1. Add industrial grade o ptio n P13~15, P34 A UG/20/2004

2.2 1. Added Pb-free o ption P34 NO V/08/2004

2.3 1. Added industrial-grade PB free o ptio n P35 DEC/10/2004

P/N:PM0538

REV. 2.3, DEC. 10, 2004

Page 40

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