Datasheet MX29F022BPC-12, MX29F022BPC-55, MX29F022BPC-70, MX29F022BPC-90, MX29F022BQC-12 Datasheet (MXIC)

FEATURES

MX29F022/022N

2M-BIT[256K x 8]CMOS FLASH MEMORY

• 262,144x 8 only

• Fast access time: 55/70/90/120ns

• Low power consumption

-30mA maximum active current

-1uA typical standby current@5MHz

• Programming and erasing voltage 5V ±10%

• Command register architecture

-Byte Programming (7us typical)

-Sector Erase (16K-Byte x1, 8K-Byte x 2, 32K-Byte
x1, and 64K-Byte x 3)

• Auto Erase (chip & sector) and Auto Program

-Automatically erase any combination of sectors or
the whole chip with Erase Suspend capability.

-Automatically programs and verifies data atspecified
address

• Erase Suspend/Erase Resume

-Suspends an erase operation to read data from,
or program data to, a sector that is not being er ased,
then resumes the erase operation.

GENERAL DESCRIPTION

• Status Reply

-Data polling & Toggle bit f or detection of program and
erase cycle completion.

• Chip protect/unprotect for 5V only system or 5V/12V

system

• 100,000 minimum erase/program cycles

• Latch-up protected to 100mA from -1 to VCC+1V

• Boot Code Sector Architecture

-T = Top Boot Sector

-B = Bottom Boot Sector

• Hardware RESET pin

-Resets internal state machine to read mode

• Low VCC write inhibit is equal to or less than 3.2V

• Pac kage type:

-32-pin PDIP

-32-pin PLCC

-32-pin TSOP (Type 1)

• 20 years data retention

The MX29F022T/B is a 2-mega bit Flash memory
organized as 256K bytes of 8 bits only. MXIC's Flash
memories offer the most cost-effectiv e and reliable read/
write non-volatile random access memory.The
MX29F022T/B is packaged in 32-pin PDIP, PLCC and
32-pin TSOP(I). It is designed to be reprogrammed and
erased in-system or in-standard EPROM programmers.

The standard MX29F022T/B offers access time as fast
as 55ns, allowing operation of high-speed microproc
essors without wait states. T o eliminate b us contention,
the MX29F022T/B has separate chip enable (CE) and
output enable (OE) controls.

MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F022T/B uses a command register to manage this
functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining
maximum EPROM compatibility.

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MXIC's Flash technology reliably stores memory
contents even after 100,000 erase and program cycles.
The MXIC cell is designed to optimize the erase and
programming mechanisms. In addition, the combina­tion of advanced tunnel oxide processing and low
internal electric fields for erase and programming
operations produces reliable cycling. The MX29F022T/
B uses a 5.0V ± 10% VCC supply to perform the High
Reliability Erase and auto Program/Erase algorithms.

The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up
protection is proved f or stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.

1

MX29F022/022N

PIN CONFIGURATIONS

32 PDIP

NC on MX29F022NT/B

RESET

A16
A15
A12

GND

A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

VCC

32

WE

31

A17

30

A14

29

A13

28

A8

27

A9

26

A11

25

OE

24

A10

23

CE

22

MX29F022T/B

Q7

21

Q6

20

Q5

19

Q4

18

Q3

17

(NC on

MX29F022NT/B)

32 PLCC

NC on MX29F022NT/B

A12

A15

A16

RESET

VCCWEA17

4

5

A7
A6
A5
A4

9

A3
A2
A1
A0

13

Q0

14 17 20

Q1

1

32

MX29F022T/B

Q2

Q3Q4Q5

VSS

30

29

A14
A13
A8
A9

25

A11
OE
A10
CE

21

Q7

Q6

PIN DESCRIPTION:

SYMBOL PIN NAME

A0~A17 Address Input
Q0~Q7 Data Input/Output
CE Chip Enable Input
WE Write Enable Input
RESET Hardware Reset Pin/Sector Protect Unlock
OE Output Enable Input
VCC Power Supply Pin (+5V)
GND Ground Pin

32 TSOP (TYPE 1)

WE

1
2

A9

3

A8

4
5
6
7
8
9
10
11
12
13

A7

14

A6

15

A5

16

A4

A11

A13
A14
A17

VCC

RESET

A16
A15
A12

SECTOR STRUCTURE

A17~A0

3FFFFH

3BFFFH

39FFFH

37FFFH
2FFFFH
1FFFFH

0FFFFH

00000H

A17~A0

3FFFFH
2FFFFH

1FFFFH

0FFFFH

07FFFH
05FFFH
03FFFH

00000H

MX29F022T/B

(NORMAL TYPE)

16 K-BYTE

(BOOT SECTOR)

8 K-BYTE

8 K-BYTE

32 K-BYTE
64 K-BYTE

64 K-BYTE
64 K-BYTE

MX29F022T Sector Architecture

64 K-BYTE

64 K-BYTE
64 K-BYTE

32 K-BYTE

8 K-BYTE
8 K-BYTE

16 K-BYTE

(BOOT SECTOR)

32

OE

31

A10

30

CE

29

Q7

28

Q6

27

Q5

26

Q4

25

Q3

24

GND

23

Q2

22

Q1

21

Q0

20

A0

19

A1

18

A2

17

A3

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MX29F022B Sector Architecture

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Block Diagram

MX29F022/022N

CE
OE

WE

RESET

A0-A17

CONTROL

INPUT
LOGIC

ADDRESS

LATCH

AND

BUFFER

PROGRAM/ERASE

HIGH VOLT AGE

X-DECODER

FLASH
ARRA Y

Y-DECODER

Y-PASS GATE

ARRAY

SOURCE

HV

WRITE

STATE

MACHINE

(WSM)

STATE

REGISTERMX29F022T/B

COMMAND

DATA

DECODER

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Q0-Q7

SENSE

AMPLIFIER

I/O BUFFER

3

PGM
DATA

HV

PROGRAM

DATA LATCH

COMMAND

DATA LATCH

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MX29F022/022N

AUTOMATIC PROGRAMMING

The MX29F022T/B is byte programmable using the
Automatic Programming algorithm. The Automatic
Programming algorithm does not require the system to
time out or verify the data programmed. The typical chip
programming time of the MX29F022T/B at room tem­perature is less than 2 seconds.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10ms erase pulses
according to MXIC's High Reliability Chip Erase
algorithm. Typical erasure at room temperature is
accomplished in less than two second. The device is
erased using the Automatic Erase algorithm. The
Automatic Erase algorithm automatically programs the
entire array prior to electrical erase. The timing and
verification of electrical erase are internally controlled
within the device.

AUTOMATIC SECTOR ERASE

The MX29F022T/B is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. Sector erase modes allow
sectors of the array to be erased in one erase cycle . The
Automatic Sector Erase algorithm automatically pro­grams the specified sector(s) prior to electrical erase.
The timing and verification of electrical erase are inter­nally controlled by the device.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stan­dard microprocessor write timings. The device will au­tomatically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
verifily the erase, and counts the number of sequences .
A status bit similar to DATA polling and status bit tog­gling between consecutive read cycles prodvides feed­back to the user as to the status of the programming
operation.

Commands are written to the command register using
standard microprocessor write timings. Register con­tents serve as inputs to an internal state-machine which
controls the erase and programming circuitry. During
write cycles, the command register internally latches
address and data needed for the programming and erase
operations. During a system write cycle addresses are
latched on the falling edge, and data are latched on the
rising edge of WE .

MXIC's Flash technology combines years of EPROM
experience to produce the highest lev els of quality, reli­ability , and cost eff ectiv eness. The MX29F022T/B elec­trically erases all bits simultaneously using Fowler­Nordheim tunneling. The bytes are programmed one
byte at a time using the EPROM programming mecha­nism of hot electron injection.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm requires the
user to only write a program set-up commands (include
2 unlock arite cycle and A0H) include 2 unlock arite cycle
and A0H and a program command (program data and
address). The de vice automatically times the program­ming pulse width, verifies the program verification, and
counts the number of sequences. A status bit similar to
DAT A polling and a status bit toggling between consecu­tive read cycles, provides f eedback to the user as to the
status of the programming operation.

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During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode . After the state machine
has completed its task, it will allow the command regis­ter to respond to its full command set.

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MX29F022/022N

T able 1 Software Command Definitions

First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus

Command Bus Cycle Cycle Cycle Cycle Cycle Cycle

Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Reset 1 XXXH F0H
Read 1 RA RD
Read Silicon ID 4 555H AAH 2AAH 5 5H 555H 90H ADI DDI
Chip Protect Verify 4 555H AAH 2AAH 55H 555H 90H (SA) 00 H

X02H 01H
Porgram 4 555H AAH 2AAH 55H 555H A0H PA PD
Chip Erase 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H
Sector Erase 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H
Sector Erase Suspend 1 XXXH B0H
Sector Erase Resume 1 XXXH 30H
Unlock for chip 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 20H
protect/unprotect

Note:

1. ADI = Address of Device identifier; A1=0,A0 =0 for manufacture code,A1=0, A0 =1 for device code (Refer to Table 3).
DDI = Data of Device identifier : C2H for manufacture code, 36H/37H for device code.
X = X can be VIL or VIH
RA=Address of memory location to be read.
RD=Data to be read at location RA.

2. PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA.
SA = Address to the sector to be erased.

3. The system should generate the following address patterns: 555H or 2AAH to Address A0~A10.
Address bit A11~A17=X=Don't care for all address commands except for Program Address (PA) and Sector
Address (SA). Write Sequence may be initiated with A11~A17 in either state.

4. For Chip Protect Verify operation:If read out data is 01H, it means the chip has been protected. If read out data is 00H,
it means the chip is still not being protected.

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MX29F022/022N

TABLE 2. MX29F022T/B BUS OPERATION

Pins CE OE WE A0 A1 A6 A9 Q0~Q7
Mode
Read Silicon ID L L H L L X VID(2) C2H
Manfacturer Code(1)
Read Silicon ID L L H H L X VID(2) 36H/37H
Device Code(1)
Read L L H A0 A1 A6 A9
Standby H X X X X X X HIGH Z
Output Disable L H H X X X X HIGH Z
Write L H L A0A1 A6A9
Chip Protect with 12V L VID(2) L X X L VID(2) X
system(6)
Chip Unprotect with 12V L VID(2) L X X H VID(2) X
system(6)
V erify chip Protect L L H X H X VID(2)
Code(5) with 12V system
Chip Protect without 12V L H L X X L H X
system (6)
Chip Unprotect without 12V L H L X X H H X
system (6)
V erify Chip Protect/Unprotect L L H X H X H Code(5)
without 12V system (7)
Reset X X X X X X X HIGH Z

D

OUT

DIN(3)

NOTES:

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.

2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.

3. Refer to Table 1 for valid Data-In during a write operation.

4. X can be VIL or VIH.

5. Code=00H means unprotected.
Code=01H means protected.

6. Refer to chip protect/unprotect algorithm and waveform.

Must issue "unlock for chip protect/unprotect" command before "chip protect/unprotect without 12V system" command.

7. The "verify chip protect/unprotect without 12V sysytem" is only following "chip protect/unprotect without 12V system"
command.

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MX29F022/022N

READ/RESET COMMAND

The read or reset operation is initiated by writing the
read/reset command sequence into the command reg­ister. Microprocessor read cycles retrieve array data.
The device remains enabled f or reads until the command
register contents are altered.

If program-fail or er ase-fail happen, the write of F0H will
reset the device to abort the operation. A valid com­mand must then be written to place the device in the
desired state.

SILICON-ID-READ COMMAND

Flash memories are intended for use in applications
where the local CPU alters memory contents. As such,
manufacturer and de vice codes must be accessible while
the device resides in the target system. PROM pro­grammers typically access signature codes by raising
A9 to a high voltage. However, multiplexing high volt­age onto address lines is not generally desired system
design practice.

SET-UP AUTOMATIC CHIP/SECTOR ERASE
COMMANDS

Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are f ollow ed by writing the
"set-up" command 80H. Two more "unlock" write cy­cles are then followed b y the chip erase command 10H.

The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the A u­tomatic Chip Erase. Upon ex ecuting the Automatic Chip
Erase, the device will automatically progr am and verify
the entire memory for an all-zero data pattern. When
the device is automatically verified to contain an all-z ero
pattern, a self-timed chip erase and verification begin.
The erase and verification operations are completed
when the data on Q7 is "1" at which time the device
returns to the Read mode. The system is not required
to provide any control or timing during these operations.

When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved f or the memory array(no
erase verify command is required).

The MX29F022T/B contains a Silicon-ID-Read opera­tion to supplement traditional PROM programming meth­odology. The operation is initiated by writing the read
silicon ID command sequence into the command regis­ter. Following the command write, a read cycle with
A1=VIL, A0=VIL retrieves the manuf acturer code of C2H.
A read cycle with A1=VIL, A0=VIH returns the device
code of 36H for MX29F022T,37H for MX29F022B.

TABLE 3. EXPANDED SILICON ID CODE

Pins A0 A1 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code(Hex)

Manufacture code VIL VIL 1 1 0 0 0 0 1 0 C2H
Device code VIHVIL0011011036H

for MX29F022T
Device code VIHVIL0011011137H
for MX29F022B
Chip Protection Verification X VIH 0 0 0 0 0 0 0 1 01H (Protected)

X VIH 0 0 0 0 0 0 0 0 00H (Unprotected)

If the Erase operation was unsuccessful, the data on
Q5 is "1"(see Table 4), indicating the erase operation of
exceed internal timing limit.

The automatic erase begins on the rising edge of the
last WE pulse in the command sequence and terminates
when the data on Q7 is "1" and the data on Q6 stops
toggling for two consecutive read cycles , at which time
the device returns to the Read mode.

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MX29F022/022N

SET-UP AUTOMATIC SECTOR ERASE
COMMANDS

The Automatic Sector Erase does not require the device
to be entirely pre-programmed prior to executing the
Automatic Set-up Sector Erase command and Automatic
Sector Erase command. Upon executing the Automatic
Sector Erase command, the device will automatically
program and verify the sector(s) memory for an all-zero
data pattern. The system does not require to provide
any control or timing during these operations.

When the sector(s) is automatically verified to contain
an all-zero pattern,a self-timed sector erase and verifi­cation begin. The erase and v erification operations are
complete when the data on Q7 is "1" and the data on Q6
stops toggling for two consecutiv e read cycles, at which
time the device returns to the Read mode. The system
does not required to provide any control or timing
during these operations.

When using the Automatic Sector Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achiev ed for the memory array
(no erase verification command is required). Sector
erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are f ollow ed by writing the
set-up command-80H. Two more "unlock" write cycles
are then followed by the sector erase command-30H.
The sector address is latched on the falling edge of WE,
while the command(data) is latched on the rising edge

of WE. Sector addresses selected are loaded into
internal register on the sixth falling edge of WE. Each
successive sector load cycle started by the falling edge
of WE must begin within 30us from the rising edge of
the preceding WE. Otherwise, the loading period ends
and internal auto sector erase cycle starts. (Monitor Q3
to determine if the sector erase timer window is still open,
see section Q3, Sector Erase Timer.) Any command
other than Sector Erase (30H) or Erase Suspend (B0H)
during the time-out period resets the device to read
mode.

ERASE SUSPEND

This command is only valid while the state machine is
executing Automatic Sector Erase operation, and
therefore will only be responded during Automatic/Sec­tor Erase operation. Writing the Erase Suspend com­mand during the Sector Erase time-out immediately ter­minates the time-out period and suspends the erase op­eration. After this command has been executed, the
command register will initiate erase suspend mode. The
state machine will return to read mode automatically af­ter suspend is ready. At this time, state machine only
allows the command register to respond to the Read
Memory Array , Erase Resume and Progr am commands.
The system can determine the status of the program
operation using the Q7 or Q6 status bits, just as in the
standard program operation. After an erase-suspendend
program operation is complete, the system can once
again read array data within non-suspended sectors.

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MX29F022/022N

T able 4. Write Operation Status

Status Q7 Q6 Q5 Q3 Q2

Note1 Note2

Byte Program in Auto Program Algorithm Q7 Toggle 0 N/A No Toggle
Auto Erase Algorithm 0 Toggle 0 1 Toggle

Erase Suspend Read 1 N o 0 N/A Toggle

In Progress (Erase Suspended Sector) Toggle

Erase Suspended Mode Erase Suspend Read Data Data Data Data Data

(Non-Erase Suspended Sector)
Erase Suspend Program Q7 Toggle 0 N/A N/A

Byte Program in Auto Program Algorithm Q7 Toggle 1 N/A No Toggle
Exceeded Auto Erase Algorithm 0 Toggle 1 1 Toggle
Time Limits Erase Suspend Program Q7 Toggle 1 N/A N/A

Note:

1.Q7 and Q2 require a valid address when reading status inf ormation. Refer to the appropriate subsection f or further
details.

2.Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.
See "Q5:Exceeded Timing Limits " f or more information.

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MX29F022/022N

ERASE RESUME

This command will cause the command register to clear
the suspend state and return back to Sector Erase mode
but only if an Erase Suspend command was pre viously
issued. Erase Resume will not have any effect in all
other conditions.Another Erase Suspend command can
be written after the chip has resumed erasing.

SET-UP AUTOMATIC PROGRAM COMMANDS

T o initiate A utomatic Program mode, A three-cycle com­mand sequence is required. There are two "unlock" write
cycles. These are f ollowed by writing the Automatic Pro­gram command A0H.

Once the Automatic Program command is initiated, the
next WE pulse causes a transition to an active program­ming operation. Addresses are latched on the falling
edge, and data are internally latched on the rising
edge of the WE pulse. The rising edge of WE also be­gins the programming operation. The system does not
require to provide further controls or timings. The de­vice will automatically provide an adequate internally
generated program pulse and v erify margin.

If the program opetation was unsuccessful, the data on
Q5 is "1", indicating the program operation of internally
exceed timing limit. The automatic programming opera­tion is complete when the data read on Q6 stops tog­gling for two consecutive read cycles and the data on
Q7 and Q6 are equivalent to data written to these two
bits, at which time the device returns to the Read
mode(no program verify command is required).

WRITE OPERA TION STATUS D ATA POLLING-Q7

While the Automatic Erase algorithm is in operation, Q7
will read "0" until the erase operation is compete. Upon
completion of the erase operation, the data on Q7 will
read "1". The Data P olling feature is valid after the rising
edge of the secone WE pulse of two write pulse se­quences.

The Data Polling f eature is active during Automatic Pro­gram/Erase algorithm or sector erase time-out.(see sec­tion Q3 Sector Erase Timer)

Q6:Toggle BIT I

The MX29F022T/B features a "Toggle Bit" as a method
to indicate to the host system that the Auto Program/
Erase algorithms are either in progress or complete.

During an Automatic Program or Erase algorithm op­eration, successive read cycles to any address cause
Q6 to toggle. The system may use either OE or CE to
control the read cycles. When the operation is complete,
Q6 stops toggling.

After an erase command sequence is written, if the chip
is protected, Q6 toggles and returns to reading array
data.

The system can use Q6 and Q2 together to determine
whether a sector is actively erasing or is erase sus­pended. When the de vice is actively erasing (that is, the
Automatic Erase algorithm is in progress), Q6 toggling.
When the device enters the Erase Suspend mode, Q6
stops toggling. However, the system must also use Q2
to determine which sectors are erasing or erase-sus­pended. Alternatively, the system can use Q7(see the
subsection on Q7:Data Polling).

The MX29F022T/B also features Data Polling as a
method to indicate to the host system that the Automatic
Program or Erase algorithms are either in progress or
completed.

While the Automatic Programming algorithm is in
operation, an attempt to read the device will produce
the complement data of the data last written to Q7. Upon
completion of the Automatic Program Algorithm an
attempt to read the device will produce the true data last
written to Q7. The Data Polling f eature is v alid after the
rising edge of the second WE pulse of the two write pulse
sequences.

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If a program address falls within a protected sector, Q6
toggles for approximately 2us after the progr am com­mand sequence is written, then returns to reading array
data.

Q6 also toggles during the erase-suspend-program
mode, and stops toggling once the Automatic Program
algorithm is complete.

The Write Operation Status table shows the outputs f or
Toggle Bit I on Q6. Ref er to the toggle bit algorithmg.

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MX29F022/022N

Q2:Toggle Bit II

The "T oggle Bit II" on Q2, when used with Q6, indicates
whether a particular sector is actively eraseing (that is,
the Automatic Erase alorithm is in process), or whether
that sector is erase-suspended. T oggle Bit I is v alid after
the rising edge of the final WE pulse in the command
sequence.

Q2 toggles when the system reads at addresses within
those sectors that have been selected f or erasure. (The
system may use either OE or CE to control the read
cycles.) But Q2 cannot distinguish whether the sector
is actively erasing or is erase-suspended. Q6, by
comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both
status bits are required for sectors and mode
information. Ref er to Table 4 to compare outputs f or Q2
and Q6.

Reading Toggle Bits Q6/ Q2

Refer to the toggle bit algorithm for the following
discussion. Whenever the system initially begins
reading toggle bit status, it must read Q7-Q0 at least
twice in a row to determine whether a toggle bit is
toggling. Typically, the system w ould note and store the
value of the toggle bit after the first read. After the
second read, the system would compare the new value
of the toggle bit with the first. If the toggle bit is not
toggling, the device has completed the program or erase
operation. The system can read array data on Q7-Q0
on the following read cycle.

Q5 through successive read cycles, determining the
status as described in the previous paragraph.
Alternatively, it may choose to perform other system
tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation(top of the toggle bit algorithm
flow chart).

Q5

Exceeded Timing Limits

Q5 will indicate if the program or erase time has
exceeded the specified limits(internal pulse count).
Under these conditions Q5 will produce a "1". This
time-out condition indicates that the program or erase
cycle was not successfully completed. Data Polling and
Toggle Bit are the only operating functions not of the
device under this condition.

If this time-out condition occurs during sector erase
operation, it specifies that a particular sector is bad and
it may not be reused. However, other sectors are still
functional and may be used for the program or erase
operation. The device must be reset to use other
sectors. Write the Reset command sequence to the
device, and then execute program or erase command
sequence. This allows the system to continue to use
the other active sectors in the device .

If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or
combination of sectors are bad.

However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of Q5 is
high (see the section on Q5). If it is , the system should
then determine again whether the toggle bit is toggling,
since the toggle bit may have stopped toggling just as
Q5 went high. If the toggle bit is no longer toggling, the
device has successfuly completed the program or erase
operation. If it is still toggling, the device did not
complete the operation successfully, and the system
must write the reset command to return to reading array
data.

The remaining scenario is that system initially determines
that the toggle bit is toggling and Q5 has not gone high.
The system may continue to monitor the toggle bit and

P/N:PM0556

If this time-out condition occurs during the byte
programming operation, it specifies that the entire
sector containing that byte is bad and this sector maynot
be reused, (other sectors are still functional and can be
reused).

The time-out condition may also appear if a user tries to
program a non blank location without erasing. In this
case the device locks out and never completes the
Automatic Algorithm operation. Hence, the system nev er
reads a valid data on Q7 bit and Q6 never stops
toggling. Once the Device has exceeded timing limits,
the Q5 bit will indicate a "1". Please note that this is not
a device failure condition since the device was
incorrectly used.

REV. 1.1, JUN. 14, 2001

11

MX29F022/022N

Q3

Sector Erase Timer

After the completion of the initial sector erase command
sequence th sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data Polling
and Toggle Bit are valid after the initial sector erase
command sequence.

If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, Q3 may be
used to determine if the sector erase timer window is
still open. If Q3 is high ("1") the inter nally controlled
erase cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or
Toggle Bit. If Q3 is low ("0"), the device will accept
additional sector erase commands. To insure the
command has been accepted, the system software
should check the status of Q3 prior to and following each
subsequent sector erase command. If Q3 were high
on the second status check, the command may not ha ve
been accepted.

DATA PROTECTION

POWER SUPPLY DECOUPLING

In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected be­tween its VCC and GND.

CHIP PROTECTION WITH 12V SYSTEM

The MX29F022T/B features hardware chip protection,
which will disable both program and erase operations.
T o activate this mode , the programming equipment must
force VID on address pin A9 and control pin OE, (sug­gest VID = 12V) A6 = VIL and CE = VIL.(see Table 2)
Programming of the protection circuitry begins on the
falling edge of the WE pulse and is terminated on the
rising edge. Please refer to chip protect algorithm and
waveform.

To verify programming of the protection circuitry, the
programming equipment must f orce VID on address pin
A9 ( with CE and OE at VIL and WE at VIH. When A1=1,
it will produce a logical "1" code at device output Q0 for
the protected status. Otherwise the device will produce
00H for the unprotected status. In this mode, the
addresses,except for A1, are in "don't care" state.
Address locations with A1 = VIL are reserved to read
manufacturer and device codes .(Read Silicon ID)

The MX29F022T/B is designed to offer protection
against accidental erasure or programming caused by
spurious system level signals that ma y exist during power
transition. During power up the device automatically
resets the state machine in the Read mode. In addition,
with its control register architecture, alteration of the
memory contents only occurs after successful
completion of specific command sequences. The
device also incorporates several features to prevent
inadvertent write cycles resulting from VCC power-up
and power-down transition or system noise .

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns(typical) on CE or WE will
not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE = VIL, CE =
VIH or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.

It is also possible to determine if the chip is protected in
the system by writing a Read Silicon ID command.
Perf orming a read operation with A1=VIH, it will produce
a logical "1" at Q0 for the protected status.

CHIP UNPROTECT WITH 12V SYSTEM

The MX29F022T/B also features the chip unprotect
mode, so that all sectors are unprotected after chip
unprotect is completed to incorporate any changes in
the code.

T o activate this mode , the programming equipment must
force VID on control pin OE and address pin A9. The
CE pins must be set at VIL. Pins A6 must be set to
VIH.(see Table 2) Refer to chip unprotect algorithm and
waveform for the chip unprotect algorithm. The
unprotection mechanism begins on the falling edge of
the WE pulse and is terminated on the rising edge.

P/N:PM0556

REV. 1.1, JUN. 14, 2001

12

MX29F022/022N

It is also possible to determine if the chip is unprotected
in the system by writing the Read Silicon ID command.
Perf orming a read operation with A1=VIH, it will produce
00H at data outputs(Q0-Q7) for an unprotected chip. It
is noted that all sectors are unprotected after the chip
unprotect algorithm is complete.

CHIP PROTECTION WITHOUT 12V SYSTEM

The MX29F022T/B also feature a hardware chip
protection method in a system without 12V power
suppply. The programming equipment do not need to
supply 12 volts to protect all sectors. The details are
shown in chip protect algorithm and wavef orm.

CHIP UNPROTECT WITHOUT 12V SYSTEM

The MX29F022T/B also feature a hardware chip
unprotection method in a system without 12V power
supply. The programming equipment do not need to
supply 12 volts to unprotect all sectors. The details are
shown in chip unprotect algorithm and wavef orm.

POWER-UP SEQUENCE

ABSOLUTE MAXIMUM RATINGS

RATING VALUE
Ambient Operating Temperature 0oC to 70oC
Storage T emperature -65oC to 125oC
Applied Input V oltage -0.5V to 7.0V
Applied Output V oltage -0.5V to 7.0V
VCC to Ground Potential -0.5V to 7.0V
A9 -0.5V to 13.5V

NOTICE:

Stresses greater than those listed under ABSOLUTE MAXI­MUM RATINGS may cause permanent damage to the de­vice. This is a stress rating only and functional operational
sections of this specification is not implied. Exposure to ab­solute maximum rating conditions for extended period may
affect reliability.

NOTICE:

Specifications contained within the following tables are sub­ject to change.

The MX29F022T/B powers up in the Read only mode.
In addition, the memory contents may only be altered
after successful completion of a two-step command
sequence. Vpp and Vcc power up sequence is not
required.

P/N:PM0556

REV. 1.1, JUN. 14, 2001

13

MX29F022/022N

Temporary Sector Unprotect Operation (only for 29F022T/B)

Start

RESET = VID (Note 1)

Perform Erase or Program Operation

Operation Completed

RESET = VIH

Temporary Sector Unprotect Completed(Note 2)

Note :

1. All protected sectors are temporary unprotected.
VID=11.5V~12.5V

2. All previously protected sectors are protected again.

P/N:PM0556

REV. 1.1, JUN. 14, 2001

14

MX29F022/022N

TEMPORARY SECTOR UNPROTECT

Parameter Std. Description T est Setup AllSpeed Options Unit
tVIDR VID Rise and Fall Time (See Note) Min 500 ns
tRSP RESET Setup Time f or Temporary Sector Unprotect Min 4 us

Note:
Not 100% tested

Temporary Sector Unprotect Timing Diagram (only for 29F022T/B)

12V

RESET

CE

WE

0 or 5V

tVIDR

tRSP

Program or Erase Command Sequence

0 or 5V

tVIDR

P/N:PM0556

REV. 1.1, JUN. 14, 2001

15

MX29F022/022N

AC CHARACTERISTICS

Parameter Std Description Test Setup All Speed Options Unit
tREAD Y RESET PIN Low (Not During Automatic Algorithms) MAX 5 00 ns

to Read or Write (See Note)
tRP1 RESET Pulse Width (During Automatic Algorithms) MIN 10 us
tRP2 RESET Pulse Width (NO T During Automatic Algorithms) MIN 50 0 ns
tR H RESET High Time Before Read(See Note) MIN 0 ns

Note:
Not 100% tested

RESET TIMING WAVFORM(only for 29F002T/B)

CE, OE

RESET

RESET

tRH

tRP2

tReady

Reset Timing NOT during Automatic Algorithms

tRP1

Reset Timing during Automatic Algorithms

P/N:PM0556

REV. 1.1, JUN. 14, 2001

16

MX29F022/022N

CAPACITANCE TA = 25oC, f = 1.0 MHz

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS
CIN1 Input Capacitance 8 pF VIN = 0V
CIN2 Control Pin Capacitance 12 pF VIN = 0V
COUT Output Capacitance 12 pF VOUT = 0V

READ OPERATION

DC CHARACTERISTICS TA = 0

o

C TO 70oC, VCC = 5V ± 10% (VCC=5V ± 5% for 29F022/022N-55)

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS

ILI Input Leakage Current 1 mA VIN = GND to VCC
ILO Output Leakage Current 10 mA VOUT = GND to VCC
ISB1 Standby VCC current 1 mA CE = VIH
ISB2 1 5 uA CE = VCC + 0.3V
ICC1 Operating VCC current 30 mA IOUT = 0mA, f=5MHz
ICC2 50 mA IOUT = 0mA, f=10MHz
VIL Input Low Voltage -0.3(NOTE1) 0.8 V
VIH Input High Voltage 2.0 VCC + 0.3 V
VOL Output Low Voltage 0.45 V IOL = 2.1mA
VOH1 Output High V oltage(TTL) 2.4 V IOH =-2mA
VOH2 Output High V oltage(CMOS)VCC-0.4 V IOH =-100uA,VCC=VCC

MIN

NOTES:

1.VIL min. = -1.0V for pulse width is equal to or less than 50 ns.
VIL min. = -2.0V for pulse width is equal to or less than 20 ns.

2.VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns
If VIH is ov er the specified maximum v alue, read operation cannot be guar anteed.

P/N:PM0556

REV. 1.1, JUN. 14, 2001

17

MX29F022/022N

AC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V

29F022T/B-55 29F022T/B-70

SYMBOL PARAMETER MIN. MAX. MIN. MAX. UNIT CONDITIONS

tACC Address to Output Delay 55 70 ns CE=OE=VIL
tCE CE to Output Delay 55 70 ns OE=VIL
tOE OE to Output Delay 25 30 ns CE=VIL
tDF OE High to Output Float (Note1) 0 20 0 20 ns CE=VIL
tOH Address to Output hold 0 0 ns CE=OE=VIL

29F022T/B-90 29F022T/B-120

SYMBOL P ARAMETER MIN. MAX. MIN. MAX. UNIT CONDITIONS

tACC Address to Output Delay 90 120 ns CE=OE=VIL
tCE CE to Output Delay 90 120 ns OE=VIL
tOE OE to Output Delay 40 50 ns CE=VIL
tDF OE High to Output Float (Note1) 0 30 0 30 ns CE=VIL
tOH Address to Output hold 0 0 ns CE=OE=VIL

TEST CONDITIONS:

±±

± 10%(VCC = 5V

±±

±±

± 5% for 29F022T/B-55)

±±

•Input pulse levels: 0.45V/2.4V f or 70ns max.

: 0V/3V for 55ns speed grade.

•Input rise and f all times: < 10ns for 70ns max.

: < 5ns for 55ns speed grade.

•Output load: 1 TTL gate + 100pF(Including scope and jig) f or 70ns max.

: 1 TTL gate + 50pF(Including scope and jig) for 55ns speed grade.

•Reference levels f or measuring timing : 0.8V/2.0V or 70ns max.

:1.5V/1.5V for 55ns speed grade .

NOTE:

1.tDF is defined as the time at which the output achieves the
open circuit condition and data is no longer driven.

P/N:PM0556

REV. 1.1, JUN. 14, 2001

18

READ TIMING WA VEFORMS

MX29F022/022N

A0~17

CE

WE

OE

DATA

Q0~7

VIH

ADD Valid

VIL

tCE

VIH

VIL

VIH

VIL

VIH

VIL

HIGH Z HIGH Z

VOH

VOL

tACC

tOE

DATA V alid

tDF

tOH

P/N:PM0556

REV. 1.1, JUN. 14, 2001

19

MX29F022/022N

COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION

DC CHARACTERISTICS TA = 0

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS
ICC1 (Read) Operating VCC Current 30 mA IOUT=0mA, f=5MHz
ICC2 50 mA IOUT=0mA, F=10MHz
ICC3 (Program) 50 mA In Programming
ICC4 (Erase) 50 mA In Erase
ICCES VCC Erase Suspend Current 2 mA CE=VIH, Erase Suspended

NOTES:

1. VIL min. = -0.6V for pulse width is equal to or less than 20ns.

2. If VIH is ov er the specified maximum v alue , programming oper ation cannot be guranteed.

3. ICCES is specified with the device de-selected. If the device is read during erase suspend mode , current draw is

the sum of ICCES and ICC1 or ICC2.

4. All current are in RMS unless otherwise noted.

o

C to 70oC, VCC = 5V

± ±

± 10%(VCC = 5V

± ±

± ±

± 5% for 29F022/022N-55)

± ±

P/N:PM0556

REV. 1.1, JUN. 14, 2001

20

MX29F022/022N

AC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V

29F022T/B-55(Note2) 29F022T/B-70 29F022T/B-90 29F022T/B-12

SYMBOL PARAMETER MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. UNIT

tOES OE setup time 0 0 0 0 ns
tCWC Command programming cycle 7 0 7 0 90 12 0 n s
tCEP WE programming pulse width 45 45 45 5 0 n s
tCEPH1 WE programming pluse width High 20 20 20 2 0 ns
tCEPH2 WE programming pluse width High 20 20 20 2 0 ns
tAS Address setup time 0 0 0 0 n s
tAH Address hold time 45 45 45 50 ns
tDS Data setup time 20 30 45 50 ns
tDH Data hold time 0 0 0 0 ns
tCESC CE setup time before command write 0 0 0 0 ns
tDF Output disable time (Note 1) 20 30 40 40 n s
tAETC Total erase time in auto chip erase 3(TYP.) 24 3(TYP.) 24 3(TYP.) 2 4 3(TYP.) 24 s
tAETB Total erase time in auto sector erase 1(TYP.)8 1(TYP.) 8 1(TYP.) 8 1(TYP.)8 s
tAVT Total programming time in auto verify 7(TYP.) 21 0 7(TYP.) 21 0 7(TYP.) 21 0 7(TYP.) 21 0 us

(Byte Program time)
tBAL Sector address load time 1 0 0 1 00 1 00 10 0 u s
tCH CE Hold Time 0 0 0 0 us
tCS CE setup to WE going low 0 0 0 0 us
tVLHT Voltge Transition Time 4 4 4 4 us
tOESP OE Setup Time to WE Active 4 4 4 4 us
tWPP1 Write pulse width for chip protect 10 10 10 10 us
tWPP2 Write pulse width for chip unprotect 12 12 12 12 ms

± ±

± 10%(VCC=5V

± ±

±±

±5% for 29F022T/B-55)

±±

NOTES:

1.tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.

2.Under condition of VCC=5V±5%,CL=50pF, VIH/VIL=3.0V/0V, VOH/VOL=1.5V/1.5V,IOL=2mA,IOH=-2mA.

P/N:PM0556

21

REV. 1.1, JUN. 14, 2001

SWITCHING TEST CIRCUITS

MX29F022/022N

DEVICE UNDER

1.6K ohm

TEST

CL

1.2K ohm

DIODES=IN3064

OR EQUIVALENT

CL=100pF Including jig capacitance for 29F022/022N-70,
29F022/022N-90,29F022/022N-12
CL=50pF Including jig capacitance for 29F022/022N-55

SWITCHING TEST WA VEFORMS(I) for MX29F022/022N-70/90/120

2.4V

0.45V
INPUT

2.0V 2.0V

TEST POINTS

0.8V

0.8V

+5V

OUTPUT

AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".
Input pulse rise and fall times are <20ns.

SWITCHING TEST WA VEFORMS(I) for MX29F022/022N-55

3.0V
TEST POINTS

22

P/N:PM0556

1.5V

0V

AC TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0".
Input pulse rise and fall times are < 5ns.

INPUT

1.5V

OUTPUT

REV. 1.1, JUN. 14, 2001

COMMAND WRITE TIMING WAVEFORM

MX29F022/022N

VCC

ADD

A0~17

WE

CE

OE

DATA

Q0-7

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

5V

ADD Valid

tAS

tOES

tCS tCH

tCEP

tDS

tAH

tCEPH1

tCWC

tDH

DIN

P/N:PM0556

REV. 1.1, JUN. 14, 2001

23

AUTOMATIC PROGRAMMING TIMING WAVEFORM

MX29F022/022N

One byte data is programmed. Verifying in fast
algorithm and additional programming by external
control are not required because these operations are
executed automatically by internal control circuit.
Programming completion can be verified by DATA

AUTOMATIC PROGRAMMING TIMING WAVEFOR

Vcc 5V

A11~A17

A0~A10

WE

CE

OE

tAS

555H

tAH

tCEP

tDS tDH

2AAH

tCWC

tCEPH1

polling and toggle bit checking after automatic
verification starts. Device outputs DATA during
programming and D A TA after programming on Q7.(Q6 is
for toggle bit; see toggle bit, DATA polling, timing
waveform)

ADD Valid

555H

ADD Valid

tAVT

tCESC

tDF

Q0~Q1

,Q4(Note 1)

Q7

Command In

Command In Command InCommand In Data In

Command #AAH Command #55H

(Q0~Q7)

Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2:Toggle bit

Command InCommand In Data In

Command #A0H

DATA

DATA polling

DATADATA

tOE

P/N:PM0556

REV. 1.1, JUN. 14, 2001

24

AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART

ST ART

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data A0H Address 555H

Write Program Data/Address

MX29F022/022N

Invalid
Command

Toggle Bit Checking
Q6 not Toggled

NO

Verify Byte Ok

Auto Program Completed

YES

YES

NO

Q5 = 1

YES

Reset

Auto Program Exceed
Timing Limit

NO

.

P/N:PM0556

REV. 1.1, JUN. 14, 2001

25

TOGGLE BIT ALGORITHM

MX29F022/022N

ST ART

Read Q7~Q0

Read Q7~Q0

Toggle Bit Q6

=Toggle?

NO

Program/Erase Operation Not

Complete, Write Reset Command

Q5=1?

Read Q7~Q0 Twice

Toggle Bit Q6

=Toggle?

(Note 1)

NO

YES

YES

(Note 1,2)

YES

Program/Erase Operation Complete

P/N:PM0556

Notes:

1.Read toggle bit Q6 twice to determine whether or not it is toggle. See te xt.

2.Recheck toggle bit Q6 because it may stop toggling as Q5 changes to "1". See text.

REV. 1.1, JUN. 14, 2001

26

AUTOMATIC CHIP ERASE TIMING WAVEFORM

MX29F022/022N

All data in chip are erased. External erase verification is
not required because data is erased automatically by
internal control circuit. Erasure completion can be
verified by DATA polling and toggle bit checking after

AUTOMA TIC CHIP ERASE TIMING WA VEFORM

Vcc 5V

A11~A17

A0~A10

555H

2AAH

555H

tAS

WE

tAH

CE

automatic erase starts. Device outputs "0" during
erasure and 1 after erasure on Q7.(Q6 is for toggle bit;
see toggle bit, DAT A polling, timing wa v ef orm)

555H

2AAH 555H

tCWC

tCEPH1

tAETC

OE

Q0,Q1,

Q4(Note 1)

Q7

tCEP

tDS tDH

Command In

Command In Command InCommand In

Command #AAH Command #55H

Command InCommand In

Command #80H

Command In

Command In

Command #AAH

(Q0~Q7)

Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

Command In

Command In

Command #55H

Command In

DATA polling

Command In

Command #10H

P/N:PM0556

REV. 1.1, JUN. 14, 2001

27

AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART

ST ART

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

MX29F022/022N

Invalid
Command

Write Data 10H Address 555H

Toggle Bit Checking
Q6 not Toggled

YES

NO

DATA Polling

Q7 = 1

YES

Auto Chip Erase Completed

NO

Q5 = 1

YES

Reset

Auto Chip Erase Exceed
Timing-Limit

NO

.

P/N:PM0556

REV. 1.1, JUN. 14, 2001

28

AUTOMATIC SECTOR ERASE TIMING WAVEFORM

MX29F022/022N

Sector data indicated by A13 to A17 are erased. Exter­nal erase verification is not required because data are
erased automatically by internal control circuit. Erasure
completion can be verified by DAT A polling and toggle bit

AUT OMA TIC SECT OR ERASE TIMING W A VEFORM

Vcc 5V

A13~A17

A0~A10

WE

CE

555H 2AAH 2AAH

tAS

tAH

555H 555H

checking after automatic erase starts. De vice outputs 0
during erasure and 1 after erasure on Q7.(Q6 is for toggle
bit; see toggle bit, D AT A polling, timing wav eform)

Sector

Address0

tCWC

tCEPH1

Sector

Address1

Sector

Addressn

tBAL

tAETB

Q0,Q1,

Q4(Note 1)

P/N:PM0556

OE

Q7

tCEP

tDS

tDH

Command InCommand

Command

In

(Q0~Q7)

In

Command InCommand

Command InCommand

In

Command InCommand

Command InCommand InCommand InCommand

In

In

Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

29

Command

In

Command

In

In

Command

In

Command #30HCommand #30HCommand #30HCommand #55HCommand #AAHCommand #80HCommand #55HCommand #AAH

DATA polling

REV. 1.1, JUN. 14, 2001

AUT OMA TIC SECTOR ERASE ALGORITHM FLO WCHART

ST ART

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 30H Sector Address

MX29F022/022N

Toggle Bit Checking

Q6 T oggled ?

YES

Load Other Sector Addrss If Necessary
(Load Other Sector Address)

Last Sector
to Erase

Time-out Bit

Checking Q3=1 ?

YES

Toggle Bit Checking

Q6 not Toggled

YES

DATA Polling

Q7 = 1

NO

NO

YES

NO

NO

Invalid Command

Q5 = 1

NO

YES

P/N:PM0556

Auto Sector Erase Completed

Reset

Auto Sector Erase Exceed
Timing Limit

REV. 1.1, JUN. 14, 2001

30

ERASE SUSPEND/ERASE RESUME FLOWCHAR T

Write Data B0H

MX29F022/022N

ST AR T

Toggle Bit checking Q6

not toggled

YES

Read Array or

Program

Reading or

Programming End

YES

Write Data 30H

Continue Erase

Another

Erase Suspend ?

YES

NO

NO

NO

P/N:PM0556

REV. 1.1, JUN. 14, 2001

31

MX29F022/022N

TIMING WAVEFORM FOR CHIP PRO TECTION FOR SYSTEM WITH 12V

A1

A6

12V

5V

A9

12V

5V

OE

WE

CE

tVLHT

tVLHT

tWPP 1

tOESP

Verify

tVLHT

Data

TIMING WAVEFORM FOR CHIP UNPRO TECTION FOR SYSTEM WITH 12V

A1

12V

5V

A9

A6

12V

5V

OE

WE

CE

tVLHT

tVLHT

tWPP 2

tOESP

01H

tOE

Verify

tVLHT

P/N:PM0556

Data

00H

tOE

REV. 1.1, JUN. 14, 2001

32

CHIP PRO TECTION ALGORITHM FOR SYSTEM WITH 12V

Device Failed

MX29F022/022N

ST ART

PLSCNT=1

OE=VID,A9=VID,CE=VIL

A6=VIL

Activate WE Pulse

Time Out 10us

Set WE=VIH, CE=OE=VIL
A9 should remain VID

No

PLSCNT=32?

Yes

Device Failed

No

Read from Sector

Addr=SA, A1=1

Data=01H?

Yes

Remove VID from A9

Write Reset Command

Chip Protection

Complete

P/N:PM0556

REV. 1.1, JUN. 14, 2001

33

CHIP UNPRO TECTION ALGORITHM FOR SYSTEM WITH 12V

ST ART

PLSCNT=1

Set OE=A9=VID
CE=VIL,A6=1

Activate WE Pulse

MX29F022/022N

Time Out 12ms

Set OE=CE=VIL

A9=VID,A1=1

Read Data from Device

Data=00H?

Yes

Remove VID from A9

Write Reset Command

Chip Unprotect

Complete

No

Increment

PLSCNT

No

PLSCNT=1000?

Yes

Device Failed

P/N:PM0556

REV. 1.1, JUN. 14, 2001

34

MX29F022/022N

TIMING WAVEFORM FOR CHIP PROTECTION/UNPR OTECTION FOR SYSTEM WITHOUT 12V

A6,A9 & sector address are don't care

A1

6th command
cycle : 555H

X

'0'

7th command
cycle

during toggle bit polling period, or just
be kept valid value in read window. Protected Verify Reset to Read Mode

'1'

X=Don't care

X

A6

A9

OE

WE

CE

(Q0-Q7)

X

X

'1'

'0'

tAS tAH

tCEP

20H Dout Dout Dout Dout F0H

(Note 2)

X

'0'

XX

X(2)

X

X

A6,A9 and Sector Addr. should be latched on the falling e
dge of WE or CE , ehich occurs last, for WSM reference

Toggle Bit Polling

tACC

tOE

tCE

Note1: Don't care except F0H.
Note2: Protection:7th command cycle A6 goes low.

Unprotection: 7th command cycle A6 goes high.

Note3: Protection verify:01H

Un-protection verify:00H

Note4: Must issue "unlock f or chip protection/unprotection" command bef ore chip protection/un-protection f or a

system without 12V provided.

P/N:PM0556

35

REV. 1.1, JUN. 14, 2001

CHIP PRO TECTION ALGORITHM FOR SYSTEM WITHOUT 12V

ST ART

PLSCNT=1

MX29F022/022N

Increment PLSCNT

No

PLSCENT=32?

Yes

Device Failed

Write "Unlock for chip protect/unprotect"

No

Command

OE=VID,A9=VID

CE=VIL,A6=VIL

Activate WE Pulse to start

Data don't care

Toggle bit checking

Q6 not Toggle

Yes

Set CE=OE=VIL

A9=VIH

Read from Sector
Addr. =SA,A1=1

Data=01H?

Yes

Write Reset Command

No

.

P/N:PM0556

Chip Protection

Complete

REV. 1.1, JUN. 14, 2001

36

MX29F022/022N

CHIP UNPRO TECTION ALGORITHM FOR SYSTEM WITHOUT 12V

ST ART

PLSCNT=1

Write "unlock for chip protect/unprotect"

Command (Table 1)

Set OE=A9=VIH
CE=VIL,A6=1

Activate WE Pulse to start

Data don't care

No

Toggle bit checking

Q6 not Toggled

Yes

Increment

PLSCNT

Set OE=CE=VIL

A9=VIH,A1=1

Read Data from Device

Data=00H?

Yes

Write Reset Command

Chip Unprotect

Complete

No

No

PLSCNT=1000?

Yes

Device Failed

P/N:PM0556

REV. 1.1, JUN. 14, 2001

37

ID CODE READ TIMING WAVEFORM MODE

MX29F022/022N

VCC

ADD

A9

A1

ADD

A2-A8

A10-A17

CE

WE

OE

DATA

Q0-Q7

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

5V

VID
VIH

VIL

tACC

tCE

tOE

DATA OUT

C2H

tOH

tACC

tDF

tOH

DATA OUT
36H/37H

P/N:PM0556

REV. 1.1, JUN. 14, 2001

38

MX29F022/022N

ORDERING INFORMATION

PLASTIC PACKA GE

PART NO. ACCESS TIME OPERATING CURRENT STANDBY CURRENT PACKA GE

(ns) MAX.(mA) MAX.(uA)

MX29F022TPC-55 55 30 5 32 Pin PDIP
MX29F022TPC-70 70 30 5 32 Pin PDIP
MX29F022TPC-90 90 30 5 32 Pin PDIP
MX29F022TPC-12 120 30 5 32 Pin PDIP
MX29F022TTC-55 55 30 5 32 Pin TSOP

MX29F022TTC-70 70 30 5 32 Pin TSOP

MX29F022TTC-90 90 30 5 32 Pin TSOP

MX29F022TTC-12 120 30 5 32 Pin TSOP

MX29F022TQC-55 55 30 5 32 Pin PLCC
MX29F022TQC-70 70 30 5 32 Pin PLCC
MX29F022TQC-90 90 30 5 32 Pin PLCC
MX29F022TQC-12 120 30 5 32 Pin PLCC
MX29F022BPC-55 55 30 5 32 Pin PDIP
MX29F022BPC-70 70 30 5 32 Pin PDIP
MX29F022BPC-90 90 30 5 32 Pin PDIP
MX29F022BPC-12 120 30 5 32 Pin PDIP
MX29F022BTC-55 55 30 5 32 Pin TSOP

MX29F022BTC-70 70 30 5 32 Pin TSOP

MX29F022BTC-90 90 30 5 32 Pin TSOP

MX29F022BTC-12 120 30 5 32 Pin TSOP

MX29F022BQC-70 70 30 5 32 Pin PLCC
MX29F022BQC-90 90 30 5 32 Pin PLCC
MX29F022BQC-12 120 30 5 32 Pin PLCC
MX29F022NTPC-55 55 30 5 32 Pin PDIP
MX29F022NTPC-70 70 30 5 32 Pin PDIP
MX29F022NTPC-90 90 30 5 32 Pin PDIP
MX29F022NTPC-12 120 30 5 32 Pin PDIP

(Normal Type)

(Normal Type)

(Normal Type)

(Normal Type)

(Normal Type)

(Normal Type)

(Normal Type)

(Normal Type)

P/N:PM0556

REV. 1.1, JUN. 14, 2001

39

MX29F022/022N

PART NO. ACCESS TIME OPERATING CURRENT STANDBY CURRENT PACKA GE

(ns) MAX.(mA) MAX.(uA)

MX29F022NTTC-55 55 3 0 5 32 Pin TSOP

(Normal Type)

MX29F022NTTC-70 70 3 0 5 32 Pin TSOP

(Normal Type)

MX29F022NTTC-90 90 3 0 5 32 Pin TSOP

(Normal Type)

MX29F022NTTC-12 120 30 5 32 Pin TSOP

(Normal Type)
MX29F022NTQC-55 55 30 5 32 Pin PLCC
MX29F022NTQC-70 70 30 5 32 Pin PLCC
MX29F022NTQC-90 90 30 5 32 Pin PLCC
MX29F022NTQC-12 120 30 5 32 Pin PLCC
MX29F022NBPC-55 55 30 5 32 Pin PDIP
MX29F022NBPC-70 70 30 5 32 Pin PDIP
MX29F022NBPC-90 90 30 5 32 Pin PDIP
MX29F022NBPC-12 120 30 5 32 Pin PDIP
MX29F022NBTC-55 55 30 5 32 Pin TSOP

(Normal Type)
MX29F022NBTC-70 70 30 5 32 Pin TSOP

(Normal Type)
MX29F022NBTC-90 90 30 5 32 Pin TSOP

(Normal Type)
MX29F022NBTC-12 120 30 5 32 Pin TSOP

(Normal Type)
MX29F022NBQC-70 70 30 5 32 Pin PLCC
MX29F022NBQC-90 90 30 5 32 Pin PLCC
MX29F022NBQC-12 120 30 5 32 Pin PLCC

P/N:PM0556

REV. 1.1, JUN. 14, 2001

40

MX29F022/022N

ERASE AND PROGRAMMING PERFORMANCE(1)

LIMITS

PARAMETER MIN. TYP.(2) MAX.(3) UNITS

Sector Erase Time 1 8 s
Chip Erase Time 3 24 s
Byte Programming Time 7 210 us
Chip Programming Time 3.5 10.5 sec
Erase/Program Cycles 100,000 Cycles

Note: 1.Not 100% Tested, Excludes external system lev el ov er head.

2.T ypical v alues measured at 25°C,5V.

3.Maximum value measured at 25°C,4.5V.

LATCHUP CHARACTERISTICS

MIN. MAX.

Input Voltage with respect to GND on all pins except I/O pins -1.0V 13.5V
Input Voltage with respect to GND on all I/O pins -1.0V Vcc + 1.0V
Current -100mA +100mA
Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.

DATA RETENTION

PARAMETER MIN. UNIT

Data Retention Time 20 Years

P/N:PM0556

REV. 1.1, JUN. 14, 2001

41

PACKAGE INFORMATION

32-PIN PLASTIC DIP

MX29F022/022N

P/N:PM0556

REV. 1.1, JUN. 14, 2001

42

32-PIN PLASTIC LEADED CHIP CARRIER (PLCC)

MX29F022/022N

P/N:PM0556

REV. 1.1, JUN. 14, 2001

43

32-PIN PLASTIC TSOP

MX29F022/022N

P/N:PM0556

REV. 1.1, JUN. 14, 2001

44

MX29F022/022N

REVISION HISTORY

Revision Description Page Date

1.0 1.To remove "Advanced Information" datasheet marking and P1 DEC/21/1999
contain information on products in full production

2.The modification summary of Revision 0.9.4 to Revision 1.0:
2-1.Program/erase cycle times:10K cycles-->100K cycles P1,41
2-2.T o add data retention 20 y ears P1,41
2-3.To remove A9 from the timing w av ef orm of protection/ P35
unprotection without 12V
2-4.Multi-sector erase time-out:30ms-->30us, P8
2-5.tBAL:80us-->100us P21

1.1 To modify "P ackage Inf ormation" P42~44 JUN/14/2001

P/N:PM0556

REV. 1.1, JUN. 14, 2001

45

MX29F022/022N

MACRONIX INTERNATIONAL CO., LTD.

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FAX:[phone]

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TEL:[phone]
FAX:[phone]

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TEL:[phone]
FAX:[phone]

http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.

46