Datasheet MX28F2000TPC-12C4, MX28F2000TPC-90C4, MX28F2000TQC-12C4, MX28F2000TQC-90C4 Datasheet (MXIC)

FEATURES

MX28F2000T

2M-BIT [256K x 8] CMOS FLASH MEMORY

• 262,144 bytes by 8-bit organization

• Fast access time: 90/120 ns

• Low power consumption
– 50mA maximum active current
– 100uA maximum standby current

• Programming and erasing voltage 12V ± 5%

• Command register architecture
– Byte Programming (15us typical)
– Auto chip erase 5 seconds typical

(including preprogramming time)

– Block Erase

• Optimized high density blocked architecture
– Eight 4-KB blocks
– Fourteen 16-KB blocks

GENERAL DESCRIPTION

The MX28F2000T is a 2-mega bit Flash memory or­ganized as 256K bytes of 8 bits each. MXIC's Flash
memories offer the most cost-effective and reliable
read/write non-volatile random access memory. The
MX28F2000T is packaged in 32-pin PDIP and PLCC
. It is designed to be reprogrammed and erased in­system or in-standard EPROM programmers.

The standard MX28F2000T offers access times as
fast as 90 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate
bus contention, the MX28F2000T has separate chip
enable (CE) and output enable (OE) controls.

MXIC's Flash memories augment EPROM function­ality with in-circuit electrical erasure and
programming. The MX28F2000T uses a command
register to manage this functionality, while
maintaining a standard 32-pin pinout. The
command register allows for 100% TTL level control
inputs and fixed power supply levels during erase
and programming, while maintaining maximum
EPROM compatibility.

• Auto Erase (chip & block) and Auto Program
– DATA polling
– Toggle bit

• 10,000 minimum erase/program cycles

• Latch-up protected to 100mA from -1 to VCC+1V

• Advanced CMOS Flash memory technology

• Compatible with JEDEC-standard byte-wide 32-pin
EPROM pinouts

• Package type:
– 32-pin plastic DIP
– 32-pin PLCC

MXIC Flash technology reliably stores memory con­tents even after 10,000 erase and program cycles.
The MXIC cell is designed to optimize the erase and
programming mechanisms. In addition, the combi­nation of advanced tunnel oxide processing and low
internal electric fields for erase and programming
operations produces reliable cycling. The
MX28F2000T uses a 12.0V ± 5% VPP supply to
perform the Auto Program/Erase algorithms.

The highest degree of latch-up protection is
achieved with MXIC's proprietary non-epi process.
Latch-up protection is proved for stresses up to 100
milliamps on address and data pin from -1V to VCC
+ 1V.

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MX28F2000P Block Address and Block Structure

MX28F2000T

A17~A0

3FFFFH

3F000H

3EFFFH

3E000H

3DFFFH

3D000H

3CFFFH

3C000H

3BFFFH

3B000H

3AFFFH

3A000H
39FFFH

39000H

38FFFH

38000H

37FFFH
34000H
33FFFH

30000H
2FFFFH

2C000H

2BFFFH

28000H
27FFFH

24000H
23FFFH

20000H
1FFFFH

1C000H

1BFFFH

18000H
17FFFH

14000H
13FFFH

10000H
0FFFFH

0C000H
0BFFFH

08000H
07FFFH

04000H
03FFFH

00000H

4-K byte
4-K byte

4-K byte

4-K byte

4-K byte
4-K byte
4-K byte

4-K byte

16-K byte

16-K byte

16-K byte

16-K byte

16-K byte

16-K byte

16-K byte

16-K byte

16-K byte

16-K byte

16-K byte

16-K byte

16-K byte

16-K byte

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PIN CONFIGURATIONS

MX28F2000T

32 PDIP

32 PLCC

VPP

1

A16

2

A15

3

A12

4

A7

5

A6

6

A5

7

A4

8

A3

9

A2

10

A1

11

A0

12

Q0

13

Q1

14

Q2

15

GND

16

A12

A15

4

5

A7
A6
A5
A4

MX28F2000T

9

A3
A2
A1
A0

13

Q0

14 17 20

VCC

32

WE

31

A17

30

A14

29

A13

28

A8

27

A9

26

A11

25

OE

24

A10

23

CE

22

MX28F2000T

A16

1

21
20
19
18
17

VPP

32

Q7
Q6
Q5
Q4
Q3

VCCWEA17

PIN DESCRIPTION:

SYMBOL PIN NAME

A0~A17 Address Input
Q0~Q7 Data Input/Output
CE Chip Enable Input
OE Output Enable Input
WE Write enable Pin
VPP Program Supply Voltage
VCC Power Supply Pin (+5V)
GND Ground Pin

30

29

A14
A13
A8
A9

25

A11
OE
A10
CE

21

Q7

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Q1

Q2

VSS

Q3Q4Q5

Q6

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BLOCK DIAGRAM

MX28F2000T

CE

OE

WE

A0-A17

CONTROL
INPUT

LOGIC

ADDRESS

LATCH

AND

BUFFER

PROGRAM/ERASE

HIGH VOLTAGE

X-DECODER

MX28F2000T

FLASH
ARRA Y

Y-DECODER

Y-PASS GATE

SENSE

AMPLIFIER

PGM

DATA

HV

PROGRAM

DATA LATCH

ARRAY

SOURCE

HV

MODE
LOGIC

STATE

REGISTER

COMMAND

DATA
DECODER

COMMAND

DATA LATCH

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Q0-Q7

I/O BUFFER

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MX28F2000T

AUTOMATIC PROGRAMMING

The MX28F2000T is byte programmable using the
Automatic Programming algorithm. The Automatic
Programming algorithm does not require the system to
time out or verify the data programmed. The typical
room temperature chip programming time of the
MX28F2000T is less than 5 seconds.

AUTOMATIC CHIP ERASE

The device may be erased using the Automatic Erase
algorithm. The Automatic Erase algorithm automati­cally programs the entire array prior to electrical erase.
The timing and verification of electrical erase are
controlled internal to the device.

AUTOMATIC BLOCK ERASE

The MX28F2000T is block(s) erasable using MXIC's
Auto Block Erase algorithm. Block erase modes allow
blocks of the array to be erased in one erase cycle.
The Automatic Block Erase algorithm automatically
programs the specified block(s) prior to electrical
erase. The timing and verification of electrical erase
are controlled internal to the device.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm requires
the user to only write a program set-up command and
a program command (program data and address). The
device automatically times the programming pulse
width, provides the program verify, and counts the
number of sequences. A status bit similar to DATA
polling and a status bit toggling between consecutive
read cycles, provide feedback to the user as to the
status of the programming operation.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to
only write an erase set-up command and erase com­mand. The device will automatically pre-program and
verify the entire array. Then the device automatically
times the erase pulse width, provides the erase verify,
and counts the number of sequences. A status bit
similar to DATA polling and a status bit toggling
between consecutive read cycles, provide feedback to
the user as to the status of the erase operation.

Commands are written to the command register using
standard microprocessor write timings. Register con­tents serve as inputs to an internal state-machine
which controls the erase and programming circuitry.
During write cycles, the command register internally
latches address and data needed for the programming
and erase operations. For system design simplifica­tion, the MX28F2000T is designed to support either
WE or CE controlled writes. During a system write
cycle, addresses are latched on the falling edge of WE
or CE whichever occurs last. Data is latched on the
rising edge of WE or CE whichever occur first. To
simplify the following discussion, the WE pin is used as
the write cycle control pin throughout the rest of this
text. All setup and hold times are with respect to the
WE signal.

MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, relia­bility, and cost effectiveness. The MX28F2000P electri­cally erases all bits simultaneously using Fowler-Nord­heim tunneling. The bytes are programmed one byte at
a time using the EPROM programming mechanism of hot
electron injection.

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MX28F2000T

TABLE 1. COMMAND DEFINITIONS

COMMAND BUS FIRST BUS CYCLE SECOND BUS CYCLE

CYCLES OPERATION ADDRESS DATA OPERATION ADDRESS DATA

Read Memory 1 Write X 00H
Read Identified codes 2 Write X 90H Read IA ID
Setup auto erase/ 2 Write X 30H Write X 30H

auto erase (chip)
Setup auto erase/ 2 Write X 20H Write EA D0H

auto erase (block)

Setup auto program/ 2 Write X 40H Write PA PD
program

Setup Erase/ 2 Write X 20H Write X 20H
Erase (chip)

Setup Erase/ 2 Write X 60H Write EA 60H
Erase (block)

Erase verify 2 Write EVA A0H Read X EVD
Reset 2 Write X FFH Write X FFH

Note:

IA = Identifier address
EA = Block of memory location to be erased
PA = Address of memory location to be pro-

grammed

ID = Data read from location IA during device iden-

tification
PD = Data to be programmed at location PA
EVA = Address of memory location to be read during

erase verify.
EVD = Data read from location EVA during erase

verify.

Auto modes have the build-in enchanced features.
Please use the auto erase mode whenever it is.

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MX28F2000T

COMMAND DEFINITIONS

When low voltage is applied to the VPP pin, the con­tents of the command register default to 00H, enabling
read-only operation.

Placing high voltage on the VPP pin enables read/write
operations. Device operations are selected by writing
specific data patterns into the command register. Ta­ble 1 defines these MX28F2000T register commands.
Table 2 defines the bus operations of MX28F2000T.

TABLE 2. MX28F2000T BUS OPERATIONS

OPERATION VPP(1) A0 A9 CE OE WE DQ0-DQ7
READ-ONLY Read VPPL A0 A9 VIL VIL VIH Data Out

Output Disable VPPL X X VIL VIH VIH Tri-State
Standby VPPL X X VIH X X Tri-State
Read Silicon ID (Mfr)(2) VPPL VIL VID(3) VIL VIL VIH Data = C2H
Read Silicon ID (Device)(2) VPPL VIH VID(3) VIL VIL VIH Data = 3CH

READ/WRITE Read VPPH A0 A9 VIL VIL VIH Data Out(4)

Standby(5) VPPH X X VIH X X Tri-State
Write VPPH A0 A9 VIL VIH VIL Data In(6)

NOTES:

1. VPPL may be grounded, a no-connect with a resistor tied

to ground, or < VCC + 2.0V. VPPH is the programming
voltage specified for the device. When VPP = VPPL,
memory contents can be read but not written or erased.

2. Manufacturer and device codes may also be accessed

via a command register write sequence. Refer to Table

1. All other addresses don't care.

3. VID is the Silicon-ID-Read high voltage.(11.5V to 13v)

4. Read operations with VPP = VPPH may access array
data or Silicon ID codes.

5. With VPP at high voltage, the standby current equals ICC
+ IPP (standby).

6. Refer to Table 1 for valid Data-In during a write operation.

7. X can be VIL or VIH.

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MX28F2000T

READ COMMAND

While VPP is high, for erasure and programming,
memory contents can also be accessed via the read
command. The read operation is initiated by writing
00H into the command register. Microprocessor read
cycles retrieve array data. The device remains en­abled for reads until the command register contents
are altered.

The default contents of the register upon VPP power­up is 00H. This default value ensures that no spurious
alteration of memory contents occurs during the VPP
power transition. Where the VPP supply is hard-wired
to the MX28F2000T, the device powers up and
remains enabled for reads until the command register
contents are changed.

SILICON-ID-READ COMMAND

Flash-memories are intended for use in applications
where the local CPU alters memory contents. As such,
manufacturer- and device-codes must be accessible
while the device resides in the target system. PROM
programmers typically access signature codes by rais­ing A9 to a high voltage. However, multiplexing high
voltage onto address lines is not a desired system­design practice.

pattern. When the device is automatically verified to
contain an all-zero pattern, a self-timed chip erase and
verify begin. The erase and verify operations are
complete when the data on DQ7 is "1" at which time the
device returns to the Read mode. The system is not
required to provide any control or timing during these
operations.

When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when
adequate erase margin has been achieved for the
memory array(no erase verify command is required).
The margin voltages are internally generated in the
same manner as when the standard erase verify
command is used.

The Automatic set-up erase command is a command­only operation that stages the device for automatic
electrical erasure of all bytes in the array. Automatic
set-up erase is performed by writing 30H to the
command register.

To command automatic chip erase, the command 30H
must be written again to the command register. The
automatic chip erase begins on the rising edge of the
WE and terminates when the data on DQ7 is "1" and
the data on DQ6 stops toggling for two consecutive
read cycles, at which time the device returns to the
Read mode.

The MX28F2000T contains a Silicon-ID-Read opera­tion to supplement traditional PROM-programming
methodology. The operation is initiated by writing 90H
into the command register. Following the command
write, a read cycle from address 0000H retrieves the
manufacturer code of C2H. A read cycle from address
0001H returns the device code of 3CH.

SET-UP AUTOMATIC CHIP ERASE/ERASE
COMMANDS

The automatic chip erase does not require the device
to be entirely pre-programmed prior to excuting the
Automatic set-up erase command and Automatic chip
erase command. Upon executing the Automatic chip
erase command, the device automatically will program
and verify the entire memory for an all-zero data

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SET-UP AUTOMATIC BLOCK ERASE/ERASE
COMMANDS

The automatic block erase does not require the device
to be entirely pre-programmed prior to executing the
Automatic set-up block erase command and
Automatic block erase command. Upon executing the
Automatic block erase command, the device automati­cally will program and verify the block(s) memory for an
all-zero data pattern. The system is not required to
provide any controls or timing during these operations.

When the block(s) is automatically verified to contain
an all-zero pattern, a self-timed block erase and verify
begin. The erase and verify operations are complete
when the data on DQ7 is "1" and the data on DQ6 stops
toggling for two consecutive read cycles, at which time
the device returns to the Read mode. The system is
not required to provide any control or timing during
these operations.

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MX28F2000T

When using the Automatic Block Erase algorithm, note
that the erase automatically terminates when
adequate erase margin has been achieved for the
memory array (no erase verify command is required).
The margin voltages are internally generated in the
same manner as when the standard erase verify
command is used.

The Automatic set-up block erase command is a com­mand only operation that stages the device for auto­matic electrical erasure of selected blocks in the array.
Automatic set-up block erase is performed by writing
20H to the command register.

To enter automatic block erase, the user must write
the command D0H to the command register. Block
addresses are loaded into internal register on the 2nd
falling edge of WE. Each successive block load cycles,
started by the falling edge of WE, must begin within
30us from the rising edge of the preceding WE.
Otherwise, the loading period ends and internal auto
block erase cycle starts. When the data on DQ7 is "1"
and the data on DQ6 stops toggling for two consecutive
read cycles, at which time auto erase ends and the
device returns to the Read mode.

Refer to page 2 for detailed block address.

SET-UP AUTOMATIC PROGRAM/PROGRAM
COMMANDS

RESET COMMAND

A reset command is provided as a means to safely
abort the erase- or program-command sequences.
Following either set-up command (erase or program)
with two consecutive writes of FFH will safely abort the
operation. Memory contents will not be altered. Should
program-fail or erase-fail happen, two consecutive
writes of FFH will reset the device to abort the
operation. A valid command must then be written to
place the device in the desired state.

WRITE OPERATON STATUS

TOGGLE BIT-DQ6

The MX28F2000T features a "Toggle Bit" as a method
to indicate to the host sytem that the Auto Program/
Erase algorithms are either in progress or completed.

While the Automatic Program or Erase algorithm is in
progress, successive attempts to read data from the
device will result in DQ6 toggling between one and
zero. Once the Automatic Program or Erase algorithm
is completed, DQ6 will stop toggling and valid data will
be read. The toggle bit is valid after the rising edge of
the second WE pulse of the two write pulse sequences.

The Automatic Set-up Program is a command-only
operation that stages the device for automatic pro­gramming. Automatic Set-up Program is performed by
writing 40H to the command register.

Once the Automatic Set-up Program operation is per­formed, the next WE pulse causes a transition to an
active programming operation. Addresses are
internally latched on the falling edge of the WE pulse.
Data is internally latched on the rising edge of the WE
pulse. The rising edge of WE also begins the
programming operation. The system is not required to
provide further controls or timings. The device will
automatically provide an adequate internally
generated program pulse and verify margin. The
automatic programming operation is completed when
the data read on DQ6 stops toggling for two
consecutive read cycles and the data on DQ7 and
DQ6 are equivalent to data written to these two bits, at
which time the device returns to the Read mode (no
program verify command is required).

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DATA POLLING-DQ7

The MX28F2000T also features Data Polling as a
method to indicate to the host system that the
Automatic Program or Erase algorithms are either in
progress or completed.

While the Automatic Programming algorithm is in op­eration, an attempt to read the device will produce the
complement data of the data last written to DQ7. Upon
completion of the Automatic Program algorithm an
attempt to read the device will produce the true data
last written to DQ7. The Data Polling feature is valid
after the rising edge of the second WE pulse of the two
write pulse sequences.

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9

While the Automatic Erase algorithm is in operation,
DQ7 will read "0" until the erase operation is com­pleted. Upon completion of the erase operation, the
data on DQ7 will read "1". The Data Polling feature is
valid after the rising edge of the second WE pulse of
two write pulse sequences.

The Data Polling feature is active during Automatic
Program/Erase algorithms.

POWER-UP SEQUENCE

The MX28F2000T powers up in the Read only mode.
In addition, the memory contents may only be altered
after successful completion of a two-step command
sequence. Power up sequence is not required.

SYSTEM CONSIDERATIONS

MX28F2000T

During the switch between active and standby condi­tions, transient current peaks are produced on the
rising and falling edges of Chip Enable. The
magnitude of these transient current peaks is
dependent on the output capacitance loading of the
device. At a minimum, a 0.1uF ceramic capacitor (high
frequency, low inherent inductance) should be used on
each device between VCC and GND, and between
VPP and GND to minimize transient effects. In
addition, to overcome the voltage drop caused by the
inductive effects of the printed circuit board traces on
FLASH memory arrays, a 4.7uF bulk electrolytic
capacitor should be used between VCC and GND for
each eight devices. The location of the capacitor
should be close to where the power supply is con­nected to the array.

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MX28F2000T

ABSOLUTE MAXIMUM RATINGS

RATING VALUE

Ambient Operating Temperature 0
Storage Temperature -65
Applied Input Voltage -0.5V to 7.0V
Applied Output Voltage -0.5V to 7.0V
VCC to Ground Potential -0.5V to 7.0V
A9 & VPP -0.5V to 13.5V

o

C to 70oC

o

C to 125oC

NOTICE:

Stresses greater than those listed under ABSOLUTE MAXI­MUM RATINGS may cause permanent damage to the de­vice. This is stress rating only and functional operational
sections of this specification is not implied. Exposure to ab­solute maximum rating conditions for extended period may
affect reliability.

NOTICE:

Specifications contained within the following tables are sub­ject to change.

CAPACITANCE TA = 25oC, f = 1.0 MHz

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS

CIN Input Capacitance 14 pF VIN = 0V
COUT Output Capacitance 16 pF VOUT = 0V

READ OPERATION
DC CHARACTERISTICS

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS

ILI Input Leakage Current 10 uA VIN = GND to VCC

TA = 0oC TO 70oC, VCC = 5V ± 10%, VPP = GND to VCC

ILO Output Leakage Current 10 uA VOUT = GND to VCC
IPP1 VPP Current 1 100 uA VPP = 5.5V
ISB1 Standby VCC current 1 mA CE = VIH
ISB2 1 100 uA CE = VCC + 0.3V
ICC1 Operating VCC current 30 mA IOUT = 0mA, f=1MHz
ICC2 50 mA IOUT = 0mA, f=11MHz
VIL Input Low Voltage -0.3(NOTE 1) 0.8 V
VIH Input High Voltage 2.4 VCC + 0.3 V
VOL Output Low Voltage 0.45 V IOL = 2.1mA
VOH Output High Voltage 2.4 V IOH = -400uA

NOTES:

1. VIL min. = -1.0V for pulse width < 50 ns.
VIL min. = -2.0V for pulse width < 20 ns.

2. VIH max. = VCC + 1.5V for pulse width < 20 ns
If VIH is over the specified maximum value, read operation
cannot be guaranteed.

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MX28F2000T

AC CHARACTERISTICS TA = 0

o

C to 70oC, VCC = 5V ± 10%, VPP = GND to VCC

28F2000T-90 28F2000T-12

SYMBOL PARAMETER MIN. MAX. MIN. MAX. UNIT CONDITIONS

tACC Address to Output Delay 90 120 ns CE=OE=VIL
tCE CE to Output Delay 90 120 ns OE=VIL
tOE OE to Output Delay 40 50 ns CE=VIL
tDF OE High to Output Float (Note1) 0 20 0 30 ns CE=VIL
tOH Address to Output hold 0 0 ns CE=OE=VIL

TEST CONDITIONS:

• Input pulse levels: 0.45V/2.4V

• Input rise and fall times: <10ns

NOTE:

1. tDF is defined as the time at which the output achieves the
open circuit condition and data is no longer driven.

• Output load: 1 TTL gate + 100pF (Including scope and jig)

• Reference levels for measuring timing: 0.8V, 2.0V

READ TIMING WAVEFORMS

ADDRESS

WE

CE

OE

DATA OUT

tACC

ACTIVE MODE

tCE

tOE

STANDBY MODESTANDBY MODE

tDF

tOH

DATA OUT VALID

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MX28F2000T

COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION
DC CHARACTERISTICS

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS

ILI Input Leakage Current 10 uA VIN=GND to VCC
ILO Output Leakage Current 10 uA VOUT=GND to VCC
ISB1 Standby VCC current 1 mA CE=VIH
ISB2 1 100 uA CE=VCC ± 0.3V
ICC1 (Read) Operating VCC Current 30 mA IOUT=0mA, f=1MHz
ICC2 50 mA IOUT=0mA, F=11MHz
ICC3 (Program) 50 mA In Programming
ICC4 (Erase) 50 mA In Erase
ICC5 (Program Verify) 50 mA In Program Verify
ICC6 (Erase Verify) 50 mA In Erase Verify
IPP1 (Read) VPP Current 100 uA VPP=12.6V

TA = 0oC to 70oC, VCC = 5V ± 10%, VPP = 12.0V ± 5%

IPP2 (Program) 50 mA In Programming
IPP3 (Erase) 50 mA In Erase
IPP4 (Program Verify) 50 mA In Program Verify
IPP5 (Erase Verify) 50 mA In Erase Verify
VIL Input Voltage -0.3 (Note 5) 0.8 V
VIH 2.4 VCC+0.3V V

(Note 6)
VOL Output Voltage 0.45 V IOL=2.1mA
VOH 2.4 V IOH=-400uA

NOTES:

1. VCC must be applied before VPP and removed after VPP.

2. VPP must not exceed 14V including overshoot.

3. An influence may be had upon device reliability if the device
is installed or removed while VPP=12V.

4. Do not alter VPP either VIL to 12V or 12V to VIL when
CE=VIL.

5. VIL min. = -0.6V for pulse width < 20ns.

6. If VIH is over the specified maximum value, programming
operation cannot be guranteed.

7. All currents are in RMS unless otherwise noted.(Sampled, not
100% tested.)

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MX28F2000T

AC CHARACTERISTICS TA = 0

o

C to 70oC, VCC = 5V ± 10%, VPP =12V ± 5%

28F2000T-90 28F2000T-12

SYMBOL PARAMETER MIN. MAX. MIN. MAX. UNIT CONTIONS

tVPS VPP setup time 100 100 ns
tOES OE setup time 100 100 ns
tCWC Command programming cycle 90 120 ns
tCEP WE programming pulse width 45 50 ns
tCEPH1 WE programming pluse width High 20 20 ns
tCEPH2 WE programming pluse width High 100 100 ns
tAS Address setup time 0 0 ns
tAH Address hold time 45 50 ns
tAH1 Address hold time for DATA POLLING 0 0 ns
tDS Data setup time 45 50 ns
tDH Data hold time 10 10 ns
tCESP CE setup time before DATA polling/toggle bit 100 100 ns
tCES CE setup time 0 0 ns
tCESC CE setup time before command write 100 100 ns
tCESV CE setup time before verify 6 6 u s
tVPH VPP hold time 100 100 ns
tDF Output disable time (Note 3) 20 30 ns
tDPA DATA polling/toggle bit access time 90 120 ns
tAETC Total erase time in auto chip erase 5(TYP.) 5(TYP. ) s
tAETB Total erase time in auto block erase 5(TYP.) 5(TYP.) s
tAVT Total programming time in auto verify 15 300 15 300 us
tBALC Block address load cycle 0.3 30 0.3 30 u s
tBAL Block address load time 100 100 us
tCH CE Hold Time 0 0 ns
tCS CE setup to WE going low 0 0 ns

NOTES:

1. CE and OE must be fixed high during VPP transition from 5V
to 12V or from 12V to 5V.

2. Refer to read operation when VPP=VCC about read opera­tion while VPP 12V.

3. tDF defined as the time at which the output achieves the open
circuit condition and data is no longer driven.

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SWITCHING TEST CIRCUITS

MX28F2000T

DEVICE UNDER

TEST

CL=35pF Including jig capacitance

SWITCHING TEST WAVEFORMS

2.4 V

0.45 V

AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".

CL

6.2K ohm

2.0V
TEST POINTS

0.8V

INPUT

Input pulse rise and fall times are <20ns.

1.8K ohm

DIODES=IN3064

OR EQUIVALENT

2.0V

0.8V
OUTPUT

+5V

P/N: PM0472

15

REV. 1.0, Jun 13, 1997

AUTOMATIC PROGRAMMING TIMING WAVEFORM

MX28F2000T

One byte data is programmed. Verify in fast algorithm
and additional programming by external control are not
required because these operations are excuted auto­matically by internal control circuit. Programming
completion can be verified by DATA polling and toggle bit

Setup auto program/
program command

Vcc 5V

12V
Vpp
0V

A0 ~ A17

WE

CE

OE

Q7

tOES

tVPS

tAS

tCWC

tCEPH1

tCEP

tDS tDH tDHtDS

checking after automatic verify starts. Device outputs
DATA during programming and DATA after programming
on Q7. Q0 to Q5 (Q6 is for toggle bit; see toggle bit, DATA
polling, timing waveform) are in high impedance.

Auto program & DATA polling

tVPH

Address

valid

tAH1

tAVT

tCEP tCESP

Data inCommand in

tCES

tDPA

DATA

tCESC

tDF

DATA

Q0~Q5

Command #40H

Data inCommand in

DATA polling

DATA

P/N: PM0472

16

REV. 1.0, Jun 13, 1997

AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART

START

Apply VppH

Write Set up auto program Command (40H)

Write Auto program Command(A/D)

MX28F2000T

Toggle Bit Checking

DQ6 not Toggled

Verify Byte Ok

NO

Auto Program Completed

Last Byte

NO

YES

NO

YES

Reset

YES

Auto Program Failed

P/N: PM0472

17

REV. 1.0, Jun 13, 1997

AUTOMATIC CHIP ERASE TIMING WAVEFORM

MX28F2000T

All data in chip are erased. External erase verify is not
required because data is erased automatically by internal
control circuit. Erasure completion can be verified by
DATA polling and toggle bit checking after automatic

Setup auto chip erase/
erase command

Vcc 5V

12V
Vpp
0V

A0 ~ A17

WE

CE

OE

Q7

tOES

tVPS

tCWC

tCEP

tCEPH1

tDS tDH tDHtDS

Command in

erase starts. Device outputs 0 during erasure and 1 after
erasure on Q7. Q0 to Q5 (Q6 is for toggle bit; see toggle
bit, DATA polling, timing waveform) are in high imped­ance.

Auto chip erase & DATA polling

tVPH

tAETC

tCEP tCESP

Command in

tCES

tDPA

tCESC

tDF

Q0~Q5

Command in

Command #30H Command #30H

Command in

DATA polling

P/N: PM0472

18

REV. 1.0, Jun 13, 1997

AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART

START

Apply VppH

Write Set up auto chip Erase Command (30H)

Write Auto chip Erase Command(30H)

MX28F2000T

Toggle Bit Checking
DQ6 not Toggled

YES

DATA Polling
DQ7 = 1

YES

Auto Chip Erase Completed

No

No

Reset

Auto Chip Erase Failed

P/N: PM0472

19

REV. 1.0, Jun 13, 1997

AUTOMATIC BLOCK ERASE TIMING WAVEFORM

MX28F2000T

Block data indicated by A12 to A17 are erased. External
erase verify is not required because data are erased
automatically by internal control circuit. Erasure comple­tion can be verified by DATA polling and toggle bit

Setup auto block erase/erase command

Vcc 5V

12V
Vpp
0V

A0 ~ A11

A12 ~ A17

CE

WE

tVPS

tCS

tCH

tAS tAH

tCWC

tCEPH1

tCEPtOES

Block

address 0

tCEP

address 1

tBALC

tCEPH2

Block

checking after automatic erase starts. Device outputs 0
during erasure and 1 after erasure on Q7. Q0 to Q5 (Q6
is for toggle bit; see toggle bit, DATA polling, timing
waveform) are in high impedance.

Auto block erase & DATA polling

tVPH

Block

address #

tAH1

tBAL

tAETB

tCESC

tDS tDH tDS tDH

Q7

Q0~Q5

Command inOECommand in

Command in Command in

Command #20H Command #D0H

*Refer to page 2 for detailed block address.

tDPA

DATA polling

tDF

P/N: PM0472

20

REV. 1.0, Jun 13, 1997

AUTOMATIC BLOCK ERASE ALGORITHM FLOWCHART

ST ART

Apply VppH

Write Set up auto block Erase Command (20H)

Write Auto block Erase Command(D0H)

to Load Block Address

Load Block Address

MX28F2000T

Last Block
to Erase

YES

Wait 200 us

Toggle Bit Checking
DQ6 not Toggled

YES

DATA Polling

DQ7 = 1

YES

Auto Block Erase Completed

NO

NO

NO

Reset

Auto Block Erase Failed

P/N: PM0472

21

REV. 1.0, Jun 13, 1997

COMPATIBLE CHIP ERASE TIMING WAVEFORM

All data in chip are erased. Control verification and
additional erasure externally according tocompatible chip
erase flowchart.

MX28F2000T

Vcc 5V

12V
Vpp
0V

A0 ~ A17

WE

CE

OE

Q7

Q0~Q6

Setup chip erase/
erase command

tVPS

Verify

Address

tAH

tAS

tCWC

tCEPtOES

tDS tDH tDS tDH

Command in

Command in

Command #20H Command #20H Command #A0H

tCEPH1

tCEP

Command in

Command in

tET

tCEP

tDS

Command in

Command in

tCESV

tDH

Erase VerifyChip erase

tCES

tVA

tVPH

tCESC

tDF

Data valid

Data valid

P/N: PM0472

22

REV. 1.0, Jun 13, 1997

COMPATIBLE BLOCK ERASE

MX28F2000T

This device can be applied to the compatible block erase
algorithm shown in the following flowchart. This algorithm
allows to obtain faster erase time by the block (refer to

COMPATIBLE BLOCK ERASE FLOWCHART

START

For selected block(s),
All bits PGM"0"

N = 0

BLOCK ERASE FLOW

FAIL

ERSVFY FLOW

ALL BITS VERIFIED

APPLY

VPP = VCC

page2) without any voltage stress to the device nor
deterioration in reliability of data.

N = N+1

N = 1024?

BLOCK ERASE FAIL

END

NO

YES

BLOCK ERASE FLOW

BLOCK ERASE

COMPLETE

VPP = VPPH

WRITE SETUP BLOCK ERASE COMMAND

WRITE BLOCK ERASE COMMAND

( LOAD FIRST SECTOR ADDRESS , 60H )

LOAD OTHER SECTORS' ADDRESS

IF NECESSARY

( LOAD OTHER SECTOR ADDRESS )

START

Apply

( 60H )

WAIT

10 ms

END

P/N: PM0472

23

REV. 1.0, Jun 13, 1997

ERASE VERIFY FLOW

MX28F2000T

START

APPLY

VPP = VPPH

ADDRESS =

FIRST ADDRESS OF ERASED BLOCKS
OR LAST VERIFY FAILED ADDRESS

INCREMENT ADDRESS

WRITE ERASE VERIFY COMMAND

NO

( A0H )

WAIT 6 us

ERSVFY

FFH ?

YES

LAST ADDRESS ?

YES

ERASE VERIFY

COMPLETE

NO

GO TO ERASE FLOW

AGAIN OR ABORT

P/N: PM0472

24

REV. 1.0, Jun 13, 1997

COMPATIBLE BLOCK ERASE TIMING WAVEFORM

Indicated block data are erased. Control verification and
additional erasure externally according to compatible
block erase flowchart.

MX28F2000T

Vcc 5V

12V
Vpp
0V

A0 ~ A13

A14 ~ A17

WE

CE

OE

Q0~Q6

tVPS

tOES tCEP tCEP

Q7

Command #60H Command #60H

Setup block erase/erase command

Block

address 0

tAS tAH

tCWC tBALC

tCEPH1

tDS tDH tDS tDH

Command in

Command in

Block

address 1

tCEPH2

Command in

Command in

tBAL

Block

address #

Block erase

tET

Verify

address

Verify

address

tAS

tAH

tCEP

tDS

Command in

Command in

Command #A0H

tCESV

tDH

Erase Verify

tCES

tVA

tVPH

tCESC

tDF

Data valid

Data valid

P/N: PM0472

25

REV. 1.0, Jun 13, 1997

VPP HIGH READ TIMING WAVEFORM

Vcc 5V

12V
Vpp
0V

tVPS

MX28F2000T

tVPH

A0 - A17

tCWC

WE

CE

tOES

tCEP

tCEPH1

OE

tDH

00H

Q0-Q7

tDS

Command in

VPP LOW ID CODE READ TIMING WAVEFORM

VID
VIH

A9

VIL

Address valid

tACC

tCE

tOE

tCESC

tOES

tDF

tOH

Data out valid

P/N: PM0472

A0

A1 - A8

A10-A17

WE
CE

OE

Q0 - Q7

VIH

tACC

tCE

tACC

tOE

Manufacturer code Device code

C2H

tOH

26

tDF

tOH

3CH

REV. 1.0, Jun 13, 1997

VPP HIGH ID CODE READ TIMING WAVEFORM

Vcc 5V

12V
Vpp
0V

tVPS

MX28F2000T

tVPH

A0

A1 - A16

WE

CE

tOES

OE

Q0-Q7

RESET TIMING WAVEFORM

Address Valid 0 or 1

tCWC

tACC

tCEP

tDS

Command in

tCEPH2

tDH

90H C2H or 3CH

tCE

tOE

Data out valid

tCESC

tOES

tDF

tOH

P/N: PM0472

Vcc 5V

12V
Vpp
0V

A0 - A17

WE

CE

OE

Q0-Q7

tVPS

tOES

tCWC

tCEP

Command in

tCEPH1

tDS tDH

FFH FFH

tCEP

tDS tDH

Command in

REV. 1.0, Jun 13, 1997

27

TOGGLE BIT, DATA POLLING TIMING WAVEFORM

Toggle bit appears in Q6, when program/erase is
opperating. DATA polling appears in Q7 during pro­gramming or erase.

HIGH

WE

Vpp 12V

CE

OE

MX28F2000T

DURING P/E

Q6

Q7

DURING P

Q7

DURING E

Q8~Q15

HIGH-Z

HIGH-Z

HIGH-Z

HIGH-Z

DATA POLLING

DATA

TOGGLE BIT

DATA DATA

PROGRAM/ERASE COMPLETE

DATA POLLING

DATA OUT

DATA OUT

DATA OUT

P/N: PM0472

28

REV. 1.0, Jun 13, 1997

MX28F2000T

ORDERING INFORMATION PLASTIC PACKAGE

PART NO. ACCESS TIME OPERATING STANDBY PACKAGE ERASE/PROGRAM

CURRENT CURRENT CYCLE

(ns) MAX.(mA) MAX.(uA) MIN.(time)

MX28F2000TPC-90C4 90 50 100 32 Pin DIP 10,000
MX28F2000TPC-12C4 12 0 50 100 32 Pin DIP 10,000
MX28F2000TQC-90C4 90 50 100 32 Pin PLCC 10,000
MX28F2000TQC-12C4 120 5 0 100 32 Pin PLCC 10,000

P/N: PM0472

29

REV. 1.0, Jun 13, 1997

PACKAGE INFORMATION

32-PIN PLASTIC DIP

MX28F2000T

ITEM MILLIMETERS INCHES

A 42.13 max. 1.660 max.
B 1.90 [REF] .075 [REF]
C 2.54 [TP] .100 [TP]
D .46 [Typ.] .050 [Typ.]
E 38.07 1.500
F 1.27 [Typ.] .050 [Typ.]
G 3.30 ± .25 .130 ± .010
H .51 [REF] .020 [REF]
I 3.94 ± .25 1.55 ± .010
J 5.33 max. .210 max.
K 15.22 ± .25 .600 ± .101
L 13.97 ± .25 .550 ± .010
M .25 [Typ.] .010 [Typ.]

NOTE: Each lead certerline is located within

.25mm[.01 inch] of its true position [TP] at a
maximum at maximum material condition.

32-PIN PLASTIC LEADED CHIP CARRIER (PLCC)

ITEM MILLIMETERS INCHES

A 12.44 ± .13 .490 ± .005
B 11.50 ± .13 .453 ± .005
C 14.04 ± .13 .553 ± .005
D 14.98 ± .13 .590 ± .005
E 1.93 .076
F 3.30 ± .25 .130 ± .010
G 2.03 ± .13 .080 ± .005
H .51 ± .13 .020 ± .005
I 1.27 [Typ.] .050 [Typ.]
J .71 [REF] .028 [REF]
K .46 [REF] .018 [REF]
L 10.40/12.94 .410/.510

(W) (L) (W) (L)
M .89R .035R
N .25[Typ.] .010[Typ.]

NOTE: Each lead certerline is located within

.25mm[.01 inch] of its true position [TP] at a
maximum at maximum material condition.

1732

1

A

F

D

E

4

5

9

13

14

F

G

H

I

16

K
L

IJ

H

G

C

B

A

B
1

32

30

17

K

L

20

J

M

29

25

CD

21

E

N

M

0~15¡

P/N: PM0472

30

REV. 1.0, Jun 13, 1997

MX28F2000T

MACRONIX INTERNATIONAL CO., LTD.

HEADQUARTERS:

TEL:[phone]
FAX:[phone]

EUROPE OFFICE:

TEL:[phone]
FAX:[phone]

JAPAN OFFICE:

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FAX:[phone]

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TEL:[phone]
FAX:[phone]

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TEL:[phone]
FAX:[phone]

CHICAGO OFFICE:

TEL:[phone]
FAX:[phone]

http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.

31