Datasheet MX28F1000PRI-12, MX28F1000PRI-70, MX28F1000PRI-90, MX28F1000PTC-12C4, MX28F1000PTC-70C4 Datasheet (MXIC)
...Page 1
FEATURES
MX28F1000P
1M-BIT [128K x 8] CMOS FLASH MEMORY
• 131,072 bytes by 8-bit organization
• Fast access time: 70ns(Vcc:5V±5%; CL:35pF)
90/120ns(Vcc:5V±10%; CL:100pF)
• Low power consumption
– 50mA maximum active current
– 100uA maximum standby current
• Programming and erasing voltage 12V ± 5%
• Command register architecture
– Byte Programming (15us typical)
– Auto chip erase 5 seconds typical
(including preprogramming time)
– Block Erase
• Optimized high density blocked architecture
– Four 4-KB blocks
GENERAL DESCRIPTION
The MX28F1000P is a 1-mega bit Flash memory organized as 128K bytes of 8 bits each. MXIC's Flash
memories offer the most cost-effective and reliable
read/write non-volatile random access memory. The
MX28F1000P is packaged in 32-pin PDIP, PLCC
and TSOP. It is designed to be reprogrammed and
erased in-system or in-standard EPROM programmers.
– Seven 16-KB blocks
• Auto Erase (chip & block) and Auto Program
– DATA polling
– Toggle bit
• 10,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1 to VCC+1V
• Advanced CMOS Flash memory technology
• Compatible with JEDEC-standard byte-wide 32-pin
EPROM pinouts
• Package type:
– 32-pin plastic DIP
– 32-pin PLCC
– 32-pin TSOP (Type 1)
MX28F1000P uses a 12.0V ± 5% VPP supply to
perform the Auto Program/Erase algorithms.
The highest degree of latch-up protection is
achieved with MXIC's proprietary non-epi process.
Latch-up protection is proved for stresses up to 100
milliamps on address and data pin from -1V to VCC
+ 1V.
The standard MX28F1000P offers access times as
fast as 70 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate
bus contention, the MX28F1000P has separate chip
enable (CE) and output enable (OE ) controls.
MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and
programming. The MX28F1000P uses a command
register to manage this functionality, while
maintaining a standard 32-pin pinout. The
command register allows for 100% TTL level control
inputs and fixed power supply levels during erase
and programming, while maintaining maximum
EPROM compatibility.
MXIC Flash technology reliably stores memory contents even after 10,000 erase and program cycles.
The MXIC cell is designed to optimize the erase and
programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low
internal electric fields for erase and programming
operations produces reliable cycling. The
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MX28F1000P Block Address and Block Structure
A16 A15 A14 A13 A12 A[16:0]
11111
11110
11101
11100
4k
4k
4k
4k
MX28F1000P
1FFFF
1F000
1EFFF
1E000
1DFFF
1D000
1CFFF
1C000
1BFFF
110XX
101XX
100XX
011XX
010XX
001XX
16k
18000
17FFF
16k
14000
13FFF
16k
10000
0FFFF
16k
0C000
0BFFF
16k
08000
07FFF
16k
04000
03FFF
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000XX
16k
00000
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Page 3
PIN CONFIGURATIONS
A11
A9
A8
A13
A14
NC
WE
VCC
VPP
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
GND
Q2
Q1
Q0
A0
A1
A2
A3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
MX28F1000P
MX28F1000P
32 PDIP
32 PLCC
VPP
1
A16
2
A15
3
A12
4
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
Q0
13
Q1
14
Q2
15
GND
16
A12
A15
4
5
A7
A6
A5
A4
MX28F1000P
9
A3
A2
A1
A0
13
Q0
14 17 20
Q1
Q2
VCC
32
WE
31
NC
30
A14
29
A13
28
A8
27
A9
26
A11
25
OE
24
A10
23
MX28F1000P
A16
VSS
22
21
20
19
18
17
VPP
VCCWENC
1
32
Q3Q4Q5
CE
Q7
Q6
Q5
Q4
Q3
TSOP (TYPE 1)
(NORMAL TYPE)
1
32
OE
CE
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
31
30
29
28
27
26
25
24
23
22
21
20
A0
19
A1
18
A2
17
A3
MX28F1000P
(REVERSE TYPE)
A10
30
29
A14
A13
A8
A9
25
A11
OE
A10
CE
21
Q7
Q6
GND
A11
2
A9
3
A8
4
A13
5
A14
6
NC
7
WE
8
VCC
9
VPP
10
A16
11
A15
12
A12
13
A7
14
A6
15
A5
16
A4
PIN DESCRIPTION:
SYMBOL PIN NAME
A0~A16 Address Input
Q0~Q7 Data Input/Output
CE Chip Enable Input
OE Output Enable Input
WE Write enable Pin
VPP Program Supply Voltage
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VCC Power Supply Pin (+5V)
GND Ground Pin
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BLOCK DIAGRAM
MX28F1000P
CE
OE
WE
A0-A16
CONTROL
INPUT
LOGIC
ADDRESS
LATCH
AND
BUFFER
PROGRAM/ERASE
HIGH VOLTAGE
X-DECODER
MX28F1000P
FLASH
ARRA Y
Y-DECODER
Y-PASS GATE
SENSE
AMPLIFIER
PGM
DATA
HV
PROGRAM
DATA LATCH
ARRAY
SOURCE
HV
MODE
LOGIC
STATE
REGISTER
COMMAND
DATA
DECODER
COMMAND
DATA LATCH
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Q0-Q7
I/O BUFFER
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MX28F1000P
AUTOMATIC PROGRAMMING
The MX28F1000P is byte programmable using the
Automatic Programming algorithm. The Automatic
Programming algorithm does not require the system to
time out or verify the data programmed. The typical
room temperature chip programming time of the
MX28F1000P is less than 5 seconds.
AUTOMATIC CHIP ERASE
The device may be erased using the Automatic Erase
algorithm. The Automatic Erase algorithm automatically programs the entire array prior to electrical erase.
The timing and verification of electrical erase are
controlled internal to the device.
AUTOMATIC BLOCK ERASE
The MX28F1000P is block(s) erasable using MXIC's
Auto Block Erase algorithm. Block erase modes allow
blocks of the array to be erased in one erase cycle.
The Automatic Block Erase algorithm automatically
programs the specified block(s) prior to electrical
erase. The timing and verification of electrical erase
are controlled internal to the device.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm requires
the user to only write a program set-up command and
a program command (program data and address). The
device automatically times the programming pulse
width, provides the program verify, and counts the
number of sequences. A status bit similar to DATA
polling and a status bit toggling between consecutive
read cycles, provide feedback to the user as to the
status of the programming operation.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
only write an erase set-up command and erase command. The device will automatically pre-program and
verify the entire array. Then the device automatically
times the erase pulse width, provides the erase verify,
and counts the number of sequences. A status bit
similar to DATA polling and a status bit toggling
between consecutive read cycles, provide feedback to
the user as to the status of the erase operation.
Commands are written to the command register using
standard microprocessor write timings. Register contents serve as inputs to an internal state-machine
which controls the erase and programming circuitry.
During write cycles, the command register internally
latches address and data needed for the programming
and erase operations. For system design simplification, the MX28F1000P is designed to support either
WE or CE controlled writes. During a system write
cycle, addresses are latched on the falling edge of WE
or CE whichever occurs last. Data is latched on the
rising edge of WE or CE whichever occur first. To
simplify the following discussion, the WE pin is used as
the write cycle control pin throughout the rest of this
text. All setup and hold times are with respect to the
WE signal.
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, reliability, and cost effectiveness. The MX28F1000P electrically erases all bits simultaneously using Fowler-Nordheim tunneling. The bytes are programmed one byte at
a time using the EPROM programming mechanism of hot
electron injection.
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MX28F1000P
TABLE 1. COMMAND DEFINITIONS
COMMAND BUS FIRST BUS CYCLE SECOND BUS CYCLE
CYCLES OPERATION ADDRESS DATA OPERATION ADDRESS DATA
Read Memory 1 Write X 00H
Read Identified codes 2 Write X 90H Read IA ID
Setup auto erase/ 2 Write X 30H Write X 30H
auto erase (chip)
Setup auto erase/ 2 Write X 20H Write EA D0H
auto erase (block)
Setup auto program/ 2 Write X 40H Write PA PD
program
Setup Erase/ 2 Write X 20H Write X 20H
Erase (chip)
Setup Erase/ 2 Write X 60H Write EA 60H
Erase (block)
Erase verify 2 Write EVA A0H Read X EVD
Reset 2 Write X FFH Write X FFH
Note:
IA = Identifier address
EA = Block of memory location to be erased
PA = Address of memory location to be pro-
grammed
ID = Data read from location IA during device iden-
tification
PD = Data to be programmed at location PA
EVA = Address of memory location to be read during
erase verify.
EVD = Data read from location EVA during erase
verify.
Auto modes have the build-in enchanced features.
Please use the auto erase mode whenever it is.
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MX28F1000P
COMMAND DEFINITIONS
When low voltage is applied to the VPP pin, the contents of the command register default to 00H, enabling
read-only operation.
Placing high voltage on the VPP pin enables read/write
operations. Device operations are selected by writing
specific data patterns into the command register. Table 1 defines these MX28F1000P register commands.
Table 2 defines the bus operations of MX28F1000P.
TABLE 2. MX28F1000P BUS OPERATIONS
OPERATION VPP(1) A0 A9 CE OE WE DQ0-DQ7
READ-ONLY Read VPPL A0 A9 VIL VIL VIH Data Out
Output Disable VPPL X X VIL VIH VIH Tri-State
Standby VPPL X X VIH X X Tri-State
Read Silicon ID (Mfr)(2) VPPL VIL VID(3) VIL VIL VIH Data = C2H
Read Silicon ID (Device)(2) VPPL VIH VID(3) VIL VIL VIH Data = 1AH
READ/WRITE Read VPPH A0 A9 VIL VIL VIH Data Out(4)
Standby(5) VPPH X X VIH X X Tri-State
Write VPPH A0 A9 VIL VIH VIL Data In(6)
NOTES:
1. VPPL may be grounded, a no-connect with a resistor tied
to ground, or < VCC + 2.0V. VPPH is the programming
voltage specified for the device. When VPP = VPPL,
memory contents can be read but not written or erased.
2. Manufacturer and device codes may also be accessed
via a command register write sequence. Refer to Table
1. All other addresses are don't care.
3. VID is the Silicon-ID-Read high voltage.(11.5V to 13v)
4. Read operations with VPP = VPPH may access array
data or Silicon ID codes.
5. With VPP at high voltage, the standby current equals ICC
+ IPP (standby).
6. Refer to Table 1 for valid Data-In during a write operation.
7. X can be VIL or VIH.
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MX28F1000P
READ COMMAND
While VPP is high, for erase and programming, memory contents can also be accessed via the read command. The read operation is initiated by writing 00H
into the command register. Microprocessor read
cycles retrieve array data. The device remains enabled for reads until the command register contents
are altered.
The default contents of the register upon VPP powerup is 00H. This default value ensures that no spurious
alteration of memory contents occurs during the VPP
power transition. Where the VPP supply is hard-wired
to the MX28F1000P, the device powers up and
remains enabled for reads until the command register
contents are changed.
SILICON-ID-READ COMMAND
Flash-memories are intended for use in applications
where the local CPU alters memory contents. As such,
manufacturer- and device-codes must be accessible
while the device resides in the target system. PROM
programmers typically access signature codes by raising A9 to a high voltage. However, multiplexing high
voltage onto address lines is not a desired systemdesign practice.
device returns to the Read mode. The system is not
required to provide any control or timing during these
operations.
When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when
adequate erase margin has been achieved for the
memory array(no erase verify command is required).
The margin voltages are internally generated in the
same manner as when the standard erase verify
command is used.
The Automatic set-up erase command is a commandonly operation that stages the device for automatic
electrical erasure of all bytes in the array. Automatic
set-up erase is performed by writing 30H to the
command register.
To command automatic chip erase, the command 30H
must be written again to the command register. The
automatic chip erase begins on the rising edge of the
WE and terminates when the data on DQ7 is "1" and
the data on DQ6 stops toggling for two consecutive
read cycles, at which time the device returns to the
Read mode.
SET-UP AUTOMATIC BLOCK ERASE/ERASE
COMMANDS
The MX28F1000P contains a Silicon-ID-Read
operation to supplement traditional PROMprogramming methodology. The operation is initiated
by writing 90H into the command register. Following
the command write, a read cycle from address 0000H
retrieves the manufacturer code of C2H. A read cycle
from address 0001H returns the device code of 1AH.
SET-UP AUTOMATIC CHIP ERASE/ERASE
COMMANDS
The automatic chip erase does not require the device
to be entirely pre-programmed prior to excuting the
Automatic set-up erase command and Automatic chip
erase command. Upon executing the Automatic chip
erase command, the device automatically will program
and verify the entire memory for an all-zero data
pattern. When the device is automatically verified to
contain an all-zero pattern, a self-timed chip erase and
verify begin. The erase and verify operations are
complete when the data on DQ7 is "1" at which time the
The automatic block erase does not require the device
to be entirely pre-programmed prior to executing the
Automatic set-up block erase command and
Automatic block erase command. Upon executing the
Automatic block erase command, the device automatically will program and verify the block(s) memory for an
all-zero data pattern. The system is not required to
provide any controls or timing during these operations.
When the block(s) is automatically verified to contain
an all-zero pattern, a self-timed block erase and verify
begin. The erase and verify operations are complete
when the data on DQ7 is "1" and the data on DQ6 stops
toggling for two consecutive read cycles, at which time
the device returns to the Read mode. The system is
not required to provide any control or timing during
these operations.
When using the Automatic Block Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verify command is required). The margin
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MX28F1000P
voltages are internally generated in the same manner
as when the standard erase verify command is used.
The Automatic set-up block erase command is a command only operation that stages the device for automatic electrical erasure of selected blocks in the array.
Automatic set-up block erase is performed by writing
20H to the command register.
To enter automatic block erase, the user must write
the command D0H to the command register. Block
addresses are loaded into internal register on the 2nd
falling edge of WE. Each successive block load cycles,
started by the falling edge of WE, must begin within
30ms from the rising edge of the preceding WE.
Otherwise, the loading period ends and internal auto
block erase cycle starts. When the data on DQ7 is "1"
and the data on DQ6 stops toggling for two
consecutive read cycles, at which time auto erase
ends and the device returns to the Read mode.
Refer to page 2 for detailed block address.
SET-UP AUTOMATIC PROGRAM/PROGRAM
COMMANDS
The Automatic Set-up Program is a command-only
operation that stages the device for automatic programming. Automatic Set-up Program is performed by
writing 40H to the command register.
Once the Automatic Set-up Program operation is performed, the next WE pulse causes a transition to an
active programming operation. Addresses are
internally latched on the falling edge of the WE pulse.
Data is internally latched on the rising edge of the WE
pulse. The rising edge of WE also begins the
programming operation. The system is not required to
provide further controls or timings. The device will
automatically provide an adequate internally
generated program pulse and verify margin. The
automatic programming operation is completed when
the data read on DQ6 stops toggling for two
consecutive read cycles and the data on DQ7 and
DQ6 are equivalent to data written to these two bits, at
which time the device returns to the Read mode (no
program verify command is required).
SET-UP CHIP ERASE/ERASE COMMANDS
Set-up Chip Erase is a command-only operation that
stages the device for electrical erasure of all bytes in
the array. The set-up erase operation is performed by
writing 20H to the command register.
To commence chip erasure, the erase command (20H)
must again be written to the register. The erase
operation begins with the rising edge of the WE pulse.
This two-step sequence of set-up followed by execution ensures that memory contents are not accidentally
erased. Also, chip-erasure can only occur when high
voltage is applied to the VPP pin. In the absence of this
high voltage, memory contents are protected against
erasure.
SET-UP BLOCK ERASE/ERASE COMMANDS
Set-up Block Erase is a command-only operation that
stages the device for electrical erasure of all selected
block(s) in the array. The set-up erase operation is
performed by writing 60H to the command register.
To enter block-erasure, the block erase command 60H
must be written again to the command register. The
block erase mode allows 1 to 8 blocks of the array to be
erased in one internal erase cycle. Internally, there are
8 registers (flags) addressed by A14 to A16. First block
address is loaded into internal registers on the 2-nd
falling of WE. Each successive block load cycles,
started by the falling edge of WE, must begin within
30ms from the rising edge of the preceding WE. Otherwise, the loading period ends and internal block erase
cycle starts. When the data on DQ7 is "1" at which time
auto erase ends and the device returns to the Read
mode.
ERASE-VERIFY COMMAND
After each erase operation, all bytes must be verified.
The erase verify operation is initiated by writing A0H
into the command register. The address for the byte to
be verified must be supplied as it is latched on the
falling edge of the WE pulse.
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MX28F1000P
The MX28F1000P applies an internally generated
margin voltage to the addressed byte. Reading FFH
from the addressed byte indicates that all bits in the
byte are erased.
The erase-verify command must be written to the
command register prior to each byte verification to
latch its address. The process continues for each byte
in the array until a byte does not return FFH data, or the
last address is accessed.
In the case where the data read is not FFH, another
erase operation is performed. (Refer to Set-up Erase/
Erase). Verification then resumes from the address of
the last-verified byte. Once all bytes in the array have
been verified, the erase step is complete. The device
can be programmed. At this point, the verify operation
is terminated by writing a valid command (e.g.
Program Set-up) to the command register. The High
Reliability Erase algorithm, illustrates how commands
and bus operations are combined to perform electrical
erasure of the MX28F1000P.
RESET COMMAND
DATA POLLING-DQ7
The MX28F1000P also features Data Polling as a
method to indicate to the host system that the
Automatic Program or Erase algorithms are either in
progress or completed.
While the Automatic Programming algorithm is in operation, an attempt to read the device will produce the
complement data of the data last written to DQ7. Upon
completion of the Automatic Program algorithm an
attempt to read the device will produce the true data
last written to DQ7. The Data Polling feature is valid
after the rising edge of the second WE pulse of the two
write pulse sequences.
While the Automatic Erase algorithm is in operation,
DQ7 will read "0" until the erase operation is completed. Upon completion of the erase operation, the
data on DQ7 will read "1". The Data Polling feature is
valid after the rising edge of the second WE pulse of
two write pulse sequences.
The Data Polling feature is active during Automatic
Program/Erase algorithms.
A reset command is provided as a means to safely
abort the erase- or program-command sequences.
Following either set-up command (erase or program)
with two consecutive writes of FFH will safely abort the
operation. Memory contents will not be altered.
Should program-fail or erase-fail happen, two
consecutive writes of FFH will reset the device to abort
the operation. A valid command must then be written
to place the device in the desired state.
WRITE OPERATON STATUS
TOGGLE BIT-DQ6
The MX28F1000P features a "Toggle Bit" as a method
to indicate to the host sytem that the Auto Program/
Erase algorithms are either in progress or completed.
While the Automatic Program or Erase algorithm is in
progress, successive attempts to read data from the
device will result in DQ6 toggling between one and
zero. Once the Automatic Program or Erase algorithm
is completed, DQ6 will stop toggling and valid data will
be read. The toggle bit is valid after the rising edge of
the second WE pulse of the two write pulse
sequences.
POWER-UP SEQUENCE
The MX28F1000P powers up in the Read only mode. In
addition, the memory contents may only be altered after
successful completion of a two-step command sequence.
Power up sequence is not required.
SYSTEM CONSIDERATIONS
During the switch between active and standby conditions, transient current peaks are produced on the
rising and falling edges of Chip Enable. The magnitude
of these transient current peaks is dependent on the
output capacitance loading of the device. At a
minimum, a 0.1uF ceramic capacitor (high frequency,
low inherent inductance) should be used on each
device between VCC and GND, and between VPP and
GND to minimize transient effects. In addition, to
overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on FLASH
memory arrays, a 4.7uF bulk electrolytic capacitor
should be used between VCC and GND for each eight
devices. The location of the capacitor should be close
to where the power supply is connected to the array.
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MX28F1000P
ABSOLUTE MAXIMUM RATINGS
RATING VALUE
Ambient Operating Temperature -40
Storage Temperature -65
Applied Input Voltage -0.5V to 7.0V
Applied Output Voltage -0.5V to 7.0V
VCC to Ground Potential -0.5V to 7.0V
A9 & VPP -0.5V to 13.5V
o
C to 85oC
o
C to 125oC
NOTICE:
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may
affect reliability.
NOTICE:
Specifications contained within the following tables are subject to change.
CAPACITANCE TA = 25oC, f = 1.0 MHz
SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS
CIN Input Capacitance 14 pF VIN = 0V
COUT Output Capacitance 16 pF VOUT = 0V
READ OPERATION
DC CHARACTERISTICS
SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS
ILI Input Leakage Current 10 uA VIN = GND to VCC
ILO Output Leakage Current 10 uA VOUT = GND to VCC
IPP1 VPP Current 1 100 uA VPP = 5.5V
ISB1 Standby VCC current 1 mA CE = VIH
ISB2 1 100 uA CE = VCC + 0.3V
ICC1 Operating VCC current 30(NOTE4) mA IOUT = 0mA, f=1MHz
ICC2 50 mA IOUT = 0mA, f=11MHz
VIL Input Low Voltage -0.3(NOTE 1) 0.8 V
VIH Input High Voltage 2.4 VCC + 0.3 V
VOL Output Low Voltage 0.45 V IOL = 2.1mA
VOH Output High Voltage 2.4 V IOH = -400uA
NOTES:
1. VIL min. = -1.0V for pulse width < 50 ns.
VIL min. = -2.0V for pulse width < 20 ns.
2. VIH max. = VCC + 1.5V for pulse width < 20 ns
If VIH is over the specified maximum value, read operation
cannot be guaranteed.
3. Test condition:
TA =-40°C to 85°C, Vcc = 5V±10%, Vpp = GND to Vcc, CL
= 100pF(for MX28F1000P-90/12)
TA = -40°C to 85°C, Vcc = 5V±10%, Vpp = GND to Vcc, CL
= 35pF(for MX28F1000P-70)
4.ICC1=35mA for TA=-40°C to 85°C
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MX28F1000P
AC CHARACTERISTICS
28F1000P-70 28F1000P-90 28F1000P-12
SYMBOL PARAMETER MIN. MAX. MIN. MAX. MIN. MAX. UNIT CONDITIONS
tACC Address to Output Delay 70 90 120 ns CE=OE=VIL
tCE CE to Output Delay 70 90 120 ns OE=VIL
tOE OE to Output Delay 30 35 50 ns CE=VIL
tDF OE High to Output Float (Note1) 0 15 0 20 0 30 ns CE=VIL
tOH Address to Output hold 0 0 0 0 ns CE=OE=VIL
TEST CONDITIONS:
• Input pulse levels: 0.45V/2.4V
• Input rise and fall times: < 10ns
• Reference levels for measuring timing: 0.8V, 2.0V
• 28F1000P-70:Vcc = 5V ± 5%, CL: 1TTL gate +
35pF(including scope and jig)
• 28F1000P-70:Vcc = 5V ± 5%, CL: 1TTL gate +
35pF(including scope and jig)
• Vpp = GND to Vcc
READ TIMING WAVEFORMS
ADDRESS
WE
CE
NOTE:
1. tDF is defined as the time at which the output achieves the
open circuit condition and data is no longer driven.
ACTIVE MODE
tCE
STANDBY MODESTANDBY MODE
DATA OUT
P/N: PM0340
OE
tACC
12
tOE
tDF
tOH
DATA OUT VALID
REV. 1.6, JAN. 19, 1999
Page 13
MX28F1000P
COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION
DC CHARACTERISTICS
SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS
ILI Input Leakage Current 10 uA VIN=GND to VCC
ILO Output Leakage Current 10 uA VOUT=GND to VCC
ISB1 Standby VCC current 1 mA CE=VIH
ISB2 1 100 uA CE=VCC ± 0.3V
ICC1 (Read) Operating VCC Current 30 mA IOUT=0mA, f=1MHz
ICC2 50 mA IOUT=0mA, F=11MHz
ICC3 (Program) 50 mA In Programming
ICC4 (Erase) 50 mA In Erase
ICC5 (Program Verify) 50 mA In Program Verify
ICC6 (Erase Verify) 50 mA In Erase Verify
IPP1 (Read) VPP Current 100 uA VPP=12.6V
IPP2 (Program) 50 mA In Programming
IPP3 (Erase) 50 mA In Erase
IPP4 (Program Verify) 50 mA In Program Verify
IPP5 (Erase Verify) 50 mA In Erase Verify
VIL Input Voltage -0.3 (Note 5) 0.8 V
VIH 2.4 VCC+0.3V V
(Note 6)
VOL Output Voltage 0.45 V IOL=2.1mA
VOH 2.4 V IOH=-400uA
NOTES:
1. VCC must be applied before VPP and removed after VPP.
2. VPP must not exceed 14V including overshoot.
3. An influence may be had upon device reliability if the device
is installed or removed while VPP=12V.
4. Do not alter VPP either VIL to 12V or 12V to VIL when
CE=VIL.
5. VIL min. = -0.6V for pulse width < 20ns.
6. If VIH is over the specified maximum value, programming
operation cannot be guranteed.
7. All currents are in RMS unless otherwise noted.(Sampled, not
100% tested.)
8. For 28F1000P-70, Vcc = 5V ±5%, CL = 35pF; for 28F1000P90/12, Vcc = 5V ± 10%, CL = 100pF.
P/N: PM0340
13
REV. 1.6, JAN. 19, 1999
Page 14
MX28F1000P
AC CHARACTERISTICS TA = -40
o
C to 85oC, VCC = 5V ± 10%, VPP =12V ± 5%
28F1000-70 28F1000P-90 28F1000P-12
SYMBOL PARAMETER MIN. MAX. MIN. MAX. MIN. MAX. UNIT CONTIONS
tVPS VPP setup time 100 100 100 ns
tOES OE setup time 100 100 100 ns
tCWC Command programming cycle 70 90 120 ns
tCEP WE programming pulse width 40 45 50 ns
tCEPH1 WE programming pluse width High 20 20 20 ns
tCEPH2 WE programming pluse width High 100 100 100 ns
tAS Address setup time 0 0 0 ns
tAH Address hold time 40 45 50 ns
tAH1 Address hold time for DATA POLLING 0 0 0 ns
tDS Data setup time 40 45 50 ns
tDH Data hold time 10 10 10 ns
tCESP CE setup time before DATA polling/toggle bit 100 100 100 ns
tCES CE setup time 0 0 0 ns
tCESC CE setup time before command write 100 100 100 ns
tCESV CE setup time before verify 6 6 6 us
tVPH VPP hold time 100 100 100 ns
tDF Output disable time (Note 3) 15 20 30 ns
tDPA DATA polling/toggle bit access time 70 90 120 ns
tAETC Total erase time in auto chip erase 5(TYP.) 5(TYP.) 5(TYP.) s
tAETB Total erase time in auto block erase 5TYP.) 5(TYP.) 5(TYP.) s
tAVT Total programming time in auto verify 15 300 15 300 15 300 us
tBALC Block address load cycle 0.3 30 0.3 30 0.3 30 us
tBAL Block address load time 200 200 200 us
tCH CE Hold Time 0 0 0 ns
tCS CE setup to WE going low 0 0 0 ns
NOTES:
1. CE and OE must be fixed high during VPP transition from 5V
to 12V or from 12V to 5V.
2. Refer to read operation when VPP=VCC about read operation while VPP 12V.
3. tDF defined as the time at which the output achieves the open
circuit condition and data is no longer driven.
P/N: PM0340
14
REV. 1.6, JAN. 19, 1999
Page 15
SWITCHING TEST CIRCUITS
MX28F1000P
DEVICE
UNDER
TEST
CL = 100 pF including jig capacitance(35pF for 70 ns parts)
SWITCHING TEST WAVEFORMS
2.4 V
0.45 V
AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".
CL
6.2K ohm
2.0V
TEST POINTS
0.8V
INPUT
Input pulse rise and fall times are <20ns.
1.8K ohm
DIODES = IN3064
OR EQUIVALENT
2.0V
0.8V
OUTPUT
+5V
P/N: PM0340
15
REV. 1.6, JAN. 19, 1999
Page 16
AUTOMATIC PROGRAMMING TIMING WAVEFORM
MX28F1000P
One byte data is programmed. Verify in fast algorithm
and additional programming by external control are not
required because these operations are excuted automatically by internal control circuit. Programming
completion can be verified by DATA polling and toggle bit
Setup auto program/
program command
Vcc 5V
12V
Vpp
0V
A0 ~ A16
WE
CE
OE
Q7
tOES
tVPS
tAS
tCWC
tCEPH1
tCEP
tDS tDH tDHtDS
checking after automatic verify starts. Device outputs
DATA during programming and DATA after programming
on Q7. Q0 to Q5 (Q6 is for toggle bit; see toggle bit, DATA
polling, timing waveform) are in high impedance.
Auto program & DATA polling
tVPH
Address
valid
tAH1
tAVT
tCEP tCESP
Data inCommand in
tCES
tDPA
DATA
tCESC
tDF
DATA
Q0~Q5
Command #40H
Data inCommand in
DATA polling
DATA
P/N: PM0340
16
REV. 1.6, JAN. 19, 1999
Page 17
AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Apply VppH
Write Set up auto program Command (40H)
Write Auto program Command(A/D)
MX28F1000P
Toggle Bit Checking
DQ6 not Toggled
Verify Byte Ok
NO
Auto Program Completed
Last Byte
NO
YES
NO
YES
Reset
YES
Auto Program Failed
P/N: PM0340
17
REV. 1.6, JAN. 19, 1999
Page 18
AUTOMATIC CHIP ERASE TIMING WAVEFORM
MX28F1000P
All data in chip are erased. External erase verify is not
required because data is erased automatically by internal
control circuit. Erasure completion can be verified by
DATA polling and toggle bit checking after automatic
Setup auto chip erase/
erase command
Vcc 5V
12V
Vpp
0V
A0 ~ A16
WE
CE
OE
Q7
tOES
tVPS
tCWC
tCEP
tCEPH1
tDS tDH tDHtDS
Command in
erase starts. Device outputs 0 during erasure and 1 after
erasure on Q7. Q0 to Q5 (Q6 is for toggle bit; see toggle
bit, DATA polling, timing waveform) are in high impedance.
Auto chip erase & DATA polling
tVPH
tAETC
tCEP tCESP
Command in
tCES
tDPA
tCESC
tDF
Q0~Q5
Command in
Command #30H Command #30H
Command in
DATA polling
P/N: PM0340
18
REV. 1.6, JAN. 19, 1999
Page 19
AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Apply VppH
Write Set up auto chip Erase Command (30H)
Write Auto chip Erase Command(30H)
MX28F1000P
Toggle Bit Checking
DQ6 not Toggled
YES
DATA Polling
DQ7 = 1
YES
Auto Chip Erase Completed
No
No
Reset
Auto Chip Erase Failed
P/N: PM0340
19
REV. 1.6, JAN. 19, 1999
Page 20
AUTOMATIC BLOCK ERASE TIMING WAVEFORM
MX28F1000P
Block data indicated by A12 to A16 are erased. External
erase verify is not required because data are erased
automatically by internal control circuit. Erasure completion can be verified by DATA polling and toggle bit
Setup auto block erase/erase command
Vcc 5V
12V
Vpp
0V
A0 ~ A11
A12 ~ A16
CE
WE
tVPS
tCS
tCH
tAS tAH
tCWC
tCEPH1
tCEPtOES
Block
address 0
tCEP
address 1
tBALC
tCEPH2
Block
checking after automatic erase starts. Device outputs 0
during erasure and 1 after erasure on Q7. Q0 to Q5 (Q6
is for toggle bit; see toggle bit, DATA polling, timing
waveform) are in high impedance.
Auto block erase & DATA polling
tVPH
Block
address #
tAH1
tBAL
tAETB
tCESC
tDS tDH tDS tDH
Q7
Q0~Q5
Command inOECommand in
Command in Command in
Command #20H Command #D0H
*Refer to page 2 for detailed block address.
tDPA
DATA polling
tDF
P/N: PM0340
20
REV. 1.6, JAN. 19, 1999
Page 21
AUTOMATIC BLOCK ERASE ALGORITHM FLOWCHART
ST ART
Apply VppH
Write Set up auto block Erase Command (20H)
Write Auto block Erase Command(D0H)
to Load Block Address
Load Block Address
MX28F1000P
Last Block
to Erase
YES
Wait 200us
Toggle Bit Checking
DQ6 not Toggled
YES
DATA Polling
DQ7 = 1
YES
Auto Block Erase Completed
NO
NO
NO
Reset
Auto Block Erase Failed
P/N: PM0340
21
REV. 1.6, JAN. 19, 1999
Page 22
COMPATIBLE CHIP ERASE TIMING WAVEFORM
All data in chip are erased. Control verification and
additional erasure externally according tocompatible chip
erase flowchart.
MX28F1000P
Vcc 5V
12V
Vpp
0V
A0 ~ A16
WE
CE
OE
Q7
Q0~Q6
Setup chip erase/
erase command
tVPS
Verify
Address
tAH
tAS
tCWC
tCEPtOES
tDS tDH tDS tDH
Command in
Command in
Command #20H Command #20H Command #A0H
tCEPH1
tCEP
Command in
Command in
tET
tCEP
tCESV
tDH
tDS
Command in
Command in
Erase VerifyChip erase
tCES
tVA
tVPH
tCESC
tDF
Data valid
Data valid
P/N: PM0340
22
REV. 1.6, JAN. 19, 1999
Page 23
COMPATIBLE BLOCK ERASE
MX28F1000P
This device can be applied to the compatible block erase
algorithm shown in the following flowchart. This algorithm
allows to obtain faster erase time by the block (16K byte
COMPATIBLE BLOCK ERASE FLOWCHART
START
For selected block(s),
All bits PGM"0"
N = 0
BLOCK ERASE FLOW
FAIL
ERSVFY FLOW
ALL BITS VERIFIED
APPLY
VPP = VCC
x 8 block) without any voltage stress to the device nor
deterioration in reliability of data.
N = N+1
N = 1024?
BLOCK ERASE FAIL
END
NO
YES
BLOCK ERASE FLOW
P/N: PM0340
BLOCK ERASE
COMPLETE
WRITE SETUP BLOCK ERASE COMMAND
( LOAD FIRST SECTOR ADDRESS , 60H )
START
Apply
VPP = VPPH
( 60H )
WRITE BLOCK ERASE COMMAND
LOAD OTHER SECTORS' ADDRESS
IF NECESSARY
( LOAD OTHER SECTOR ADDRESS )
WAIT
10 ms
END
23
REV. 1.6, JAN. 19, 1999
Page 24
ERASE VERIFY FLOW
MX28F1000P
START
APPLY
VPP = VPPH
ADDRESS =
FIRST ADDRESS OF ERASED BLOCKS
OR LAST VERIFY FAILED ADDRESS
INCREMENT ADDRESS
WRITE ERASE VERIFY COMMAND
NO
( A0H )
WAIT 6 us
ERSVFY
FFH ?
YES
LAST ADDRESS ?
YES
ERASE VERIFY
COMPLETE
NO
GO TO ERASE FLOW
AGAIN OR ABORT
P/N: PM0340
24
REV. 1.6, JAN. 19, 1999
Page 25
COMPATIBLE BLOCK ERASE TIMING WAVEFORM
Indicated block data (16 Kbyte) are erased. Control
verification and additional erasure externally according to
compatible block erase flowchart.
MX28F1000P
Vcc 5V
12V
Vpp
0V
A0 ~ A13
A14 ~ A16
WE
CE
OE
Q0~Q6
tVPS
tOES tCEP tCEP
Q7
Command #60H Command #60H
Setup block erase/erase command
Block
address 0
tAS tAH
tCWC tBALC
tCEPH1
tDS tDH tDS tDH
Command in
Command in
Block
address 1
tCEPH2
Command in
Command in
tBAL
Block
address #
Block erase
tET
Verify
address
Verify
address
tAS
tAH
tCEP
tDS
Command in
Command in
Command #A0H
tCESV
tDH
Erase Verify
tCES
tVA
tVPH
tCESC
tDF
Data valid
Data valid
P/N: PM0340
25
REV. 1.6, JAN. 19, 1999
Page 26
VPP HIGH READ TIMING WAVEFORM
Vcc 5V
12V
Vpp
0V
tVPS
MX28F1000P
tVPH
A0 - A16
tCWC
WE
CE
tOES
tCEP
tCEPH1
OE
tDH
00H
Q0-Q7
tDS
Command in
VPP LOW ID CODE READ TIMING WAVEFORM
VID
VIH
A9
VIL
Address valid
tACC
tCE
tOE
tCESC
tOES
tDF
tOH
Data out valid
P/N: PM0340
A0
A1 - A8
A10-A16
WE
CE
OE
Q0 - Q7
VIH
tACC
tACC
tCE
tOE
Manufacturer code Device code
C2H
tOH
26
tDF
tOH
1AH
REV. 1.6, JAN. 19, 1999
Page 27
VPP HIGH ID CODE READ TIMING WAVEFORM
Vcc 5V
12V
Vpp
0V
tVPS
MX28F1000P
tVPH
A0
A1 - A16
WE
CE
tOES
OE
Q0-Q7
RESET TIMING WAVEFORM
Address Valid 0 or 1
tCWC
tACC
tCEP
tDS
Command in
tCEPH2
tDH
90H C2H or 1AH
tCE
tOE
Data out valid
tCESC
tOES
tDF
tOH
P/N: PM0340
Vcc 5V
12V
Vpp
0V
A0 - A16
WE
CE
OE
Q0-Q7
tVPS
tOES
tCWC
tCEP
Command in
tCEPH1
tDS tDH
FFH FFH
tCEP
tDS tDH
Command in
REV. 1.6, JAN. 19, 1999
27
Page 28
TOGGLE BIT, DATA POLLING TIMING WAVEFORM
Toggle bit appears in Q6, when program/erase is
opperating. DATA polling appears in Q7 during programming or erase.
HIGH
WE
Vpp 12V
CE
OE
MX28F1000P
DURING P/E
Q6
Q7
DURING P
Q7
DURING E
Q0~Q5
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
DATA POLLING
DATA
TOGGLE BIT
DATA
DATA DATA DATA
PROGRAM/ERASE COMPLETE
DATA POLLING
DATA
ERASE AND PROGRAMMING PERFORMANCE
LIMITS
PARAMETER MIN. TYP. MAX. UNITS
Chip/Sector Erase Time 1.5 20 sec
Chip Programming Time 2 13.8 sec
Erase/Program Cycles 10,000 cycles
Byte Program Time 15 642 us
P/N: PM0340
28
REV. 1.6, JAN. 19, 1999
Page 29
MX28F1000P
ORDERING INFORMATION PLASTIC PACKAGE
PART NO. ACCESS TIME OPERATING STANDBY PACKAGE ERASE/PROGRAM
CURRENT CURRENT CYCLE
(ns) MAX.(mA) MAX.(uA) MIN.(time)
MX28F1000PPC-70C4 70 50 100 32 Pin DIP 10,000
MX28F1000PPC-90C4 90 50 100 32 Pin DIP 10,000
MX28F1000PPC-12C4 120 50 100 32 Pin DIP 10,000
MX28F1000PQC-70C4 70 50 100 32 Pin PLCC 10,000
MX28F1000PQC-90C4 90 50 100 32 Pin PLCC 10,000
MX28F1000PQC-12C4 120 50 100 32 Pin PLCC 10,000
MX28F1000PTC-70C4 70 50 100 32 Pin TSOP 10,000
(Normal Type)
MX28F1000PTC-90C4 90 50 100 32 Pin TSOP 10,000
(Normal Type)
MX28F1000PTC-12C4 120 50 100 32 Pin TSOP 10,000
(Normal Type)
MX28F1000PRC-70C4 70 50 100 32 Pin TSOP 10,000
(Reverse Type)
MX28F1000PRC-90C4 90 50 100 32 Pin TSOP 10,000
(Reverse Type)
MX28F1000PRC-12C4 120 50 100 32 Pin TSOP 10,000
(Reverse Type)
MX28F1000PPI-70 70 50 100 32 Pin DIP 10,000
MX28F1000PPI-90 90 50 100 32 Pin DIP 10,000
MX28F1000PPI-12 120 50 100 32 Pin DIP 10,000
MX28F1000PQI-70 70 50 1 00 32 Pin PLCC 10,000
MX28F1000PQI-90 90 50 1 00 32 Pin PLCC 10,000
MX28F1000PQI-12 120 50 100 32 Pin PLCC 10,000
MX28F1000PTI-70 70 50 100 32 Pin TSOP 10,000
(Normal Type)
MX28F1000PTI-90 90 50 100 32 Pin TSOP 10,000
(Normal Type)
MX28F1000PTI-12 120 50 100 32 Pin TSOP 10,000
(Normal Type)
MX28F1000PRI-70 70 5 0 100 32 Pin TSOP 10,000
(Reverse Type)
MX28F1000PRI-90 90 5 0 100 32 Pin TSOP 10,000
(Reverse Type)
MX28F1000PRI-12 120 5 0 100 32 Pin TSOP 10,000
(Reverse Type)
P/N: PM0340
29
REV. 1.6, JAN. 19, 1999
Page 30
PACKAGE INFORMATION
32-PIN PLASTIC DIP
ITEM MILLIMETERS INCHES
A 42.13 max. 1.660 max.
B 1.90 [REF] .075 [REF]
C 2.54 [TP] .100 [TP]
D .46 [Typ.] .050 [Typ.]
E 38.07 1.500
F 1.27 [Typ.] .050 [Typ.]
G 3.30 ± .25 .130 ± .010
H .51 [REF] .020 [REF]
I 3.94 ± .25 1.55 ± .010
J 5.33 max. .210 max.
K 15.22 ± .25 .600 ± .101
L 13.97 ± .25 .550 ± .010
M .25 [Typ.] .010 [Typ.]
NOTE: Each lead certerline is located within
.25mm[.01 inch] of its true position [TP] at a
maximum at maximum material condition.
MX28F1000P
1732
1
A
F
D
E
16
K
L
IJ
H
G
C
B
M
0~15¡
32-PIN PLASTIC LEADED CHIP CARRIER (PLCC)
ITEM MILLIMETERS INCHES
A 12.44 ± .13 .490 ± .005
B 11.50 ± .13 .453 ± .005
C 14.04 ± .13 .553 ± .005
D 14.98 ± .13 .590 ± .005
E 1.93 .076
F 3.30 ± .25 .130 ± .010
G 2.03 ± .13 .080 ± .005
H .51 ± .13 .020 ± .005
I 1.27 [Typ.] .050 [Typ.]
J .71 [REF] .028 [REF]
K .46 [REF] .018 [REF]
L 10.40/12.94 .410/.510
(W) (L) (W) (L)
M .89R .035R
N .25[Typ.] .010[Typ.]
NOTE: Each lead certerline is located within
.25mm[.01 inch] of its true position [TP] at a
maximum at maximum material condition.
A
B
4
5
9
13
14
F
G
H
1
32
30
29
25
CD
21
17
I
K
L
20
E
N
M
J
P/N: PM0340
30
REV. 1.6, JAN. 19, 1999
Page 31
32-PIN PLASTIC TSOP
ITEM MILLIMETERS INCHES
A 20.0 ± .20 .078 ± .006
B 18.40 ± .10 .724 ± .004
C 8.20 max. .323 max.
D 0.15 [Typ.] .006 [Typ.]
E .80 [Typ.] .031 [Typ.]
F .20 ± .10 .008 ± .004
G .30 ± .10 .012 ± .004
H .50 [Typ.] .020 [Typ.]
I .45 max. .018 max.
J 0 ~ .20 0 ~ .008
K 1.00 ± .10 .039 ± .004
L 1.27 max. .050 max.
M .50 .020
N 0 ~5° .500
NOTE: Each lead certerline is located within
.25mm[.01 inch] of its true position [TP] at a
maximum at maximum material condition.
MX28F1000P
A
B
C
O
M
D
E
F
H
G
N
KL
J
I
P/N: PM0340
31
REV. 1.6, JAN. 19, 1999
Page 32
MX28F1000P
Note. Revision History
Revision # Description Page Date
1.4 Fast access time 150ns and 1,000 times erase cycles removed.
Tsop pin configuration diagram rotated 180°.
The flow chart of block erase corrected.
1.5 Fast access time 70ns added. Dec/26/1996
1.6 1)Absolute max. ratings:TA=-40°C to 85°C P11 JAN/19/1999
2)DC Characteristics:ICC1=35mA for TA=-40°C to 85°C
3)AC Characteristics:TA=-40°C to 85°C P14
4)Order Informance:Add Industrial Grade P29
5)Erase & Programming Performance:New in Creased table
P/N: PM0340
32
REV. 1.6, JAN. 19, 1999
Page 33
MX28F1000P
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-8888
FAX:+886-3-578-8887
EUROPE OFFICE:
TEL:+32-2-456-8020
FAX:+32-2-456-8021
JAPAN OFFICE:
TEL:+81-44-246-9100
FAX:+81-44-246-9105
SINGAPORE OFFICE:
TEL:+65-747-2309
FAX:+65-748-4090
TAIPEI OFFICE:
TEL:+886-3-509-3300
FAX:+886-3-509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-453-8088
FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900
FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.
33
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