Datasheet MX27C8100MC-10, MX27C8100MC-12, MX27C8100MC-15, MX27C8100MC-20, MX27C8100PC-10 Datasheet (MXIC)

FEATURES

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

NC
A18
A17

A7
A6
A5
A4
A3
A2
A1
A0

CE

GND

OE

Q0

Q8

Q1

Q9

Q2
Q10

Q3
Q11

NC
NC
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE/VPP
GND
Q15/A1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC

MX27C8100

MX27C8100

8M-BIT [1M x8/512K x16] CMOS OTP ROM

• 1M x 8 or 512K x 16 organization

• +12.5V programming voltage

• Fast access time: 100/120/150/200 ns

• Totally static operation

• Completely TTL compatible

GENERAL DESCRIPTION

The MX27C8100 is a 5V only, 8M-bit, One Time Program­mable Read Only Memory. It is organized as 1M x 8 or
512K x 16, operates from a single + 5 volt supply, has
a static standby mode, and features fast single address
location programming. All programming signals are TTL
levels, requiring a single pulse. For programming outside
from the system, existing EPROM programmers may be

PIN CONFIGURATIONS

PDIP

A18
A17

CE

GND

OE
Q0
Q8
Q1
Q9
Q2

Q10

Q3

Q11

1
2

A7

3

A6

4

A5

5

A4

6

A3

7

A2

8

A1

9

A0

10
11
12

MX27C8100

13
14
15
16
17
18
19
20
21

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

NC
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE/VPP
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC

• Operating current: 60mA

• Standby current: 100uA

• Package type:

-42 pin plastic DIP

-44 pin SOP

used. The MX27C8100 supports a intelligent fast pro­gramming algorithm which can result in programming
time of less than two minutes.

This One Time Programmable Read Only Memory is
packaged in industry standard 42 pin dual-in-line plastic
package and 44 pin SOP packages.

SOP

BLOCK DIAGRAM

CE
OE

BYTE/VPP

A0~A18

ADDRESS

INPUTS

VCC

P/N: PM0261

GND

.
.
.
.
.
.
.
.

CONTROL

LOGIC

Y-DECODER

X-DECODER

OUTPUT

BUFFERS

.

Y-SELECT

.
.
.
.
.
.
.

8M BIT

CELL

MAXTRIX

Q0~Q14
Q15/A-1

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REV. 2.3, NOV. 12, 2001

MX27C8100

PIN DESCRIPTION

SYMBOL PIN NAME

A0~A18 Address Input
Q0~Q14 Data Input/Output
CE Chip Enable Input
OE Output Enable Input
BYTE/VPP Word/Byte Selection/Program Supply Voltage
Q15/A-1 Q15(Word mode)/LSB addr. (Byte mode)
VCC Power Supply Pin (+5V)
GN D Ground Pin

TRUTH TABLE OF BYTE FUNCTION

BYTE MODE(BYTE = GND)

CE OE Q15/A-1 MODE Q0-Q7 SUPPLY CURRENT

H X X Non selected High Z Standby(ICC2)
L H X Non selected High Z Operating(ICC1)
L L A-1 input Selected DOUT Operating(ICC1)

WORD MODE(BYTE = VCC)

CE OE Q15/A-1 MODE Q0-Q14 SUPPLY CURRENT

H X High Z Non selected High Z Standby(ICC2)
L H High Z Non selected High Z Operating(ICC1)
L L DOUT Selected DOUT Operating(ICC1)

NOTE : X = H or L

P/N: PM0261

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REV. 2.3, NOV. 12, 2001

MX27C8100

FUNCTIONAL DESCRIPTION

THE PROGRAMMING OF THE MX27C8100

When the MX27C8100 is delivered, the chip has all 8M
bits in the "ONE" or HIGH state. "ZEROs" are loaded into
the MX27C8100 through the procedure of programming.

For programming, the data to be programmed is applied
with 16 bits in parallel to the data pins.

Vcc must be applied simultaneously or before Vpp, and
removed simultaneously or after Vpp. When
programming an MXIC One Time Programmable Read
Only Memory, a 0.1uF capacitor is required across Vpp
and ground to suppress spurious voltage transients
which may damage the device.

FAST PROGRAMMING

The device is set up in the fast programming mode when
the programming voltage VPP = 12.75V is applied, with
VCC = 6.25 V and OE = VIH (Algorithm is shown in Figure

1). The programming is achieved by applying a single
TTL low level 50us pulse to the CE input after addresses
and data line are stable. If the data is not verified, an
additional pulse is applied for a maximum of 25 pulses.
This process is repeated while sequencing through each
address of the device. When the programming mode is
completed, the data in all address is verified at VCC =
VPP = 5V ± 10%.

PROGRAM INHIBIT MODE

Programming of multiple MX27C8100's in parallel with
different data is also easily accomplished by using the
Program Inhibit Mode. Except for CE and OE, all like
inputs of the parallel MX27C8100 may be common. A
TTL low-level program pulse applied to an MX27C8100
CE input with VPP = 12.5 ± 0.5 V will program the
MX27C8100. A high-level CE input inhibits the other
MX27C8100 from being programmed.

PROGRAM VERIFY MODE

AUTO IDENTIFY MODE

The auto identify mode allows the reading out of a binary
code from an One Time Programmable Read Only
Memory that will identify its manufacturer and device
type. This mode is intended for use by programming
equipment for the purpose of automatically matching the
device to be programmed with its corresponding
programming algorithm. This mode is functional in the
25°C ± 5°C ambient temperature range that is required
when programming the MX27C8100.

To activate this mode, the programming equipment must
force 12.0 ± 0.5 V on address line A9 of the device. Two
identifier bytes may then be sequenced from the device
outputs by toggling address line A0 from VIL to VIH. All
other address lines must be held at VIL during auto
identify mode.

Byte 0 ( A0 = VIL) represents the manufacturer code, and
byte 1 (A0 = VIH), the device identifier code. For the
MX27C8100, these two identifier bytes are given in the
Mode Select Table. All identifiers for manufacturer and
device codes will possess odd parity, with the MSB (Q15)
defined as the parity bit.

READ MODE

The MX27C8100 has two control functions, both of which
must be logically satisfied in order to obtain data at the
outputs. Chip Enable (CE) is the power control and
should be used for device selection. Output Enable (OE)
is the output control and should be used to gate data to
the output pins, independent of device selection.
Assuming that addresses are stable, address access
time (tACC) is equal to the delay from CE to output (tCE).
Data is available at the outputs tOE after the falling edge
of OE's, assuming that CE has been LOW and addresses
have been stable for at least tACC - t OE.

WORD-WIDE MODE

With BYTE/VPP at VCC ± 0.2V outputs Q0-7 present
data Q0-7 and outputs Q8-15 present data Q8-15, after
CE and OE are appropriately enabled.

Verification should be performed on the programmed bits
to determine that they were correctly programmed. The
verification should be performed with OE at VIL, CE at
VIH, and VPP at its programming voltage.

P/N: PM0261

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REV. 2.3, NOV. 12, 2001

MX27C8100

BYTE-WIDE MODE

With BYTE/VPP at GND ± 0.2V, outputs Q8-15 are tri­stated. If Q15/A-1 = VIH, outputs Q0-7 present data bits
Q8-15. If Q15/A-1 = VIL, outputs Q0-7 present data bits
Q0-7.

STANDBY MODE

The MX27C8100 has a CMOS standby mode which
reduces the maximum VCC current to 100 uA. It is
placed in CMOS standby when CE is at VCC ± 0.3 V. The
MX27C8100 also has a TTL-standby mode which
reduces the maximum VCC current to 1.5 mA. It is
placed in TTL-standby when CE is at VIH. When in
standby mode, the outputs are in a high-impedance
state, independent of the OE input.

TWO-LINE OUTPUT CONTROL FUNCTION

To accommodate multiple memory connections, a two­line control function is provided to allow for:

1. Low memory power dissipation,

2. Assurance that output bus contention will not
occur.

It is recommended that CE be decoded and used as the
primary device-selecting function, while OE be made a
common connection to all devices in the array and
connected to the READ line from the system control bus.
This assures that all deselected memory devices are in
their low-power standby mode and that the output pins
are only active when data is desired from a particular
memory device.

SYSTEM CONSIDERATIONS

During the switch between active and standby
conditions, transient current peaks are produced on the
rising and falling edges of Chip Enable. The magnitude
of these transient current peaks is dependent on the
output capacitance loading of the device. At a minimum,
a 0.1 uF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between Vcc
and GND to minimize transient effects. In addition, to
overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on One Time
Programmable Read Only Memory arrays, a 4.7 uF bulk
electrolytic capacitor should be used between VCC and
GND for each eight devices. The location of the
capacitor should be close to where the power supply is
connected to the array.

MODE SELECT TABLE

BYTE/

MODE CE OE A9 A0 Q15/A-1 VPP(5) Q8-14 Q0-7

Read (Word) VIL VIL X X Q15 Out VC C Q8-14 Out Q0-7 Out
Read (Upper Byte) VIL VIL X X VIH GND High Z Q8-15 Out
Read (Lower Byte) VIL VIL X X VIL GND High Z Q0-7 Out
Output Disable VIL VIH X X High Z X High Z High Z
Standby VIH X X X High Z X High Z High Z
Program VIL VIH X X Q15 In VPP Q8-14 In Q0-7 In
Program Verify VIH VIL X X Q15 Out VPP Q8-14 Out Q0-7 Out
Program Inhibit VIH VIH X X High Z VPP High Z High Z
Manufacturer Code(3) VIL VIL VH VIL 0B VCC 00H C2H
Device Code(3) VIL VIL VH VIH 1B VCC 38H 16H

NOTES:

1. VH = 12.0V ± 0.5V

2. X Either VIL or VIH.

3. A1 - A8, A10 - A18 = VIL (for auto select)

4. See DC Programming Characteristics for VPP voltages.

5. BYTE/VPP is intended for operation under DC Voltage conditions
only.

6. Manufacture code = 00C2H
Device code = B816H

P/N: PM0261

4

REV. 2.3, NOV. 12, 2001

FIGURE 1. FAST PROGRAMMING FLOW CHART

MX27C8100

START

ADDRESS = FIRST LOCATION

VCC = 6.25V
VPP = 12.75V

X = 0

PROGRAM ONE 50us PULSE

INTERACTIVE
SECTION

VERIFY SECTION

INCREMENT ADDRESS

FAIL

NO

INCREMENT X

X = 25?

NO

VERIFY BYTE

?

PASS

LAST ADDRESS

YES

VCC = VPP = 5.25V

VERIFY ALL BYTES

?

PASS

DEVICE PASSED

YES

FAIL

FAIL

DEVICE FAILED

P/N: PM0261

5

REV. 2.3, NOV. 12, 2001

SWITCHING TEST CIRCUITS

MX27C8100

DEVICE
UNDER

TEST

CL = 100 pF including jig capacitance

SWITCHING TEST WAVEFORMS

AC driving levels

AC TESTING: AC driving levels are 2.4V/0.4V.

CL

6.2K ohm

2.0V
TEST POINTS

0.8V

INPUT

Input pulse rise and fall times are < 10ns.

1.8K ohm
+5V

DIODES = IN3064
OR EQUIVALENT

2.0V

0.8V
OUTPUT

P/N: PM0261

6

REV. 2.3, NOV. 12, 2001

MX27C8100

ABSOLUTE MAXIMUM RATINGS

RATING VALUE

Ambient Operating Temperature 0oC to 70oC
Storage Temperature -65oC to 125oC
Applied Input Voltage -0.5V to 7.0V
Applied Output Voltage -0.5V to VCC + 0.5V
VCC to Ground Potential -0.5V to 7.0V
A9 & VPP -0.5V to 13.5V

DC/AC Operating Conditions for Read Operation

-10 -12 -15 -20

Operating Temperature Commercial 0°C to 70°C0°C to 70°C0°C to 70°C0°C to 70°C
Vcc Power Supply 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10%

NOTICE:

Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended period may affect reliability.

NOTICE:

Specifications contained within the following tables are subject to
change.

MX27C8100

DC CHARACTERISTICS

SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS

VO H Output High Voltage 2.4 V IOH = -0.4mA
VOL Output Low Voltage 0.4 V IOL = 2.1mA
VIH Input High Voltage 2.0 VCC + 0.5 V
VIL Input Low Voltage -0.3 0.8 V
ILI Input Leakage Current -10 10 uA VIN = 0 to 5.5V
ILO Output Leakage Current -1 0 10 uA VOUT = 0 to 5.5V
ICC3 VCC Power-Down Current 100 uA CE = VCC ± 0.3V
ICC2 VCC Standby Current 1.5 mA CE = VIH
ICC1 VCC Active Current 60 mA CE = VIL, f=5MHz, Iout = 0mA
IPP VPP Supply Current Read 10 uA CE = OE = VIL, VPP = 5.5V

CAPACITANCE TA = 25

SYMBOL PARAMETER TYP. MAX. UNIT CONDITIONS

CIN Input Capacitance 8 12 pF VIN = 0V
COUT Output Capacitance 8 12 pF VOUT = 0V
CVPP VPP Capacitance 18 25 pF VPP = 0V

o

C, f = 1.0 MHz (Sampled only)

P/N: PM0261

7

REV. 2.3, NOV. 12, 2001

MX27C8100

AC CHARACTERISTICS

27C8100-10 27C8100-12 27C8100-15 27C8100-20

SYMBOL PARAMETER MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. UNIT CONDITIONS

tACC Address to Output Delay 100 120 150 200 ns CE = OE = VIL
tCE Chip Enable to Output Delay 100 120 150 200 n s OE = VIL
tOE Output Enable to Output Delay 40 50 65 80 ns CE = VIL
tDF OE High to Output Float, 0 30 0 3 5 0 50 0 50 ns

or CE High to Output Float0

tO H Output Hold from Address, 0 0 0 0 ns

CE or OE which ever occurred first
tBHA BYTE Access Time 100 120 150 200 ns
tOHB BYTE Output Hold Time 0 0 0 0 ns
tBHZ BYTE Output Delay Time 70 70 70 70 n s
tBLZ BYTE Output Set Time 10 10 10 10 n s

DC PROGRAMMING CHARACTERISTICS TA = 25

SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS

VO H Output High Voltage 2.4 V IOH = -0.40mA
VOL Output Low Voltage 0.4 V IOL = 2.1mA
VIH Input High Voltage 2.0 VCC + 0.5 V
VIL Input Low Voltage -0.3 0.8 V
ILI Input Leakage Current -1 0 10 uA VIN = 0 to 5.5V
VH A9 Auto Select Voltage 11.5 12.5 V
ICC3 VCC Supply Current (Program & Verify) 50 mA
IPP2 VPP Supply Current(Program) 30 mA CE = VIL, OE = VIH
VCC1 Fast Programming Supply Voltage 6.00 6.50 V
VPP1 Fast Programming Voltage 12.5 13.0 V

AC PROGRAMMING CHARACTERISTICS TA = 25

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

tAS Address Setup Time 2.0 us
tOES OE Setup Time 2.0 us
tDS Data Setup Time 2.0 us
tAH Address Hold Time 0 us
tDH Data Hold Time 2.0 us
tDFP Chip Enable to Output Float Delay 0 130 ns
tVCS VCC Setup Time 2.0 us
tVPS BYTE/VPP Setup Time 2.0 us
tPW CE initial Program Pulse Width 50 us
tOE Data valid from OE 150 ns

o

C ± 5oC

o

C ± 5oC

P/N: PM0261

8

REV. 2.3, NOV. 12, 2001

WAVEFORMS

READ CYCLE(WORD MODE)

MX27C8100

ADDRESS

INPUTS

CE

OE

DATA

OUT

READ CYCLE(BYTE MODE)

A-1

BYTE/VPP

HIGH-Z

tACC

tCE

tOE

tACC

DATA ADDRESS

tDF

VALID DATA

tOH

HIGH-Z

tOH

P/N: PM0261

Q0-Q7

Q15-Q8

tOHB

tBHZ

9

VALID DATA

VALID DATA

tBHA

VALID DATA

tBLZ

REV. 2.3, NOV. 12, 2001

WAVEFORMS

FAST PROGRAMMING ALGORITHM WAVEFORMS

MX27C8100

Addresses

DATA

BYTE/VPP

VCC

CE

OE

VIH

VIL

VPP1

VCC

VCC1

VCC

VIH

VIL

VIH

VIL

tAS

tDS

tVPS

tVCS

DATA SET

tPW

PROGRAM

tDH

VALID ADDRESS

tOES

VERIFY

tAH

DATA OUT VALID

tDFP

tOE

P/N: PM0261

10

REV. 2.3, NOV. 12, 2001

MX27C8100

ORDERING INFORMATION

PLASTIC PACKAGE

PART NO. ACCESS TIME OPERATING CURRENT STANDBY CURRENT PACKAGE

(ns) MAX.(mA) MAX.(uA)

MX27C8100PC-10 100 60 100 42 Pin DIP(ROM pin out)
MX27C8100PC-12 120 60 100 42 Pin DIP(ROM pin out)
MX27C8100PC-15 150 60 100 42 Pin DIP(ROM pin out)
MX27C8100PC-20 200 60 100 42 Pin DIP(ROM pin out)
MX27C8100MC-10 100 60 100 44 Pin SOP(ROM pin out)
MX27C8100MC-12 120 60 100 44 Pin SOP(ROM pin out)
MX27C8100MC-15 150 60 100 44 Pin SOP(ROM pin out)
MX27C8100MC-20 200 60 100 44 Pin SOP(ROM pin out)

P/N: PM0261

11

REV. 2.3, NOV. 12, 2001

PACKAGE INFORMATION

42-PIN PLASTIC DIP(600 mil)

MX27C8100

P/N: PM0261

12

REV. 2.3, NOV. 12, 2001

44-PIN PLASTIC SOP

MX27C8100

P/N: PM0261

13

REV. 2.3, NOV. 12, 2001

MX27C8100

Revision History

Revision No. Description Page Date

2.0 1) Eliminate Interactive Programming Mode. 5/30/1997

2) Programming pulse change from 100us to 50us

2.1 IPP : 100uA----> 10uA 8/8/1997

2.2 Modify Package Information P12,13 JAN/12/2000

2.3 Modify Package Information: change title P12 NO V/12/2001
Modify Package Information: add coplanarity parameter P13

P/N: PM0261

14

REV. 2.3, NOV. 12, 2001

MX27C8100

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MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.

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