Datasheet MX27C256QC-45, MX27C256QC-55, MX27C256QC-70, MX27C256QC-90, MX27C256QI-10 Datasheet (MXIC)

SYMBOL PIN NAME

A0~A14 Address Input
Q0~Q7 Data Input/Output
CE Chip Enable Input
OE Output Enable Input
VPP Program Supply Voltage
NC No Internal Connection
VCC Power Supply Pin (+5V)
GND Ground Pin

GENERAL DESCRIPTION

The MX27C256 is a 5V only, 256K-bit, ultraviolet Eras­able Programmable Read Only Memory. It is organized
as 32K by 8 bits, operates from a single + 5volt supply,
has a static standby mode, and features fast single
address location programming. All programming
signals are TTL levels, requiring a single pulse. For
programming from outside the system, existing

FEATURES

• 32K x 8 organization

• Single +5V power supply

• +12.5V programming voltage

• Fast access time: 45/55/70/90/100/120/150 ns

• Totally static operation

• Completely TTL compatible

• Operating current: 30mA

• Standby current: 100uA

• Package type:

- 28 pin plastic DIP

- 32 pin PLCC

- 28 pin 8 x 13.4mm TSOP(I)

1

PIN CONFIGURATIONS

PDIP

EPROM programmers may be used. The MX27C256
supports intelligent fast programming algorithm which
can result in programming time of less than ten seconds.

This EPROM is packaged in industry standard 28 pin
dual-in-line packages, 32 lead PLCC, and 28 lead
TSOP(I) packages.

REV. 5.3, SEP. 19, 2001P/N: PM0203

BLOCK DIAGRAM

PIN DESCRIPTION

PLCC

8 x 13.4mm 28-TSOP(I)

MX27C256

256K-BIT [32K x 8] CMOS EPROM

1

4

5

9

13

14 17 20

21

25

29

32

30

A8
A9
A11
NC
OE
A10
CE
Q7
Q6

A6
A5
A4
A3
A2
A1

A0
NC
Q0

Q1

Q2

GND

NC

Q3Q4Q5

A7

A12

VPPNCVCC

A14

A13

MX27C256

1
2
3
4
5
6
7
8
9
10
11
12
13
14

VPP

A12

A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2

GND

28
27
26
25
24
23
22
21
20
19
18
17
16
15

VCC
A14
A13
A8
A9
A11
OE
A10
CE
Q7
Q6
Q5
Q4
Q3

MX27C256

OE

A11

A9

A8
A13
A14

VCC

VPP

A12

A7

A6

A5

A4

A3

22
23
24
25
26
27
28
1
2
3
4
5
6
7

A10
CE
Q7
Q6
Q5
Q4
Q3
GND
Q2
Q1
Q0
A0
A1
A2

21
20
19
18
17
16
15
14
13
12
11
10

9
8

MX27C256

CONTROL

LOGIC

OUTPUT

BUFFERS

Q0~Q7

CE
OE

A0~A14

ADDRESS

INPUTS

Y-DECODER

X-DECODER

Y-SELECT

256K BIT

CELL

MAXTRIX

VCC
GND

VPP

.
.
.
.
.
.
.
.

.
.
.
.
.
.
.
.

2

P/N:PM0203

REV.5.3, SEP. 19, 2001

MX27C256

AUTO IDENTIFY MODE

The auto identify mode allows the reading out of a binary
code from an EPROM that will identify its manufacturer
and device type. This mode is intended for use by
programming equipment for the purpose of
automatically matching the device to be programmed
with its corresponding programming algorithm. This
mode is functional in the 25°C ± 5°C ambient
temperature range that is required when programming
the MX27C256.

To activate this mode, the programming equipment
must force 12.0 ± 0.5 (VH) on address line A9 of the
device. Two identifier bytes may then be sequenced
from the device outputs by toggling address line A0 from
VIL to VIH. All other address lines must be held at VIL
during auto identify mode.

Byte 0 ( A0 = VIL) represents the manufacturer code,
and byte 1 (A0 = VIH), the device identifier code. For the
MX27C256, these two identifier bytes are given in the
Mode Select Table. All identifiers for manufacturer and
device codes will possess odd parity, with the MSB (Q7)
defined as the parity bit.

READ MODE

The MX27C256 has two control functions, both of which
must be logically satisfied in order to obtain data at the
outputs. Chip Enable (CE) is the power control and
should be used for device selection. Output Enable
(OE) is the output control and should be used to gate
data to the output pins, independent of device selection.
Assuming that addresses are stable, address access
time (tACC) is equal to the delay from CE to output (tCE).
Data is available at the outputs tOE after the falling edge
of OE, assuming that CE has been LOW and addresses
have been stable for at least tACC - tOE.

STANDBY MODE

The MX27C256 has a CMOS standby mode which
reduces the maximum Vcc current to 100 uA. It is
placed in CMOS standby when CE is at VCC ± 0.3 V.
The MX27C256 also has a TTL-standby mode which
reduces the maximum VCC current to 1.5 mA. It is
placed in TTL-standby when CE is at VIH. When in
standby mode, the outputs are in a high-impedance
state, independent of the OE input.

FUNCTIONAL DESCRIPTION

THE PROGRAMMING OF THE MX27C256

When the MX27C256 is delivered, or it is erased, the
chip has all 256K bits in the "ONE" or HIGH state.
"ZEROs" are loaded into the MX27C256 through the
procedure of programming.

For programming, the data to be programmed is applied
with 8 bits in parallel to the data pins.

VCC must be applied simultaneously or before VPP, and
removed simultaneously or after VPP. When
programming an MXIC EPROM, a 0.1uF capacitor is
required across VPP and ground to suppress spurious
voltage transients which may damage the device.

FAST PROGRAMMING

The device is set up in the fast programming mode when
the programming voltage VPP = 12.75V is applied, with
VCC = 6.25 V and OE = VIH (Algorithm is shown in
Figure 1). The programming is achieved by applying a
single TTL low level 100us pulse to the CE input after
addresses and data line are stable. If the data is not
verified, an additional pulse is applied for a maximum of
25 pulses. This process is repeated while sequencing
through each address of the device. When the
programming mode is completed, the data in all address
is verified at VCC = VPP = 5V ± 10%.

PROGRAM INHIBIT MODE

Programming of multiple MX27C256s in parallel with
different data is also easily accomplished by using the
Program Inhibit Mode. Except for CE and OE, all like
inputs of the parallel MX27C256 may be common. A
TTL low-level program pulse applied to an MX27C256
CE input with VPP = 12.5 ± 0.5 V and OE HIGH will
program that MX27C256. A high-level CE input inhibits
the other MX27C256s from being programmed.

PROGRAM VERIFY MODE

Verification should be performed on the programmed
bits to determine that they were correctly programmed.
The verification should be performed with CE and OE
at VIL, and VPP at its programming voltage.

3

P/N:PM0203

REV.5.3, SEP. 19, 2001

MX27C256

TWO-LINE OUTPUT CONTROL FUNCTION

To accommodate multiple memory connections, a two­line control function is provided to allow for:

1. Low memory power dissipation,

2. Assurance that output bus contention will not
occur.

It is recommended that CE be decoded and used as the
primary device-selecting function, while OE be made a
common connection to all devices in the array and
connected to the READ line from the system control bus.
This assures that all deselected memory devices are in
their low-power standby mode and that the output pins
are only active when data is desired from a particular
memory device.

SYSTEM CONSIDERATIONS

During the switch between active and standby
conditions, transient current peaks are produced on the
rising and falling edges of Chip Enable. The magnitude
of these transient current peaks is dependent on the
output capacitance loading of the device. At a minimum,
a 0.1 uF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
VCC and GND to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on EPROM
arrays, a 4.7 uF bulk electrolytic capacitor should be
used between Vcc and GND for each eight devices. The
location of the capacitor should be close to where the
power supply is connected to the array.

MODE SELECT TABLE

PINS

MODE CE OE A0 A9 VPP OUTPUTS

Read VIL VIL X X VCC DOUT
Output Disable VIL VIH X X VCC High Z
Standby (TTL) VIH X X X VCC High Z
Standby (CMOS) VCC±0.3V X X X VCC High Z
Program VIL VIH X X VPP DIN
Program Verify VIH VI L X X V PP DOUT
Program Inhibit VIH VIH X X VPP High Z
Manufacturer Code(3) VIL VIL VIL VH VCC C2H
Device Code(3) VIL VIL VIH VH VCC 10H

4. See DC Programming characteristics for VPP voltage during
programming.

NOTES: 1. VH = 12.0 V ± 0.5 V

2. X = Either VIH or VIL

3. A1 - A8 = A10 - A14 = VIL(For auto select)

4

P/N:PM0203

REV.5.3, SEP. 19, 2001

MX27C256

ST AR T

ADDRESS = FIRST LOCATION

VCC = 6.25V
VPP = 12.75V

X = 0

PROGRAM ONE 100us PULSE

INCREMENT X

X = 25?

VERIFY BYTE

LAST ADDRESS

VCC = VPP = 5.25V

DEVICE PASSED

VERIFY ALL BYTES

?

DEVICE FAILED

INCREMENT ADDRESS

INTERACTIVE
SECTION

VERIFY SECTION

FAIL

PASS

YES

PASS

NO

YES

NO

FAIL

FIGURE 1. FAST PROGRAMMING FLOW CHART

FAIL

?

5

P/N:PM0203

REV.5.3, SEP. 19, 2001

MX27C256

SWITCHING TEST CIRCUITS

SWITCHING TEST WAVEFORMS

DEVICE
UNDER

TEST

DIODES = IN3064
OR EQUIVALENT

CL = 100 pF including jig capacitance(30pF for 45/55/70ns parts)

6.2K ohm

1.8K ohm
+5V

CL

2.0V

0.8V

TEST POINTS

INPUT

2.0V

0.8V
OUTPUT

AC TESTING: AC driving levels are 2.4V/0.4V for commercial grade, 3.0V/0V for industrial grade.

Input pulse rise and fall times are < 10ns.

AC driving levels

1.5V

TEST POINTS

INPUT

1.5V

OUTPUT

AC TESTING: (1) AC driving levels are 3.0V/0V for both commercial grade and industrial grade.

Input pulse rise and fall times are < 10ns.
(2) For MX27C256-45, MX27C256-55, MX27C256-70.

AC driving levels

6

P/N:PM0203

REV.5.3, SEP. 19, 2001

MX27C256

ABSOLUTE MAXIMUM RATINGS

RATING VALUE

Ambient Operating Temperature -40oC to 85oC
Storage Temperature -65oC to 125oC
Applied Input Voltage -0.5V to 7.0V
Applied Output Voltage -0.5V to VCC + 0.5V
VCC to Ground Potential -0.5V to 7.0V
A9 & Vpp -0.5V to 13.5V

NOTICE:

Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended period may affect reliability.

NOTICE:

Specifications contained within the following tables are subject to
change.

DC CHARACTERISTICS

SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS

VOH Output High Voltage 2.4 V IOH = -0.4mA
VOL Output Low Voltage 0.4 V IOL = 2.1mA
VIH Input High Voltage 2.0 VCC + 0.5 V
VIL Input Low Voltage -0.3 0.8 V
ILI Input Leakage Current -10 10 uA VIN = 0 to 5.5V
ILO Output Leakage Current -10 10 uA VOUT = 0 to 5.5V
ICC3 VCC Power-Down Current 100 uA CE = VCC ± 0.3V
ICC2 VCC Standby Current 1.5 mA CE = VIH
ICC1 VCC Active Current 30 mA CE = VIL, f=5MHz, Iout = 0mA
IPP VPP Supply Current Read 10 uA CE = OE = VIL, VPP = 5.5V

CAPACITANCE TA = 25

o

C, f = 1.0 MHz (Sampled only)

SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS

CIN Input Capacitance 8 12 pF VIN = 0V
COUT Output Capacitance 8 12 pF VOUT = 0V
VPP VPP Capacitance 18 25 pF VPP = 0V

DC/AC Operating Conditions for Read Operation

MX27C256

-45 -55 -70 -90 -10 -12 -15

Operating Commercial 0 °C to 70°C0°C to 70°C0°C to 70°C0°C to 70°C0°C to 70°C0°C to 70°C0°C to 70°C
Temperature Industrial -45°C to 85°C -40°C to 85 °C -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C
Vcc Power Supply 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% 5V ±10% 5V ± 10% 5V ± 10%

7

P/N:PM0203

REV.5.3, SEP. 19, 2001

MX27C256

AC CHARACTERISTICS

27C256-45 27C256-55 27C256-70 27C256-90

SYMBOL PARAMETER MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. UNIT CONDITIONS

tACC Address to Output Delay 45 55 70 90 ns CE = OE = VIL
tCE Chip Enable to Output Delay 45 55 70 90 ns OE = VIL
tOE Output Enable to Output 22 30 35 40 ns CE = VIL

Delay

tDF OE High to Output Float, 0 16 0 20 0 20 0 25 ns

or CE High to Output Float

tOH Output Hold from Address, 0 0 0 0 ns

CE or OE which ever occurred
first

27C256-10 27C256-12 27C256-15

SYMBOL PARAMETER MIN. MAX. MIN. MAX. MIN. MAX. UNIT CONDITIONS

tACC Address to Output Delay 100 120 150 ns CE = OE = VIL
tCE Chip Enable to Output Delay 100 120 150 ns OE = VIL
tOE Output Enable to Output 45 50 55 ns CE = VIL

Delay

tDF OE High to Output Float, 0 30 0 35 0 50 ns

or CE High to Output Float

tOH Output Hold from Address, 0 0 0 ns

CE or OE which ever occurred
first

DC PROGRAMMING CHARACTERISTICS TA = 25

o

C ± 5°C

SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS

VOH Output High Voltage 2.4 V IOH = -0.40mA
VOL Output Low Voltage 0.4 V IOL = 2.1mA
VIH Input High Voltage 2.0 VCC + 0.5 V
VIL Input Low Voltage -0.3 0.8 V
ILI Input Leakage Current -10 10 uA VIN = 0 to 5.5V
VH A9 Auto Select Voltage 11.5 12.5 V
ICC3 VCC Supply Current(Program & Verify) 40 mA
IPP2 VPP Supply Current(Program) 30 mA CE = VIL, OE = VIH
VCC1 Fast Programming Supply Voltage 6.00 6.50 V
VPP1 Fast Programming Voltage 12.5 13.0 V

8

P/N:PM0203

REV.5.3, SEP. 19, 2001

MX27C256

AC PROGRAMMING CHARACTERISTICS TA = 25

o

C ± 5°C

SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS

tAS Address Setup Time 2.0 us
tOES OE Setup Time 2.0 us
tDS Data Setup Time 2.0 us
tAH Address Hold Time 0 us
tDH Data Hold Time 2.0 us
tDFP Output Enable to Output Float Delay 0 130 ns
tVPS VPP Setup Time 2.0 us
tVCS VCC Setup Time 2.0 us
tOE Data Valid from OE 150 ns
tPW PGM Program Pulse Width 95 105 us

9

P/N:PM0203

REV.5.3, SEP. 19, 2001

MX27C256

WVEFORMS

READ CYCLE

FAST PROGRAMMING ALGORITHM WAVEFORM

ADDRESS

INPUTS

DATA

OUT

OE

CE

DATA ADDRESS

VALID DATA

tDF

tACC

tCE

tOE

tOH

Addresses

CE

OE

DATA

VPP

VCC

VIH

VIL

VPP1

VCC

VCC1

VCC

VIH

VIL

VIH

VIL

DATA OUT VALID

Hi-z

DATA IN STABLE

tAS

tVPS

tVCS

tOE
Max

tPW

tDS

tDH

tOES

tDFP

tAH

PROGRAM VERIFY

PROGRAM

10

P/N:PM0203

REV.5.3, SEP. 19, 2001

MX27C256

PLASTIC PACKAGE

PART NO. ACCESS TIME(ns) OPERATING STANDBY OPERATING PACKAGE

CURRENT MAX.(mA) CURRENT MAX.(uA) TEMPERATURE

MX27C256PC-45 45 30 100 0°C to 70°C 28 Pin DIP
MX27C256QC-45 45 30 100 0°C to 70°C 32 Pin PLCC
MX27C256TC-45 45 30 100 0°C to 70°C 28 Pin TSOP(I)
MX27C256PC-55 55 30 100 0°C to 70°C 28 Pin DIP
MX27C256QC-55 55 30 100 0°C to 70°C 32 Pin PLCC
MX27C256TC-55 55 30 100 0°C to 70°C 28 Pin TSOP(I)
MX27C256PC-70 70 30 100 0°C to 70°C 28 Pin DIP
MX27C256QC-70 70 30 100 0°C to 70°C 32 Pin PLCC
MX27C256TC-70 70 30 100 0°C to 70°C 28 Pin TSOP(I)
MX27C256PC-90 90 30 100 0°C to 70°C 28 Pin DIP
MX27C256QC-90 90 30 100 0°C to 70°C 32 Pin PLCC
MX27C256TC-90 90 30 100 0°C to 70°C 28 Pin TSOP(I)
MX27C256PC-10 100 30 100 0°C to 70°C 28 Pin DIP
MX27C256QC-10 100 30 100 0°C to 70°C 32 Pin PLCC
MX27C256TC-10 100 30 100 0°C to 70°C 28 Pin TSOP(I)
MX27C256PC-12 120 30 100 0°C to 70°C 28 Pin DIP
MX27C256QC-12 120 30 100 0°C to 70°C 32 Pin PLCC
MX27C256TC-12 120 30 100 0°C to 70°C 28 Pin TSOP(I)
MX27C256PC-15 150 30 100 0°C to 70°C 28 Pin DIP
MX27C256QC-15 150 30 100 0°C to 70°C 32 Pin PLCC
MX27C256TC-15 150 30 100 0°C to 70°C 28 Pin TSOP(I)
MX27C256PI-45 45 30 100 -40°C to 85°C 28 Pin DIP
MX27C256QI-45 45 30 100 -40 °C to 85°C 32 Pin PLCC
MX27C256TI-45 45 30 100 -40°C to 85°C 28 Pin TSOP(I)
MX27C256PI-55 55 30 100 -40°C to 85°C 28 Pin DIP
MX27C256QI-55 55 30 100 -40 °C to 85°C 32 Pin PLCC
MX27C256TI-55 55 30 100 -40°C to 85°C 28 Pin TSOP(I)
MX27C256PI-70 70 30 100 -40°C to 85°C 28 Pin DIP
MX27C256QI-70 70 30 100 -40 °C to 85°C 32 Pin PLCC
MX27C256TI-70 70 30 100 -40°C to 85°C 28 Pin TSOP(I)
MX27C256PI-90 90 30 100 -40°C to 85°C 28 Pin DIP
MX27C256QI-90 90 30 100 -40 °C to 85°C 32 Pin PLCC
MX27C256TI-90 90 30 100 -40°C to 85°C 28 Pin TSOP(I)
MX27C256PI-10 100 30 100 -40°C to 85°C 28 Pin DIP
MX27C256QI-10 100 30 100 -40 °C to 85°C 32 Pin PLCC
MX27C256TI-10 100 30 100 -40°C to 85°C 28 Pin TSOP(I)
MX27C256PI-12 120 30 100 -40°C to 85°C 28 Pin DIP
MX27C256QI-12 120 30 100 -40 °C to 85°C 32 Pin PLCC
MX27C256TI-12 120 30 100 -40°C to 85°C 28 Pin TSOP(I)
MX27C256PI-15 150 30 100 -40°C to 85°C 28 Pin DIP
MX27C256QI-15 150 30 100 -40 °C to 85°C 32 Pin PLCC
MX27C256TI-15 150 30 100 -40°C to 85°C 28 Pin TSOP(I)

ORDERING INFORMATION

11

P/N:PM0203

REV.5.3, SEP. 19, 2001

MX27C256

PACKAGE INFORMATION

28-PIN PLASTIC DIP (600 mil)

12

P/N:PM0203

REV.5.3, SEP. 19, 2001

MX27C256

32-PIN PLASTIC LEADED CHIP CARRIER (PLCC)

13

P/N:PM0203

REV.5.3, SEP. 19, 2001

MX27C256

8 x 13.4mm 28-PIN PLASTIC TSOP

14

P/N:PM0203

REV.5.3, SEP. 19, 2001

MX27C256

REVISION HISTORY

Revision No. Description Page Date

5.0 1) Reduce operating current from 40mA to 30mA. 6/16/1997

2) Add 28-TSOP(I) and 28-SOP packages offering.

3) Eliminate Interactive Programming Mode.

5.1 1) IPP1 100uA ----> 10uA 7/17/1997

5.2 Cancel ceramic DIP package type P1,2,10,12 FEB/25/2000

5.3 Remove 28-pin SOP Package P1,10 SEP/19/2001
Package Information format changed P11~13

MX27C256

15

MACRONIX INTERNATIONAL CO., LTD.

HEADQUARTERS:

TEL:[phone]
FAX:[phone]

EUROPE OFFICE:

TEL:[phone]
FAX:[phone]

JAPAN OFFICE:

TEL:[phone]
FAX:[phone]

SINGAPORE OFFICE:

TEL:[phone]
FAX:[phone]

TAIPEI OFFICE:

TEL:[phone]
FAX:[phone]

MACRONIX AMERICA, INC.

TEL:[phone]
FAX:[phone]

CHICAGO OFFICE:

TEL:[phone]
FAX:[phone]

http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.