Datasheet MX23L12822YC-12, MX23L12822MC-12 Datasheet (MXIC)

FEATURES

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51
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44

NC

A0
A1
A2
A3
A4

A5
NC
NC

VCC

D0

D16

D1

D17

VSS

VCC

D2

D18

D3

D19

NC
NC

D4

D20

D5

D21

VSS

VCC

D6

D22

D7

D23

VSS

A6

A7

A8

A9

A10
A11
A12
A13

NC
NC

NC
NC
NC
A21
A20
WORD
OE
CE
NC
VSS
NC
D31/A-1
D15
D30
D14
VSS
VCC
D29
D13
D28
D12
NC
D27
D11
D26
D10
VSS
VCC
D25
D9
D24
D8
VCC
A19
A18
A17
A16
A15
A14
NC
NC
NC
NC

MX23L12822

MX23L12822

128M-BIT (8M x 16 / 4M x 32) MASK ROM WITH PAGE MODE

• Bit organization

- 8M x 16 (byte mode)

- 4M x 32 (double word mode)

• Fast access time

- Random access: 120ns (max.)

- Page access: 30ns (max.)

• Page Size

- 8 double words per page

• Current

- Operating: 75mA (max.)

- Standby: 15uA (max.)

• Supply voltage

- 3.3V±10%

• Package

- 70 pin SSOP (500 mil)

- 86 pin TSOP(2)

PIN CONFIGURATION

70 SSOP

70

A0

2

A1

3

A2

4

A3

5

A4

6

A5

7

VCC

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P/N:PM0561 REV. 1.5, DEC. 26, 2000

D16

D17
VSS
VCC

D18

D19

D20

D21
VSS
VCC

D22

D23
VSS

A10

A11

A12

D0

9
10

D1

11
12
13
14

D2

15
16

D3

17
18

D4

19
20

D5

D6

D7

A6
A7
A8
A9

21
22
23
24
25
26
27
28
29
30
31
32
33
34
35

MX23L12822

NC

69

A21

68

A20

67

WORD

66

OE

65

CE

64

VSS

63

D31/A-1

62

D15

61

D30

60

D14

59

VSS

58

VCC

57

D29

56

D13

55

D28

54

D12

53

D27

52

D11

51

D26

50

D10

49

VSS

48

VCC

47

D25

46

D9

45

D24

44

D8

43

VCC

42

A19

41

A18

40

A17

39

A16

38

A15

37

A14

36

A13

86 TSOP

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MX23L12822

ORDER INFORMATION

Part No. Access Time Page Access Time Package
MX23L12822MC-12 120ns 30ns 70 pin SSOP
MX23L12822YC-12 120ns 30ns 86 pin TSOP

PIN DESCRIPTION

Symbol Pin Function
A0~A21 Address Inputs
D0~D30 Data Outputs
D31/A-1 D31 (Double Word Mode)/ LSB Address (W ord Mode)
CE Chip Enable Input
OE Output Enab le Input
Word Double Word/ W ord Mode Selection
VCC Pow er Supply Pin
VSS Ground Pin
NC No Connection

MODE SELECTION

CE OE Word D31/A-1 D0~D15 D16~D31 Mode Power
H X X X High Z High Z - Stand-by
L H X X High Z High Z - Active
L L H Output D0~D15 D16~D31 Double Word Active
L L L Input D0~D15 High Z Word Active

P/N:PM0561

REV. 1.5, DEC. 26, 2000

2

MX23L12822

BLOCK DIAGRAM

A0/(A-1)

A2

A3

A21

CE

WORD

OE

Address

Buffer

Memory

Array

Page

Buffer

Page

Decoder

ABSOLUTE MAXIMUM RATINGS

Item Symbol Ratings
V oltage on any Pin Relativ e to VSS VIN -1.3V to 2.0V
Ambient Operating Temperature T opr 0°C to 70°C
Storage T emperature Tstg -65°C to 125°C

Double

Word/

Word

Output

Buffer

D0

D31/(D15)

Note: Minimum DC v oltage on input or I/O pins is -0.5V.
During voltage transitions, inputs may undershoot VSS
to -1.3V for periods of up to 20ns. Maximum DC voltage
on input or I/O pins is VCC+0.5V. During v oltage transi­tions, input may overshoot VCC to VCC+2.0V for peri­ods of up to 20ns.

DC CHARACTERISTICS (Ta = 0°C ~ 70°C, VCC = 3.3V±10%)

Item Symbol MIN. MAX. Conditions
Output High Voltage VOH 2.4V - IOH = -0.4mA
Output Low Voltage VOL - 0.4V IOL = 1.6mA
Input High Voltage VIH 2.2V VCC+0.3V
Input Low Voltage VIL -0.3V 0.8V
Input Leakage Current ILI - 5uA 0V, VCC
Output Leakage Current ILO - 5uA 0V , VCC
Operating Current ICC1 - 75mA tRC = 120ns, all output open,

with normal sequential access

testing pattern
Standby Current (TTL) ISTB1 - 1mA CE = VIH
Standby Current (CMOS) ISTB2 - 15uA CE>VCC-0.2V
Input Capacitance CIN - 10pF Ta = 25°C, f = 1MHZ
Output Capacitance COUT - 10pF Ta = 25°C, f = 1MHZ

P/N:PM0561

REV. 1.5, DEC. 26, 2000

3

AC CHARACTERISTICS (Ta = 0°C ~ 70°C, VCC = 3.3V±10%)

Item Symbol 23L12822-12

MIN. MAX.
Read Cycle Time tRC 120ns ­Address Access Time tAA - 120ns
Chip Enable Access Time tACE - 120ns
Page Mode Access Time tPA - 30ns
Output Enable Time tOE - 30ns
Output Hold After Address tOH 0ns ­Output High Z Delay tHZ - 20ns

Note:Output high-impedance delay (tHZ) is measured
from OE or CE going high, and this parameter guaran­teed by design over the full v oltage and temperature op­erating range - not tested.

AC T est Conditions

MX23L12822

Input Pulse Levels 0.4V~ 2.4V
Input Rise and Fall Times 10ns
Input Timing Level 1.4V
Output Timing Level 1.4V
Output Load See Figure

IOH (load)=-0.4mA

DOUT

IOL (load)=1.6mA

Note:No output loading is present in tester load board.
Active loading is used and under software programming control.
Output loading capacitance includes load board's and all stray capacitance.

C<100pF

P/N:PM0561

REV. 1.5, DEC. 26, 2000

4

TIMING DIAGRAM

RANDOM READ

MX23L12822

PAGE READ

(A-1),A0,A1,A2

ADD

CE

OE

DATA

A3-A21

DATA

ADD

tACE

tOE

1'st ADD

tAA

VALID

VALID

tAA

2'nd ADD

tPA

VALID

ADD

tRC

VALID ADD

VALID

3'rd ADD

VALID

tOH

ADD

tHZ

VALID

P/N:PM0561

Note: CE, OE are enable.
Page size is 8 double words in 32-bit mode, 16 words in 16-bit mode.

REV. 1.5, DEC. 26, 2000

5

MX23L12822

Revision History

Revision # Description Page Date

1.3 DC Characteristics ISTB2(CMOS Standby Current) 5uA-->15uA P3 DEC/15/1999

1.4 Operating Current (ICC1) 60mA-->75mA P1,3 JAN/14/2000

1.5 Modify Pin Configuration--86 TSOP D31-->D31/A-1 P1 DEC/26/2000

P/N:PM0561

REV. 1.5, DEC. 26, 2000

6

MX23L12822

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