The MX105A is a monolithic CMOS tone detector for tone decoding in single and multitone signaling systems. Using
phase locked loop (PLL) decoding techniques, the MX105A recognizes tones in the presence of high noise levels and
strong adjacent channel tones. Detection frequency and bandwidth can each be independently adjusted. The design is
immune to high levels of harmonic and sub-harmonic noise. It also maintains excellent noise immunity and constant
bandwidth over a wide range of input signal levels.
The MX105A requires a voltage supply of 2.7V to 5.5V and is available in the following package styles: 16-pin SOIC
(MX105ADW), 16-pin PDIP (MX105AP), and 24-pin PLCC (MX105ALH).
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Tone Detector6MX105A PRELIMINARY INFORMATION
4. General Description
The MX105A implements a frequency detector with a phase locked loop (PLL) and a lock detector. The voltage controlled
oscillator (VCO) center frequency, detection bandwidth, loop filter, and detect filter are all independently controlled by
external components.
The MX105A provides a pair of pseudo-sinewave multipliers for splitting the input signal into approximately orthogonal
components. These multipliers are implemented with commutating filters (cyclically sampling filters) which translate an in
band AC input signal to DC. The commutating loop filter is used as the phase detector of the PLL while the commutating
detect filter provides for lock detection. Each pseudo-sinewave has a cyclic form (1 1 0 -1 -1 0) to eliminate low order
harmonic responses. The loop filter produces an error signal, which when applied to the VCO input allows frequency
locking. A limiter between the loop filter output and the VCO input provides tunable control of the detection bandwidth
(BW). Once lock is achieved the detect filter produces a DC value proportional to the input tone amplitude. An internally
generated reference is compared to the detect filter output to determine whether the PLL is locked to an input tone. Once
lock is determined the internal reference is reduced by 50% to minimize output chatter with marginal input signals.
The sampling clocks of the detect filter lag those of the loop filter by 60°. To improve performance, a capacitor (C4) can
be used to phase shift the input to the loop filter by 30°. This shifts all sampling clocks an additional 30° relative to the
input tone to phase align the detect filter sampling clocks with the amplitude peaks of the input tone.
Figure 3 shows the sampling clocks relative to an in band input tone; this figure represents the steady state ‘locked’
condition without C4.
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Tone Detector7MX105A PRELIMINARY INFORMATION
5. Application
The external components shown in Figure 2 are used to adjust the various performance parameters of the MX105A. The
signal-to-noise performance, response time and signal bandwidth are all interrelated factors which should be optimized to
meet the requirements of the application.
By selecting component values in accordance with the following formulas, optimum circuit performance is obtained for any
given application.
First define the following application parameters:
A. The center frequency to be detected (f
B. The MX105A Minimum Usable Bandwidth (MUBW). This is obtained by taking into account the worst case
tolerances on the input tone frequency and variations in the MX105A f
effect of the MX105A and its supporting components.
C. The maximum permissible MX105A response time.
D. The minimum input signal amplitude.
Note: Using this information the appropriate component values can be calculated, and the signal-to-noise performance
can be read from a chart. Do not add large safety margins for response time and minimum signal amplitude;
reasonable margins are already included in the formulas. Excessive margins may result in reduced noise immunity.
5.1 Method for Calculating External Component Values
The examples on the following pages demonstrate the calculation of component values for any given application. For the
purpose of the examples, the values below are used:
A. f
= 2800 Hz
0
B. ∆TEMP = 100 °C, ∆ V
C. Maximum allowed response time = 50ms
D. Minimum input signal amplitude = 200 mV
= 1V, ∆fIN = 0.5%
DD
).
0
due to supply voltage and any temperature
0
.
RMS
5.2 Define f
The components R1, C1
0
and C1B set the free running frequency of the VCO and therefore the f0 of the MX105A. As
A
shown below, the frequency of 2800 Hz corresponds to a capacitor value of 220pF and a resistor value of 385 kΩ. This
resistance can be achieved with a 300 kΩ fixed resistor for R1
C1
and C1B should include 10-20pF parasitic capacitance due to the device and its package plus any board parasitic
A
and for R1V a 100 kΩ potentiometer. The capacitance of
F
capacitance.
=
f
0
⋅+
K R1(C1C1 )
1
AB
⇒× =
R1 C1
A
2Kf
1
0
where : K=2.1 ± 5%
R1=(R1
+ R1V)
F
5.3 Calculate Minimum Usable Bandwidth
Minimum Usable Bandwidth (MUBW) is the TOTAL bandwidth required for the following:
A. Input signal frequency tolerance
B. MX105A f
C. MX105A f
Note: Add A, B and C and express as TOTAL bandwidth, not as a ± percentage (%) value.
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+
=
=
6%
2
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Tone Detector8MX105A PRELIMINARY INFORMATION
5.5 Select R4 for Operating BW
R4
=
10.35 BW
=
−
×
4.8 BW
The exact bandwidth given by any value of R4 will vary slightly. In applications where an exact bandwidth is required, R4
should be a variable resistor to permit adjustment.
×
4.8 6
10.35 6
−
≈Ω
6.8k
5.6 Calculate R2×C2
For a frequency of 2800 Hz, a bandwidth of 6%, and a choice of
A
×≈
R2 C2
A
100
××
3f BW
0
=⇒=µΩ
C20.01 FR200k
AV
.
Note: Use nearest preferred values.
5.7 Define Maximum Allowed Response Time
The maximum response time (TON) is the sum of the VCO lock time (T
The MX105A’s T
must not exceed the maximum time allowed for the application, but a value lying near the maximum
ON
gives the best S/N performance.
A. Calculate T
LOCK
T
LOCK
150
=
×
fBW
0
Using the formula above, for a frequency of 2800 Hz and a bandwidth of 6% the approximate Lock time (T
ms. Since the maximum response time is 50 ms, a DETECT time of 41 ms is allowed.
Note: T
B. Calculate Maximum Allowable T
C. Define Minimum Expected Signal Amplitude
This is used in calculating T
may vary from near zero to the value given, causing corresponding variations in actual TON.
LOCK
DETECT
DETECT
components.
TTT
DETECTONLOCK
()
=−
V
IN
MIN
MAX
) and the DETECT integration time (T
LOCK
LOCK
DETECT
) will be 9
).
5.8 Calculate R3×C3
A
Note:
1. For a signal amplitude of 200 mV
a T
DETECT
time of 20ms. This in turn yields a response time of 9ms + 20 ms = 29ms.
2. Use nearest preferred values.
T
R3 C3
×≈
A
where: V
, a resistor value R3 of 510 kΩ with a 0.1µF capacitor for C3A and C3B will yield
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Tone Detector9MX105A PRELIMINARY INFORMATION
5.9 Calculate Maximum De-response Time
T3ln
≈− ×
OFF
where: V
is the detect filter sensitivity.
TH
V
TH
V
IN
MAX
R3 C3
×
A
For improved de-response time, a diode (1N914 or similar) can be placed between pins 5 and 6, as shown in Figure 3.
The formula and figure below show the approximate time the MX105A will take to turn off after an in-band signal has been
removed. The effect of this diode is to greatly reduce the turn-off time with signal input amplitudes greater than 300
mV
. This graph is for VDD = 5V; for lower VDD KDT increases.
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Tone Detector10MX105A PRELIMINARY INFORMATION
g
5.10 Calculate Signal to Noise Performance
Worst-case S/N calculations depend on calculation of a value “M” using the formula shown below:
R3 C3
×
×
00185.
A
A
=
.
M =
∞
M = 1
M
=
3R2C2
××
substituting example values,
510 0.1
=
M
××
3200
By substituting this value for M in Figure 5, the minimum required S/N of an in band tone with respect to an adjacent
interfering tone can be found. This then has to be increased depending on the input tone amplitude.
-28
-24
-20
M = 0.33
-16
M = 0.1
-12
-8
-4
0
1
24
6810
Number of Bandwidths Separation
Figure 5: S/N vs. BW Separation
The following formula expresses the reduction in noise immunity as the input signal approaches the detect filter sensitivity
.
V
TH
required
S
= 20lo
N
V
VV
INTH
+
S
N
Figure 5
IN
−
If this S/N is better than required for the application, R3×C3
can be reduced, or the operating bandwidth can be
A
increased to obtain a faster tone detection time.
If the S/N performance is not adequate, the operating bandwidth can be reduced toward the MUBW, or R3C3
can be
A
increased to improve S/N performance at the expense of slower response time.
5.11 Calculate C4 for 30° Phase Shift
Capacitor C4 is used to phase shift the input to the VCO commutating filter by 30°, thereby shifting the sampling clocks by
the same amount. This enables the Detect sampling filter to sample and integrate at the maximum and minimum of the
input tone.
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Tone Detector12MX105A PRELIMINARY INFORMATION
6.1.3 Operating Characteristics
For the following conditions unless otherwise specified:
V
= 5.0 V @ T
DD
AMB
= 25°C
Load resistance on decoder output = 20kΩ.
NotesMin.Typ.Max.Units
Static Parameters
I
DD
Amplifier Input Impedance160200
Digital Output Impedance5001000
Analog Output Impedance10001200
1.0mA
k
Ω
Ω
Ω
Dynamic Parameters
Input Signal
Frequency4020,000Hz
Lowest Must Detect Level130mV
Highest Will Not Detect Level120mV
Highest Will Not Detect f0/21, 230
790
Highest Will Not Detect 5(f0)1, 220
250
mV
mV
RMS
RMS
dB
RMS
dB
RMS
VCO
Frequency3120120,000Hz
Frequency Stability100ppm/°C
5000ppm/V
BW Limiter
BW Range210%f
0
Amplifier
Open Loop Gain60dB
GBWP1.0MHz
Closed Loop Gain0dB
Detect Commutating Filter
Sensitivity (VTH)125mV
RMS
Operating Characteristics Notes:
1. Multiply by V
2. The reference level is V
/5V for other supply values.
DD
. The following formula converts dB to mV
TH
mV = V
RMS
10
(dB/20)
×
RMS
TH
.
3. Observing pins 13, 14, or 15 (DW/J package) will cause a frequency shift due to additional loading. If tuning center
frequency by observing oscillator, design in a buffer amplifier between pin 15 and probe/calibration point and tune with
no input signal. Otherwise, tune by observing detect output band edges while sweeping input signal. VCO center
frequency is 6(f