NPN Silicon Surface Mount Transistor
with Monolithic Bias Resistor Network
This new series of digital transistors is designed to replace a single
device and its external resistor bias network. The BRT (Bias Resistor
Transistor) contains a single transistor with a monolithic bias network
consisting of two resistors; a series base resistor and a base--emitter
resistor. The BRT eliminates these individual components by
integrating them into a single device. The use of a BRT can reduce
both system cost and board space. The device is housed in the
SC--70/SOT--323 package which is designed for low power
surface mount applications.
Features
Simplifies Circuit Design
Reduces Board Space
Reduces Component Count
The SC--70/SOT--323 package can be soldered using wave or reflow.
The modified gull--winged leads absorb thermal stress during
soldering eliminating the possibility of damage to the die.
Available in 8 mm embossed tape and reel. Use the Device Number
to order the 7 inch/3000 unit reel.
These Devices are Pb--Free, Halogen Free/BFR Free and are RoHS
Compliant
PIN 1
BASE
(INPUT)
1
http://onsemi.com
NPN SILICON
BIAS RESISTOR
TRANSISTORS
R
1
R
2
3
2
SC--70/SOT--323
CASE 419
STYLE 3
PIN 3
COLLECTOR
(OUTPUT)
PIN 2
EMITTER
(GROUND)
MAXIMUM RATINGS (T
Rating
Collector--Base VoltageV
Collector--Emitter VoltageV
Collector CurrentI
=25C unless otherwise noted)
A
SymbolValueUnit
CBO
CEO
C
50Vdc
50Vdc
100mAdc
THERMAL CHARACTERISTICS
CharacteristicSymbolMaxUnit
Total Device Dissipation
Derate above 25C
Thermal Resistance, Junction--to--Ambient
Thermal Resistance, Junction--to--Lead
Junction and Storage Temperature
Range
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. FR--4 @ Minimum Pad.
2. FR--4 @ 1.0 x 1.0 inch Pad.
T
A
=25C
P
R
θ
R
θ
TJ,T
202 (Note 1)
D
310 (Note 2)
1.6 (Note 1)
2.5 (Note 2)
618 (Note 1)
JA
403 (Note 2)
280 (Note 1)
JL
332 (Note 2)
-- 55 to +150C
stg
mW
mW/C
C/W
C/W
MARKING DIAGRAM
8x M G
G
8x = Device Code
M= Date Code*
G= Pb--Free Package
(Note: Microdot may be in either location)
*Date Code orientation may vary depending
upon manufacturing location.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
DEVICE MARKING INFORMATION
See specific marking information in the device marking table
on page 2 of this data sheet.
Semiconductor Components Industries, LLC, 2010
October, 2010 -- Rev. 9
1Publication Order Number:
MUN5211T1/D
Page 2
MUN5211T1G Series
DEVICE MARKING AND RESISTOR VALUES
DevicePackageMarkingR1 (K)R2 (K)Shipping
MUN5211T1GSC--70/SOT--323
(Pb--Free)
MUN5212T1GSC--70/SOT--323
(Pb--Free)
MUN5213T1GSC--70/SOT--323
(Pb--Free)
MUN5214T1GSC--70/SOT--323
(Pb--Free)
MUN5215T1GSC--70/SOT--323
(Pb--Free)
MUN5216T1G (Note 3)SC--70/SOT--323
(Pb--Free)
MUN5230T1GSC--70/SOT--323
(Pb--Free)
MUN5231T1G (Note 3)SC--70/SOT--323
(Pb--Free)
MUN5232T1GSC--70/SOT--323
(Pb--Free)
MUN5233T1GSC--70/SOT--323
(Pb--Free)
MUN5234T1G (Note 3)SC--70/SOT--323
(Pb--Free)
MUN5235T1GSC--70/SOT--323
(Pb--Free)
MUN5236T1G (Note 3)SC--70/SOT--323
(Pb--Free)
MUN5237T1G (Note 3)SC--70/SOT--323
(Pb--Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
3. New devices. Updated curves to follow in s ubsequent data sheets.
*For additional information on our Pb--Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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