Datasheet MU9C8148-FC, MU9C8148-TCC Datasheet (MUSIC)

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MUSIC

SEMICONDUCTORS

DATA SHEET DRAFT

DISTINCTIVE CHARACTERISTICS

• Supports High-speed Source Routing or Source Routing Transparent Bridging for up to eight ports

• Glue-free operation with the MUSIC MU9C1480 LANCAM and Texas Instruments’ Token Ring chip set

• Configurable for either Motorola or Intel processor addressing modes

• Complies with the IEEE standards for 4 and 16 Mb/s Token Ring

• Contains a 128-entry Instruction Buffer that holds up to seven down-loadable filtering and purging routines, which can be automatically or directly invoked

GENERAL DESCRIPTION

The MU9C8148 is a Source Routing Transparent (SRT) Interface for the MUSIC Semiconductors MU9C1480 LANCAM for use in Token Ring LAN Bridges and Brouters. This interface operates in accordance with IEEE standards while supporting address filtering rates up to 150,000 frames/sec for minimum-length frames.

The MU9C8148 has four interfaces to provide glue-free address filtering. The Transceiver interface monitors receive data from the Transceiver to the MAC, and determines whether to filter according to Source Routing or Transparent Bridging standards. The MAC interface supplies Match, Fail, and Flush signals to instruct the Token Ring controller to reject or copy a frame. The LANCAM interface controls the companion LANCAM(s) for Transparent filtering. The Host Processor interface allows for direct initialization of the MU9C8148, and downloading of the filtering and purging routines, to offload the communication processor.

MU9C8148

SRT Interface

• Automatically selects Source Routed or Transparent filtering routines based on Transceiver output data, and supplies the proper Match, Fail, or Flush signals to the MAC chips

• Built-in arbitration allows two MU9C8148s to share a central LANCAM database

• Selectable filtering options for each frame type

• Frame validity is checked on all Routing Information Fields

• Manufactured in CMOS technology

• Available in 68-pin PLCC package and 80-pin TQFP package

The MU9C8148 can choose to copy or reject a frame depending on the frame type (MAC, LLC, or reserved), and can perform multiple validity checks on the Routing Information Field (RIF), including general checks on every Routing Control Field (RCF), as well as multiple frame related checks.

The Instruction Buffer can be loaded with up to 128 instructions at initialization for the LANCAM routines such as matching, learning, aging, purging, and data buffering operations. Internal arbitration controls access to the LANCAM. Separate arbitration pins allow two MU9C8148s to easily form a dual-port Bridge by sharing a central LANCAM-based station list.

With seven Ring-Bridge-Ring number combinations stored internally, the MU9C8148 can also operate as a source routing accelerator in multi-port Token Ring Bridge/Brouter environments.

BLOCK DIAGRAM

/RDY RXD RXC XMATCH XFAIL, /FLUSH

TRANSCEIVER

INTERFACE

/CM

/EC

/MI

LANCAM INTERFACE

/FI

DQ15-DQ0

LANCAM, the MUSIC logo, and the phrase “MUSIC Semiconductors” are registered trademarks of MUSIC Semiconductors. MUSIC is a trademark of MUSIC Semiconductors. This device takes advantage of features in the LANCAM patented under U.S. Patent 5,383,146.

TRANSPARENT

BRIDGING BLOCK

SOURCE ROUTING

BLOCK

INSTRUCTION

BUFFER

ARBITER

/RQ /RQI

MAC

INTERFACE

HOST PROCESSOR

/INTEL

/INT

A4-A0 D15-D0 ALE, SRNW /CS /RS, /LDS /WS, /UDS /HBRDY /HBEN /HBDIR /RESET

/FULL, /EMPTY

15 April 1997 Rev. 5.5 Draft

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MU9C8148

PINOUT DIAGRAMS

DQ5

DQ4

D10

GND

D11

39 38

D12 D13

D14

D15

35 34

/HBRDY /HBEN

/HBDIR

/RQ

31 30

/RQI XFAIL,/FLUSH

XMATCH

/RDY

27 26

RXD RXC

VCC

23 22

NC GND

2019181716151413121110987654321

DQ1

DQ2

DQ0

DQ3

/INT

/FULL,/EMPTY

/INTEL

/RESET

GND VCC

/WS,/UDS

/CS

VCC

GND

ALE,SRNW

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

62 63

A4 A3

66 67

69 70

/EC

/CM

74 75

/FI

/MI

77 78

79 80

/RS,/LDS

DQ14

DQ15

MU9C8148

80-pin TQFP

DQ11

DQ12

DQ13

DQ10

DQ9

DQ8

DQ7

DQ6

PIN DESCRIPTIONS

(/X indicates an active LOW function)

LANCAM Interface:

DQ15–DQ0 (Data Bus, Input/Output, TTL)

The DQ15–DQ0 lines transfer data, commands and status between the MU9C8148 and the LANCAM. The direction and nature of the information that flows between the devices is determined by the states of /CM and /W.

/E (Chip Enable, Output, Three-state TTL)

The /E output enables the LANCAM while LOW and registers /W, /CM, /EC and DQ15–DQ0 (if /W is LOW) on the falling edge of /E. If /W is HIGH, data on DQ15–DQ0 from the LANCAM is valid on the rising edge of /E.

/W (Write Enable, Output, Three-state TTL)

The /W output selects the direction of data flow during a LANCAM cycle. DQ15–DQ0 write to the LANCAM if /W is LOW at the falling edge of /E. Read data is output from the LANCAM to DQ15–DQ0 on the rising edge of /E if /W is HIGH at the falling edge of /E.

/CM (Data/Command Select, Output, Three-state

TTL)

The /CM signal determines whether DQ15–DQ0 contain LANCAM data or commands. /CM is LOW at the falling edge of /E for Command cycles and HIGH for Data cycles.

XFAIL,/ FLUSH

/HBDIR

/RQ

/RESET

/EC

/RQI

/CM

/FI

XMATCH

/RDY

/MI

RXD

293031

RXC

GND

VCC VCC

GND

DQ0

DQ1

DQ2

DQ3

22 21

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

D10

/WS, /UDS

/RS, /LDS

/CS

ALE, SRNW

GND VCC

/HBRDY

D13

D14

/HBEN

D15

373635

MU9C8148

68-pin PLCC

/INT

/INTEL

/FULL, /EMPTY

GND

D11

D12

424140

44 45

55 56

57 58

59 60

626364

/EC (Enable Comparison, Output, Three-state TTL)

The /EC signal enables the LANCAM /MF pin to output the results of a comparison. If /EC is LOW at the falling edge of /E for a given cycle, the LANCAM /MF output is enabled on the rising edge of /E. If /EC is HIGH, the LANCAM /MF output is held HIGH.

/MI (Match Flag, Input, TTL)

The LANCAM /MF pin takes the MU9C8148's /MI input LOW if a valid match occurs during a Comparison cycle, and /EC was also LOW at the start of that cycle. The state of the /MI pin controls branching in the MU9C8148's routines.

/FI (Full Flag, Input, TTL)

The /FI input will be driven LOW by the LANCAM /FF output pin if all the LANCAM memory locations have valid contents. The status of the /FI pin can be read by the Host processor from the MU9C8148's Control register.

Transceiver Interface:

RXD (Receive Data, Input, TTL)

The RXD pin monitors the data received by the TMS38053/4 from the Token Ring. RXD is clocked on the rising edge of RXC.

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PIN DESCRIPTIONS (CONT’D)

RXC (Receive Clock, Input, TTL)

The rising edge of RXC clocks the RXD data received by the TMS38053/4 from the Token Ring. The RXC clock is also used to generate the control signals to the LANCAM, and controls the internal operation of the MU9C8148.

/RDY (Ring Interface Ready, Input, TTL)

The /RDY pin is taken LOW by the TMS38053/4 to indicate the presence of received data. /RDY must be HIGH if the RXD data is not valid.

MAC Interface:

XMATCH (Match, Output, Three-state TTL)

XMATCH goes HIGH in combination with XFAIL going LOW to indicate that the frame currently being received should be copied. If XFAIL is HIGH, XMATCH is forced LOW.

XFAIL, /FLUSH (FAIL/FLUSH, Output,

Three-state TTL)

The function of this pin is defined by the Control register. If the MU9C8148 is connected to a TMS380CX6, this pin is defined as XFAIL, which goes HIGH when XMATCH goes LOW, to tell the TMS380CX6 to discard the frame and flush the receive buffer.

Host Processor Interface:

ALE, SRNW (Address Latch Enable/System Read

Not Write, Input, TTL)

This pin is ALE when the MU9C8148 is used in the Intel mode. The falling edge of ALE latches the address on the address lines. If the MU9C8148 is in the Motorola mode, this pin becomes SRNW, and is HIGH for a Host Processor Read cycle and LOW for a Write cycle.

/CS (Chip Select, Input, TTL)

/CS going LOW enables the Host Processor interface of the MU9C8148 for a Host Processor read or write. When /CS is HIGH, /HBRDY goes three-state and the Host Processor interface is disabled.

A4–A0 (Address, Input, TTL)

The Address pins select the internal register for Host processor reads and writes. In the Intel mode, the Address pins are latched by the falling edge of ALE. In the Motorola mode, the Address pins must remain stable until the rising edge of /LD and /UDS, as shown in the Timing diagrams.

MU9C8148

D15–D0 (Data, Common I/O, TTL)

The Data pins transfer data between the Host Processor and the internal registers of the MU9C8148. The data pins are registered on the falling edge of /HBRDY in the Write mode, and are valid on the falling edge of /HBRDY in the Read mode, as shown in the Timing diagrams.

/RS, /LDS (Read Strobe/Lower Data Strobe,

Input, TTL)

In the Intel mode, this pin is /RS and is taken LOW to begin a read cycle to the Host Processor interface. Data on D(15-0) is valid when /HBRDY goes LOW. In the Motorola mode, this pin is /LDS for Host processor read and write cycles. The falling edge of /LDS or /UDS begins the cycle; data is strobed when /HBRDY goes LOW for a Write cycle, and is valid on D(15-0) when /HBRDY goes LOW for a Read cycle.

/WS, /UDS (Write Strobe/Upper Data Strobe,

Input, TTL)

In the Intel mode, this pin is /WS, and is taken LOW to begin a write cycle from the Host Processor interface. Data on D(15-0) is strobed into the MU9C8148 when /HBRDY goes LOW. In the Motorola mode, this pin is /UDS for Host processor read and write cycles. The falling edge of /LDS or /UDS begins the Write cycle; data is strobed when /HBRDY goes LOW for a Write cycle, and is valid on D(15-0) when /HBRDY goes LOW for a Read cycle.

/HBRDY (Ready, Output, Three-state TTL)

/HBRDY goes LOW to indicate to the Host processor that a data transfer is completed for a Write cycle or that data is valid for a Read cycle. After the Host processor takes /RS, /WS, or /LDS and /UDS HIGH, the MU9C8148 takes /HBRDY HIGH. /HBRDY becomes three-state one RXC period after it goes HIGH, or when /CS goes HIGH.

/HBEN (Data Buffer Enable, Output, TTL)

/HBEN goes LOW to enable external bi-directional buffers, if are needed on the D15–D0 lines. /HBEN goes HIGH to disable the external buffers.

/HBDIR (Data Buffer Direction, Output, TTL)

/HBDIR controls the direction of data flow in external bi-directional buffers. /HBDIR goes LOW to enable data flowing to the MU9C8148 and HIGH to enable data coming from the MU9C8148 registers.

/INT (Interrupt, Output, Open Drain)

This pin goes LOW to notify the Host processor that the MU9C8148 is running an Instruction Buffer routine, therefore accessing the LANCAM. /INT will remain LOW as long the routine is running.

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MU9C8148

PIN DESCRIPTIONS (CONT’D)

Arbitration Signals between two MU9C8148s:

/RQ (Request, Output, TTL)

The /RQ pin is used to arbitrate access to a shared LANCAM, and goes LOW when access is required to the LANCAM. /RQ of one MU9C8148 is connected to /RQI on the other MU9C8148 to provide notification that a LANCAM access is pending. One MU9C8148 is configured as Master, and the other as Slave, to resolve conflicts. /RQ goes HIGH after the LANCAM interface transactions are completed.

/RQI (Request Indication, Input, TTL)

If /RQI goes LOW, another MU9C8148 has a request pending for access to the LANCAM. The LANCAM interface on this chip is then disabled, and execution of routines is posponed until /RQI goes HIGH. This pin must be tied HIGH if it is not used.

are 0000H after a Hardware reset (except for register 04H), all three-state pins are High-Z, and all TTL output pins will be HIGH.

/FULL, /EMPTY (Full/Empty, Output, Open Drain)

If part of the Instruction buffer in the MU9C8148 is configured as a FIFO, this active-LOW pin can be configured to signal whether the FIFO is full (all entries contain valid data) or empty (no entry contains data). The definition of this signal is programmed in the FIFO Control register.

/INTEL (HPI Selection, Input, TTL)

The /INTEL pin identifies which type of microcontroller is connected to the Host Processor interface. This pin is set LOW for Intel-type addressing modes and HIGH for Motorola-type addressing modes.

Miscellaneous:

/RESET (Hardware Reset, Input, TTL)

Taking /RESET LOW for at least 2 RXC cycles sets the MU9C8148 to a predefined state. The contents of all registers

128 Locations

/W, /CM, /EC, S

LANCAM

Interface

Instruction

Pointer and

Control

Arbiter

Start

Address

VCC, GND (Positive Power Supply and Ground)

These pins are the main power supply connections to the MU9C8148. VCC must be held at +5V ± 10% relative to the GND pin, which is at 0V (system reference potential), for correct operation of the device.

D15 - D0

Address

Pointer

FIFO

Control

FIFO

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TB block

Start Address Register

Control

Figure 1: The Instruction Buffer

FIFO

Control

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FUNCTIONAL DESCRIPTION

Referring to the Block diagram shown on Page 1, the MU9C8148 consists of four functional blocks: the Transparent Bridging (TB) block, the Source Routing Block (SRB), the Instruction Buffer (IB), and the Arbiter. Four interfaces connect the MU9C8148 to the Transceiver, the MAC controller, the Host processor, and the LANCAM. For a detailed description of Token Ring frames, refer to IEEE Standard 802.5, or the IBM Token-Ring Network Architecture Reference.

Transparent Bridging Block

If a frame does not contain an RIF, the TB block makes decisions whether to copy or discard a frame based on the Destination address (DA). If the bridge is set for Transparent bridging only (the TBO bit in the Control register is HIGH, disabling the SRB), the TB block also makes copy or discard decisions for frames which do contain an RIF. The TB block parses the data as received from the Transceiver off the Token Ring network, and indicates to the MAC whether to assert the XMATCH and/or XFAIL (/FLUSH) signals. For each frame, the TB block examines the Token bit, the Frame Type bits, the Destination address (DA), and the Source address (SA), which contains the Routing Information indicator (RII).

The Token bit signals whether the current frame is a Token or a regular frame. If the Token bit is LOW, a Token frame is being received, and the TB block discards the frame. For a regular frame, the Frame Type bits signify the type of frame (LLC, MAC, or Reserved) being received, and the TB block decides to copy or discard the frame, based on the settings in the Frame Type Selection register and the results of filtering on the Destination address (DA).

Positive or negative filtering on the DA can be done for frames without an RIF, or for all frames when the bridge is set for Transparent bridging only, based on the setting of the PONNE bit in the Transparent Bridging register. Positive filtering implies that a frame should be forwarded if its DA is found in the LANCAM address database. Routine 0 in the instruction buffer examines the DA field to determine whether a frame should be copied or not. The results of this comparison are used to notify the LAN controller to copy or discard the frame. Negative filtering implies that a frame should be forwarded if its DA is not found in the address database. In this case, the MU9C8148 checks the DA before routine 0 is started to differentiate between MAC, Broadcast, Functional and Group addresses. Based upon the settings of the Transparent Bridging register, the TB block discards a frame whose DA is a Broadcast, Functional and/or Group address before Routine 0 is started.

If the MU9C8148 is not used in a Transparent Bridging Only mode and a frame containing an RIF is received, Routine 2 in the Instruction buffer can be started. The results of this comparison are combined with the output of the SRB to instruct the LAN controller to copy or discard the frame. Routine 2 can only perform positive filtering.

The Source address (SA) of a frame can be used to update the database of addresses stored in the LANCAM. Routine 1 in the Instruction buffer checks the SA of a frame against all the entries in the database, and if the SA is not found, the address is new, and if the frame received is error free, the address can be learned by adding it to the LANCAM database. Learning can

MU9C8148

be enabled on the four different frame types (MAC, LLC and two types of reserved frames) individually. For each frame type, a choice between two different learning routines can be made in the Transparent Bridging register. Note that learning can only take place when the RII bit of the frame is ZERO, or for every frame when the TBO bit is HIGH. Thus, Routine 0 or Routine 2 is started after the RII bit is received and evaluated. Routine 1 is started by the TB block after the Frame Status field has been received and the frame found to be error-free.

Source Routing Block

The Source Routing Block (SRB) only decides to copy or discard a frame if it contains an RIF, and the MU9C8148 is not in TBO mode. The SRB (in combination with the results of Routine 2 of the TB) notifies the MAC interface how to assert its output flags .

When a frame is received, the SRB checks whether the Token bit in the AC field is LOW, in which case a Token frame is being received and no further processing is necessary. If the Token bit is HIGH, a regular frame is being received and the SRB examines the Frame Type bits in the FC field, which give the type of frame being received. The frame types to be processed by the SRB (those with an RIF) are selectable in the Frame Type Selection register. If the RII bit is HIGH, the SRB signals the MAC interface, based on the frame type and the settings in the Frame Type Selection register, either to discard the frame and flush the buffer, or to continue to check the RIF of the frame, or to accept the frame. If the RII is LOW, the SRB is not allowed to process the frame any further and waits for the next frame to arrive.

If a copy/discard decision is to be made based on the RIF, the SRB examines the information contained in the RCF. If the length (LTH) bits of the RCF indicate a length equal to zero, or contain an odd length, or if the length of the RIF is longer than the allowed length stored in the RIF Length register, reception of the frame is stopped, and the SRB indicates that the frame is to be discarded. The D bit of the Routing Control Field (RCF) indicates which direction the Routing Descriptors (RDs) of the RIF should be interpreted.

The SRB provides for seven Ring(in)–Bridge–Ring(out) combinations (LIN-BN-LOUT) stored in the Source Ring Number register and Bridge/Destination Ring Number registers. LIN is the LAN ID of the ring connected to that specific port, while the BN(s) and LOUT(s) depend on the topology of the network and the bridge design. The SRB provides for checks between the LAN ring numbers and bridge numbers contained in every RD with every LIN-BN-LOUT stored, allowing the user to develop an SR(T) bridge with an internal virtual ring, or a bridge with a Full Mesh design (IEEE P802.5M).

If the Routing Type (RT) bits are equal to 0XXB, a Specifically-Routed Frame (SRF) is being received, and should be forwarded on the conditions shown in Table 1. If the RT bits are equal to 10XB, the frame is an All Routes Explorer (ARE) frame, and should be handled as shown in Table 1. If the RT bits are equal to 11XB, the frame is a Spanning Tree Explorer (STE) frame, and should be dealt with as shown in Table 1 Also described in Table 1 are the conditions on which the Error counters (Register 17H) are incremented.

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MU9C8148

FUNCTIONAL DESCRIPTION (CONT’D)

Condition ActionType

A prestored LIN-BN-LOUT combination is found in the RIF & that LOUT has occurred only once in the RIF.

A prestored LIN-BN-LOUT combination is found in the RIF & that LOUT has occurred more than one time in the RIF.

No prestored LIN-BN-LOUT combination is found in the RIF.

Frame

#RDs ≥ SRFRD

Specifically Routed

Prestored LIN is found more than once in the RIF. LTH = 2 Last LOUT in RIF ≠ LIN, LTH ≠ 2

#RDS ≥ ARERD

Not all prestored LOUTs in RIF #RDS < ARERD

All Routes Explorer Frame

All prestored LOUTs in RIF, LTH ≠ 2 LTH = 2 Last LOUT in RIF ≠ LIN, LTH ≠ 2

Copy frame. Signal MAC Interface.

Discard frame. Signal MAC Interface. Increment DUPLOUT counter.

Discard frame. Signal MAC Interface. Discard frame. Signal MAC Interface. Discard frame. Signal MAC interface. Copy frame. Signal MAC Interface. Discard frame. Signal MAC Interface.

Increment LANIDMISMATCH counter.

Discard frame. Signal MAC Interface. Increment ARERDLIMITEXCEEDED counter.

Copy frame. Signal MAC Interface.

Discard frame. Signal MAC Interface. . Copy frame. Signal MAC Interface.

Discard frame, Signal MAC Interface. Increment LANIDMISMATCH counter.

#RDS ≥ STERD

Not all prestored LOUTs in RIF #RDS < STERD

All prestored LOUTs in RIF, LTH ≠ 2

Spanning Tree Explorer Frames

Bit DISSTE = ONE

Note: Signalling takes place at the end of the RIF. Discard actions overrule copy actions. The result of the SRB is

OR’ed with the result of Routine 2, whereby the copy action overrules.

Discard frame. Signal MAC Interface. Increment STERDLIMITEXCEEDED counter.

Copy frame. Signal MAC Interface.

Discard frame. Signal MAC Interface. Increment DUPLANIDORTREEERROR counter.

Discard frame. Signal MAC Interface.

Table 1: Source Routing Forwarding Conditions

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FUNCTIONAL DESCRIPTION (CONT’D)

Instruction Buffer

The Instruction buffer (IB) shown in Figure 1 consists of the following: the 128-entry Instruction storage, the Instruction pointer (IP), the Address pointer, the Start address registers, the FIFO, and FIFO control registers.

The Instruction Storage (IS) can store up to seven down-loaded routines which contain instructions for the LANCAM to execute, plus room for data storage. The IS location accessed by the Host processor port is controlled by an auto-incrementing Address pointer, which is part of the Control register. Each instruction is a 16-bit LANCAM op-code or data word along with 3 bits that indicate the level of /W, /CM, /EC during the instruction. An additional S-bit is used to indicate whether this entry is a LANCAM instruction or a MU9C8148 instruction.

The Instruction pointer (IP) points to the instruction currently executing. At the start of a routine the IP is loaded with the appropriate Start address. The IP can also be loaded from Branch Routine addresses or addresses contained in an instruction itself. For example, when a “Wait for a match” instruction is executed and no match has occurred, the IP is loaded with the address of the next instruction to execute.

The Start Address registers contain the start addresses of all seven routines. When a routine is started, this address is copied into the IP and execution is started. In addition to the regular start addresses, two Branch Routine addresses are available in the IB Start I register and are selected based on the received frame type, as enabled in the Transparent Bridging register. If a “Wait for match then execute at Branch Routine address selected” instruction is executed and no match occurs, the IP is loaded with the Branch Routine address selected by the current frame type and execution continues.

Part of the IS may be used as a FIFO for data storage. Data from the routines can be moved either to or from the Host Processor interface through the FIFO. While routines are loaded into the IS from 00H up towards 7FH, the FIFO goes from 7FH down to the limit set in the FIFO control register. The functionallity of the /FULL or /EMPTY flag is programmed in the FIFO Control register to prevent FIFO overflow or underflow situations.

Programming and Execution of Routines

The IS is loaded and read through the IB register in two 16-bit cycles. The first 16-bit cycle moves the data on the D15–D0 lines of the Host Processor interface into the data field of the location in the IB indicated by the Address pointer in the Control register, or vice-versa in case of a read from the IB register. The second 16-bit word is written to or read from the /W, /CM, /EC, and /S bits of that same location.

The Control register contains an Address pointer that selects the accessed location in the IS. The Address pointer can be read out or overwritten. It is incremented when the Host processor has completed the two write or read cycles to one location of the IB.

Routines in the instruction buffer can be started either by the Host processor (Routines 3–6 only) or the Transparent Bridging block. If a routine is started by the Host processor, it can be

MU9C8148

either started directly, or after an RII has been received, or after the second C bit of the Frame Status field has been received. If the STDIR bit of a specific routine is set HIGH, the routine is started immediately. If the START bit of a specific routine is set to HIGH, the routine is started directly after an RII has been received (SA/DA is HIGH) or after the second C bit has been received (SA/DA is LOW). After execution has finished, the START and STDIR bits are set LOW. If the AUTOSTART bit for Routines 3, 4, 5 or 6 is set HIGH in the IB Start II register, that routine is started for every frame received directly after an RII has been received (when SA/DA is HIGH), or after the second C bit has been received (when SA/DA is LOW). If more than one routine should be started at the same time, the routine with the numerically lowest start address is started first.

The TB block starts Routine 0, 1 or 2 when the enable bit of that routine is set HIGH. Routines 0 and 2, used for DA comparison, are started directly after the RII while Routine 1, used for SA comparison, is started after the last C bit of the FS field has been received, and if the frame was error-free.

Arbiter

The Arbiter block has two primary tasks: 1) Arbitration between the execution of different routines stored in the Instruction Buffer; and, 2) Arbitration between two MU9C8148's when they are sharing the same LANCAM.

Routine Priorities

Of the seven routines stored in the Instruction buffer, execution of Routines 0–2 is time critical because there is a direct relation to the incoming data stream of the Token Ring; therefore, they have the highest priority and cannot be interrupted by other routines. The time length of Routines 0 or 2 plus Routine 1 must fit in the time interval of a minimum length frame. Routines 3–6 have a lower priority and they can be interrupted by routines having a lower number.

During execution of Routine 0–2, no lower priority routine can be started. When a second routine is programmed to be started and execution of the first routine has ended, this second routine is started immediately afterward. A currently running routine can be interrupted by a higher priority routine, and the lower priority routine will re-start from the beginning immediately after the interrupting routine is finished.

Host Processor Access

The Address bus, A(4-0), is used to select the Registers, Instruction Buffer, or LANCAM for access from the Host processor port. Direct access to the LANCAM through registers 18H to 1FH should only be used for LANCAM initialization and should be completed prior to enabling IB routines. After that, new addresses written to the LANCAM by the host processor should be first stored in the IB, and a routine started that transfers it to the LANCAM. Access to the IB is arbitrated if network activity triggers a pre-stored routine. The /INT pin goes LOW (the INT bit in the Control register goes HIGH) to notify the host processor that a routine is running. (If an access to the IB is attempted while /INT is LOW, the return of /HBRDY is delayed slightly until the routine instruction currently executing is completed.) /INT will stay LOW until all routines have completed. The processor can then re-issue its request.

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MU9C8148

FUNCTIONAL DESCRIPTION (CONT’D)

For a non-arbitrated Write cycle, /HBEN and /HBDIR go LOW after the second rising edge of RXC past the falling edge of /WS (Intel mode) or /UDS and /LDS (Motorola mode). /HBRDY goes LOW after the second rising edge of RXC past the falling edge of /HBEN for Register and Instruction Buffer write cycles, and after the 8th rising edge of RXC past the falling edge of /HBEN for CAM write cycles. The write data on the D(15-0) bus is strobed by the rising edge of RXC that outputs /HBRDY.

For a non-arbitrated Read cycle, /HBEN goes LOW after the third rising edge of RXC past the falling edge of /RS (Intel mode) or /UDS and /LDS (Motorola mode). /HBRDY goes LOW after the first rising edge of RXC past the falling edge of /HBEN for a Register read cycle, the 4th rising edge of RXC past the falling edge of /HBEN for an Instruction Buffer read cycle, and the 7th rising edge of RXC past the falling edge of /HBEN for a CAM read cycle. Read data is output to the D(15-0) bus immediately prior to /HBRDY going LOW.

For both non-arbitrated Write and Read cycles, /HBRDY goes HIGH after the first rising edge of RXC past the rising edge of /WS or /RS in Intel mode or /UDS, /LDS in Motorola mode. /HBEN and /HBDIR return HIGH and /HBRDY will go three-state after the next rising edge of RXC.

On a FIFO write, /HBRDY goes LOW after the fifth rising edge of RXC past the falling edge of /HBEN. On a FIFO read, /HBRDY goes LOW after the fourth rising edge of RXC past the falling edge of /HBEN.

MAC Interface

The TB block and/or the SRB notify the MAC interface to copy or reject a frame through the XMATCH and the XFAIL pins for the TMS380CX6, or the /FLUSH pin for the 82C581, using the TEXAS bit in the Control register to select the operating mode. When Routine 2 is enabled, the results from the TB and the SRB are combined.

Transceiver Interface

The MU9C8148 connects to the received data bus between the TMS38053/4 and the TMS380CX6. The differential Manchester

encoded data received from the Token Ring transceiver is input to the RXD pin which clocked by the RXC clock. The /RDY signal indicates the presence of received data on the RXD pin. The Transceiver interface notifies the TB block and the SRB that it has detected a JK Start delimiter in the incoming data stream and to begin parsing the other fields of the frame. The Transceiver interface performs a number of error checks: whether the data contained any control characters before an ED was received; that no second SD is received before an ED is received; and, /RDY is still asserted. In any of these cases, both the TB and SRB are notified and reception of data is cancelled. Also checked are: the correctness of the FCS, the value of the E bit in the ED, and the values of both C bits and both A bits in the FS field. If there is an error situation detected in one of these items, the TB is notified not to start Routine 1.

Host Processor Interface

The Host Processor interface is configured for Intel or Motorola addressing modes using the /INTEL pin. In both modes the MU9C8148 is a slave on the processor bus and can be programmed using the registers described in this document. The MU9C8148 provides /HBEN and /HBDIR to enable the user to add external bi-directional buffers in the D15-D0 datalines. In Intel mode, ALE is used to latch the address lines. In Motorola mode, both /UDS and /LDS are used to load the upper and lower bytes to all of the registers including the Instruction buffer and FIFO.

Two MU9C8148s Sharing One LANCAM

Two MU9C8148s may share the same LANCAM string if they are operating at the same frequency, using /RQ and /RQI to arbitrate the LANCAM access by setting the ASSRQ bit in the Control register to HIGH. One MU9C8148 is set to be Master, and given Routines 0–2, and the other is set to be Slave and given the non-time-critical Routines 3–6 in addition to Routines 0–2. Routines 3–6 running on the Slave can be interrupted immediately by time-critical routines running on either the Master or Slave, but if both MU9C8148s try to run a high priority routine at the same time, the Master device will be given priority, and the Slave device will start its routine after the Master has finished.

INSTRUCTION SET DESCRIPTION

Instruction: LANCAM Instruction Binary Op Code: iiii iiii iiii iiii wce0

i Instruction Code (see The LANCAM Handbook) w The state of /W c The state of /CM e The state of /EC

This instruction transfers data or commands to or from the LANCAM. Instructions from the LANCAM instruction set are described in the LANCAM Handbook. The state of the control outputs /W, /CM and /EC at the falling edge of /E for this cycle are defined by w,c, and e.

Instruction: Stop Execution Binary Op Code: 0000 0000 0000 0000 xxx1

x Don't Care

Rev. 5.5 Draft

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The “Stop Execution” instruction stops the execution of the routine currently running. Control is transferred to the arbiter.

Instruction: Wait for match for yyyyB + 4 cycles, if no

match then execute at Branch Routine Address selected.

Binary Op Code: 0001 yyyy rrrr rrrr xxx1

y Wait period r Reserved (set LOW)

x Don't Care

This instruction waits for a maximum period of yyyyB + 4 clock cycles for the /MI input to become active, asserting XMATCH and XFAIL as appropriate. If no match condition occurs during that period, a branch is executed to the address stored in the Branch Routine address determined by the frame type. If a match condition is detected, execution proceeds to the instruction at the next address.

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INSTRUCTION SET DESCRIPTION (CONT’D)

Instruction: Wait for match for yyyyB + 4 cycles, if no

match then execute at address aaaaaaaB.

Binary Op Code: 0010 yyyy raaa aaaa xxx1

y Wait period r Reserved (set LOW) a Address x Don't Care

This instruction waits for a maximum period of yyyyB + 4 clock cycles for the /MI input to become active, asserting XMATCH and XFAIL as appropriate. If no match condition occurs during that period, a branch is executed to the address which is stored in the “a” bits of the instruction. If a match condition is detected, execution proceeds to the instruction in the next address.

Instruction: Move DA part 0 to DQ15–DQ0. Binary Op Code: 0011 0000 0000 0000 0ce1