Datasheet MTV018N, MTV018N20, MTV018N24 Datasheet (MYSON)

Page 1

This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of the product.

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FEATURES GENERAL DESCRIPTION

BLOCK DIAGRAM

• Horizontal sync input may be up to 120 KHz.

• On-chip PLL circuitry up to 96 MHz.

• Programmable horizontal resolutions up to 1524 dots per display row.

• 942 bytes display registers to control full screen display.

• Full screen display consists of 15 (rows) by 30 (columns) characters.

• 12 x 18 dot matrix per character.

• Total 256 characters and graphic fonts including 248 mask ROM fonts and 8 programmable RAM fonts.

• 8 color selectable maximum per display character.

• Double character height and/or width control.

• Programmable positioning for display screen center.

• Bordering, shadowing and blinking effect.

• Programmable vertical character height (18 to 71 lines) control.

• Row to row spacing register to manipulate the constant display height.

• 4 programmable background windows with multi-level operation

• Software clears for display frame.

• Polarity selectable to Hsync and Vsync inputs.

• Auto detection for input edge bounce distortion between Hsync and Vsync inputs.

• Half tone and fast blanking output.

• Software force blank function for external display.

• 8 channels 8 bits PWM D/A converters output.

• Provide a clock output synchronous to the incoming Hsync for external PWM D/A.

• Compatible to SPI bus or I2C interface.

• I2C interface with address 7AH (Slave address is mask option).

• 16 pins, 20 pins or 24 pins PDIP package.

Super On-Screen-Display

MTV018 is designed for monitor applications to display the built-in characters or fonts onto monitor screen. The display operation is by transferring data and control information from micro controller to RAM through a serial data interface. It can execute full screen display automatically and specific functions such as character bordering, shadowing, blinking, double height and width, font by font color control, frame positioning, frame size control by character height and horizontal display resolution, and windowing effect. Moreover, MTV018 also provide 8 PWM DAC channels with 8 bits resolution and a PWM clock output for external digital to analog control.

SERIAL DATA

INTERFACE

ADDRESS BUS

ADMINISTRATOR

VERTICAL

DISPLAY

CONTROL

DISPLAY & ROW

CONTROL

REGISTERS

COLOUR

ENCODER

WINDOWS &

FRAME

CONTROL

WRWGWB

FBKGC

BLANK

LUMAR LUMAG LUMAB

BLINK

VCLKX

DATA

VERTD

HORD

8 8 7

BSEN SHADOW OSDENB HSP VSP

HORIZONTAL

DISPLAY CONTROL

PHASE LOCK LOOP

DATA

LPN

CWS

VCLKS

DATA

CWS

CHS

8 LUMAR

LUMAG LUMAB BLINK CRADDR

LUMA BORDER

ARWDB HDREN

VCLKX

HORD

CHS

VERTD

7 8

LPN NROW VDREN

RCADDR DADDR FONTADDR WINADDR PWMADDR

5 9 9 5 5

ARWDB HDREN VDREN

NROW

DATA ROW, COL ACK

8 9

CHARACTER ROM

USER FONT RAM

LUMINANCE &

BORDGER

GENERATOR

VDD

VSS

VDDA

VSSA

ROUT GOUT BOUT FBKG HTONE

HFLB

VCO

VFLB

SSB

SCK

SDA

VSP

HSP

PWM D/A

CONVERTER

PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7

DATA

POWER ON

RESET

PRB

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1.0 PIN CONNECTION

2.0 PIN DESCRIPTIONS

Name I/O

Pin No.

Descriptions

N N20 N24

VSSA - 1 1 1 Analog ground. This ground pin is used to internal analog circuitry.

VCO I/O 2 2 2 Voltage Control Oscillator. This pin is used to control the internal

oscillator frequency by DC voltage input from external low pass filter.

RP I/O 3 3 3 Bias Resistor. The bias resistor is used to regulate the appropriate

bias current for internal oscillator to resonate at specific dot frequency.

VDDA - 4 4 4 Analog power supply. Positive 5 V DC supply for internal analog cir-

cuitry. And a 0.1uF decoupling capacitor should be connected across to VDDA and VSSA.

HFLB I 5 5 5 Horizontal input. This pin is used to input the horizontal synchroniz-

ing signal. It is a leading edge triggered and has an internal pull-up resistor.

SSB I 6 6 6 Serial interface enable. It is used to enable the serial data and is

also used to select the operation of I2C or SPI bus. If this pin is left floating, I2C bus is enabled, otherwise the SPI bus is enabled.

SDA I 7 7 7 Serial data input. The external data transfer through this pin to inter-

nal display registers and control registers. It has an internal pull-up resistor.

SCK I 8 8 8 Serial clock input. The clock-input pin is used to synchronize the

data transfer. It has an internal pull-up resistor.

PWM0 O - 9 9 Open-Drain PWM D/A converter 0. The output pulse width is pro-

grammable by the register of Row 15, Column 19.

PWM1 O - 10 10 Open-Drain PWM D/A converter 1. The output pulse width is pro-

grammable by the register of Row 15, Column 20.

VSSA

VCO

VDDA

HFLB

SSB

SDA SCK

VSS ROUT GOUT BOUT FBKG HTONE/PWMCK VFLB VDD

16 15 14 13 12 11 10

1 2 3 4 5 6 7 8

MTV018N

VSSA

VCO

VDDA

HFLB

SSB SDA

SCK PWM0 PWM1 PWM2 PWM3

VSS ROUT GOUT BOUT FBKG HTONE/PWMCK VFLB VDD PWM7 PWM6 PWM5 PWM4

24 23 22 21 20 19 18 17 16 15 14 13

1 2 3 4 5 6 7 8 9 10 11 12

MTV018N24

VSSA

VCO

VDDA

HFLB

SSB SDA

SCK PWM0 PWM1

VSS ROUT GOUT BOUT FBKG HTONE/PWMCK VFLB VDD PWM7 PWM6

20 19 18 17 16 15 14 13 12 11

1 2 3 4 5 6 7 8 9 10

MTV018N20

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3.0 FUNCTIONAL DESCRIPTIONS

3.1 SERIAL DATA INTERFACE

The serial data interface receives data transmitted from an external controller. And there are 2 types of bus can be accessed through the serial data interface, one is SPI bus and other is I2C bus.

3.1.1 SPI bus

While SSB pin is pulled to "high" or "low" level, the SPI bus operation is selected. And a valid transmission should be starting from pulling SSB to "low" level, enabling MTV018 to receiving mode, and retain "low" level until the last cycle for a complete data packet transfer. The protocol is shown in Figure 1.

PWM2 O -

11 Open-Drain PWM D/A converter 2. The output pulse width is pro-

grammable by the register of Row 15, Column 21.

PWM3 O - - 12 Open-Drain PWM D/A converter 3. The output pulse width is pro-

grammable by the register of Row 15, Column 22.

PWM4 O -

13 Open-Drain PWM D/A converter 4. The output pulse width is pro-

grammable by the register of Row 15, Column 23.

PWM5 O -

14 Open-Drain PWM D/A converter 5. The output pulse width is pro-

grammable by the register of Row 15, Column 24.

PWM6 O - 11 15 Open-Drain PWM D/A converter 6. The output pulse width is pro-

grammable by the register of Row 15, Column 25.

PWM7 O - 12 16 Open-Drain PWM D/A converter 7. The output pulse width is pro-

grammable by the register of Row 15, Column 26.

VDD - 9 13 17 Digital power supply. Positive 5 V DC supply for internal digital cir-

cuitry and a 0.1uF decoupling capacitor should be connected across to VDD and VSS.

VFLB I 10 14 18 Vertical input. This pin is used to input the vertical synchronizing sig-

nal. It is leading triggered and has an internal pull-up resistor.

HTONE /

PWMCK

O 11 15 19 Half tone output / PWM clock output. This is a multiplexed pin

selected by PWMCK bit. This pin can be a PWM clock or used to attenuate R, G, B gain of VGA for the transparent windowing effect.

FBKG O 12 16 20 Fast Blanking output. It is used to cut off external R, G, B signals of

VGA while this chip is displaying characters or windows.

BOUT O 13 17 21 Blue color output. It is a blue color video signal output.

GOUT O 14

22 Green color output. It is a green color video signal output.

ROUT O 15 19 23 Red color output. It is a red color video signal output.

VSS - 16 20 24 Digital ground. This ground pin is used to internal digital circuitry.

Name I/O

Pin No.

Descriptions

N N20 N24

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There are three transmission formats shown as below: Format (a) R - C - D → R - C - D → R - C - D Format (b) R - C - D → C - D → C - D → C - D Format (c) R - C - D → D → D → D → D → D Where R=Row address, C=Column address, D=Display data

3.1.2 I2C bus

I2C bus operation is only selected when SSB pin is left floating. And a valid transmission should be starting from writing the slave address 7AH, which is mask option, to MTV018. The protocol is shown in Figure 2.

There are three transmission formats shown as below: Format (a) S - R - C - D → R - C - D → R - C - D Format (b) S - R - C - D → C - D → C - D → C - D Format (c) S - R - C - D → D → D → D → D → D Where S=Slave address, R=Row address, C=Column address, D=Display data

Each arbitrary length of data packet consists of 3 portions viz, Row address (R), Column address (C), and Display data (D). Format (a) is suitable for updating small amount of data which will be allocated with different row address and column address. Format (b) is recommended for updating data that has same row address but different column address. Massive data updating or full screen data change should use format (c) to increase transmission efficiency. The row and column address will be incremented automatically when the format (c) is applied. Furthermore, the undefined locations in display or fonts RAM should be filled with dummy data.

There are 3 types of data should be accessed through the serial data interface, one is ADDRESS bytes of display registers, second is ATTRIBUTE bytes of display registers and other is user fonts RAM data, the protocol are same for all except the bit6 and bit5 of row address. The MSB(b7) is used to distinguish row and column addresses when transferring data from external controller. The bit6 of row address is used to distinguish display registers and user fonts RAM data and the bit6 of column address is used to differentiate the column address for format (a), (b) and format (c) respectively. Bit5 of row address for display register is used to distinguish ADDRESS byte when it is set to "0" and ATTRIBUTE byte when it is set to "1". See Table 1.

MS B

LSB

SSB

SCK

SDA

first byte last byte

FIGURE 1. Data transmission protocol

FIGURE 2. Data transmission protocol (I2C)

SCK

SDA

first byte

¡@¡@¡@¡@

¡@

START ACK

second byte last byte

ACK STOP

B7 B6 B0 B7 B0

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The data transmission is permitted to change from format (a) to format (b) and (c), or from format (b) to format (a), but not from format (c) back to format (a) and (b). The alternation between transmission formats is configured as the state diagram shown in Figure3 on page5.

3.2 Address bus administrator

The administrator manages bus address arbitration of internal registers or user fonts RAM during external data write in. The external data write through serial data interface to registers must be synchronized by internal display timing. In addition, the administrator also provides automatic increment to address bus when external write using format (c).

3.3 Vertical display control

The vertical display control can generates different vertical display sizes for most display standards in current monitors. The vertical display size is calculated with the information of double character height bit(CHS), verti-

TABLE 1. The configuration of transmission formats.

Address b7 b6 b5 b4 b3 b2 b1 b0 Format

Address Bytes

of Display Reg.

Row 1 0 0 x R3 R2 R1 R0 a,b,c

Column

0 0 x C4 C3 C2 C1 C0 a,b

Column

0 1 x C4 C3 C2 C1 C0 c

Attribute Bytes of Display Reg.

Row 1 0 1 x R3 R2 R1 R0 a,b,c

Column

0 0 x C4 C3 C2 C1 C0 a,b

Column

0 1 x C4 C3 C2 C1 C0 c

User Fonts

RAM

Row 1 1 x x x R2 R1 R0 a,b,c

Column

0 0 C5 C4 C3 C2 C1 C0 a,b

Column

0 1 C5 C4 C3 C2 C1 C0 c

Initiate

ROW

COL

1, X

0, 1

0, 0

X, X

0, 1

1, X

format (a)

format (b)

format (c)

X, X

0, X

Input = b7, b6

0, 0

FIGURE 3. Transmission state diagram

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cal display height control register(CH6-CH0).The algorithm of repeating character line display are shown as Table 2 and Table 3. The programmable vertical size range is 270 lines to maximum 2130 lines.

The vertical display center for full screen display could be figured out according to the information of vertical starting position register (VERTD) and VFLB input. The vertical delay starting from the leading edge of VFLB, is calculated with the following equation:

Vertical delay time = ( VERTD * 4 + 1 ) * H Where H = one horizontal line display time

Note:" v " means the nth line in the character would be repeated once, while " - " means the nth line in the

character would not be repeated.

3.4 Horizontal display control

The horizontal display control is used to generate control timing for horizontal display based on double character width bit (CWS), horizontal positioning register (HORD), horizontal resolution register (HORR), and HFLB input. A horizontal display line consists of (HORR*12) dots which include 360 dots for 30 display characters and the remaining dots for blank region. The horizontal delay starting from HFLB leading edge is calculated with the following equation,

Horizontal delay time = ( HORD * 6 + 49) * P - phase error detection pulse width Where P = One pixel display time = One horizontal line display time / (HORR*12)

3.5 Phase lock loop (PLL)

On-chip PLL generates system clock timing (VCLK) by tracking the input HFLB and horizontal resolution register (HORR). The frequency of VCLK is determined by the following equation:

TABLE 2. Repeat line weight of character

CH6 - CH0 Repeat Line Weight

CH6,CH5=11 +18*3 CH6,CH5=10 +18*2 CH6,CH5=0x +18

CH4=1 +16 CH3=1 +8 CH2=1 +4 CH1=1 +2 CH0=1 +1

TABLE 3. Repeat line number of character

Repeat Line

Weight

Repeat Line #

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

+1 - - - - - - - - v - - - - - - - - +2 - - - - v - - - - - - - v - - - - +4 - - v - - - v - - - v - - - v - - -

+8 - v - v - v - v - v - v - v - v - +16 - v v v v v v v v v v v v v v v v +17 v v v v v v v v v v v v v v v v v +18 v v v v v v v v v v v v v v v v v v

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VCLK Freq = HFLB Freq * HORR * 12

The VCLK frequency ranges from 6MHz to 96MHz selected by (VCO1, VCO0). In addition, when HFLB input is not present to MTV018, the PLL will generate a specific system clock, approximately 2.5MHz, by a built-in oscillator to ensure data integrity.

3.6 Display & Row control registers

The internal RAM contains display and row control registers. The display registers have 450 locations which are allocated between (row 0, column 0) to (row 14, column 29), as shown in Figure 4. Each display register has its corresponding character address on ADDRESS byte, and 1 blink bit and its corresponding color bits on ATTRIBUTE bytes. The row control register is allocated at column 30 for row 0 to row 14, it is used to set character size to each respective row. If double width character is chosen, only even column characters could be displayed on screen and the odd column characters will be hidden.

FIGURE 4. Memory map

3.6.1 Register descriptions

1. Display Register, (Row 0 - 14, Column 0 - 29) ADDRESS BYTE

CRADDR - Define ROM character and user programmable fonts address. (a) 0 ~ 247 ⇒ 248 build-in characters and graphic symbols. (b) 248 ~ 255 ⇒ 8 user programmable fonts.

ATTRIBUTE BYTE

ROW # COLUMN #

0 1 28 29 30 31

0 1

13 14

DISPLAY

REGISTERS

ROW

CTRL REG

R E S E R V E D

ROW 15

COLUMN#

02 35 68 911 1218 1926

WINDOW1 WINDOW2 WINDOW3 WINDOW4 FRAME

CRTL REG

PWM D/A

CRTL REG

b7 b6 b5 b4 b3 b2 b1 b0

CRADDR

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

- - - - BLINK R1 G1 B1

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BLINK - Enable blinking effect while this bit is set to " 1 ". And the blinking is alternate per 32 vertical frames. R1, G1, B1 - These bits are used to specify its relative address character color 1.

2. Row Control Registers, (Row 0 - 14)

R2, G2, B2 - These bits are used to specify its relative row character color 2. While corresponding CCS bit is

set to 1, color 2 should be chosen. CHS - Define double height character to the respective row. CWS - Define double width character to the respective row.

3.7 User font RAM

The user font RAM have 288 locations which are allocated between (row 0, column 0) to (row 7, column 35) to specify 8 user programmable fonts, as shown in Figure 5. Each programmable font consists of 12x18 dot matrix. And each row of dot matrix consists of 2 bytes data which include 4 dummy bits as shown in figure 6. That is, the dot matrix data of each font are stored in 36 bytes registers. For example, font 0 is stored in row 0 from column 0 to column 35 and font 1 is stored in row 1 from column 0 to column 35. etc.

FIGURE 5. User font RAM memory map

COLN 30

b7 b6 b5 b4 b3 b2 b1 b0

- - - R2 G2 B2 CHS CWS

ROW #

COLUMN #

0 1 34 35 36 63

0 1

6 7

USER FONT RAM RESERVED

Nth byte (N+1)th byte

12 bits for one row data of font dot matrix Dummy bits

rightmost dot of font

Where N=even number

b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0

leftmost dot of font

FIGURE 6. Data format of font dot matrix

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3.8 Character ROM

The character ROM contains 248 built-in characters and symbols from address 0 to 247. Each character and symbol consists of 12x18 dots matrix. The detail pattern structures for each character and symbols are shown in “CHARACTERS AND SYMBOLS PATTERN” on page16.

3.9 Luminance & border generator

There are 2 shift registers included in the design which can shift out of luminance and border dots to color encoder. The bordering and shadowing feature is configured in this block. For bordering effect, the character will be enveloped with blackedge on four sides. For shadowing effect, the character is enveloped with blackedge for right and bottom sides only.

3.10 Window and frame control

The display frame position is completely controlled by the contents of VERTD and HORD. The window size and position control are specified in column 0 to 11 on row 15 of memory map, as shown in Figure 4. Window 1 has the highest priority, and window 4 is the least, when two windows are overlapping. More detailed information is described as follows:

1. Window control registers, ROW 15

START(END) ADDR - These addresses are used to specify the window size. It should be noted that when the

start address is greater than the end address, the window will be disabled. WEN - Enable the window display. CCS - When a window is overlapping with the character, character color 2 should be chosen while this bit is

set to 1. Otherwise color 1 is selected.

R, G, B - Specify the color of the relative background window.

2. Frame control registers, ROW 15

Column

0,3,6,OR 9

b7 b6 b5 b4 b3 b2 b1 b0

ROW START ADDR

MSB LSB

ROW END ADDR

MSB LSB

Column

1,4,7,OR 10

b7 b6 b5 b4 b3 b2 b1 b0

COL START ADDR

MSB LSB

WEN CCS -

Column

2,5,8,OR 11

b7 b6 b5 b4 b3 b2 b1 b0

COL END ADDR

MSB LSB

R G B

Column 12

b7 b6 b5 b4 b3 b2 b1 b0

VERTD

MSB LSB

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VERTD - Specify the starting position for vertical display. The total steps are 256, and the increment of each

step is 4 Horizontal display lines. The initial value is 4 after power up.

HORD - Define the starting position for horizontal display. The total steps are 256, and the increment of each

step is 6 dots. The initial value is 15 after power up.

CH6-CH0 - Define the character vertical height, the height is programmable from 18 to 71 lines. The character

vertical height is at least 18 lines if the contents of CH6-CH0 is less than 18. For example, when the contents is " 2 ", the character vertical height is regarded as equal to 20 lines. And if the contents of CH4-CH0 is greater than or equal to 18, it will be regarded as equal to 17. See Table 2 and Table 3 for detail description of this operation.

HORR - Specify the resolution of a horizontal display line, and the increment of each step is 12 dots. That is,

the pixels' number per H line equal to HORR*12. It is recommended that HORR should be greater than or equal to 36 and smaller than 90M / (Hfreq*12). The initial value is 40 after power up.

RSPACE - Define the row to row spacing in unit of horizontal line. That is, extra RSPACE horizontal lines will

be appended below each display row, and the maximum space is 31 lines. The initial value is 0 after power up.

OSDEN - Activate the OSD operation when this bit is set to "1". The initial value is 0 after power up. BSEN - Enable the bordering and shadowing effect. SHADOW - Activate the shadowing effect if this bit is set, otherwise the bordering is chosen. TRIC - Define the driving state of output pins ROUT, GOUT, BOUT and FBKG when OSD is disabled. That is,

while OSD is disabled, these four pins will drive low if this bit is set to 1, otherwise these four pins are

in high impedance state. The initial value is 0 after power up. BLANK - Force the FBKG pin output to high while this bit is set to "1". WENCLR - Clear all WEN bits of window control registers when this bit is set to "1". The initial value is 0 after

power up.

RAMCLR - Clear all ADDRESS bytes of display registers when this bit is set to "1". The initial value is 0 after

power up.

Column 14

b7 b6 b5 b4 b3 b2 b1 b0

- CH6 CH5 CH4 CH3 CH2 CH1 CH0

Column 15

b7 b6 b5 b4 b3 b2 b1 b0

- HORR MSB LSB

Column 16

b7 b6 b5 b4 b3 b2 b1 b0

- - - RSPACE

MSB LSB

Column 17

b7 b6 b5 b4 b3 b2 b1 b0

OSDEN BSEN SHADOW TRIC BLANK WENCLR RAMCLR FBKGC

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FBKGC - Define the output configuration for FBKG pin. When it is set to "0", the FBKG outputs during the dis-

playing of characters or windows, otherwise, it outputs only during the displaying of characters.

TEST - = 0 ⇒ Normal mode. = 1 ⇒ Test mode, not allowed in applications.

FBKGP - Select the polarity of the output pin FBKG

= 1 ⇒Positive polarity FBKG output is selected. = 0 ⇒Negative polarity FBKG output is selected.

The initial value is 1 after power up. PWMCK - Select the output options to HTONE/PWMCK pin.

= 0 ⇒ HTONE option is selected.

= 1 ⇒ PWMCK option is selected with 50/50 duty cycle and synchronous with the input HFLB. The frequency is selected by (VCO1, VCO0) shown as Table 4 on page 12. The initial value is 0 after power up.

SELVCL - Enable auto detection for horizontal and vertical syncs input edge distorition while the bit is set to

"1". The initial value is 0 after power up.

HSP - = 1 ⇒ Accept positive polarity Hsync input.

= 0 ⇒ Accept negative polarity Hsync input.

VSP - = 1 ⇒ Accept positive polarity Vsync input.

= 0 ⇒ Accept negative polarity Vsync input.

VCO1, VCO0 - Select the appropriate curve partitions of VCO frequency to voltage based on HFLB input and

horizontal resolution register (HORR).

(i) 12K ohm:

= (0, 0) ⇒ 6MHz < Pixel rate < 12MHz = (0, 1) ⇒ 12MHz < Pixel rate < 24MHz = (1, 0) ⇒ 24MHz < Pixel rate < 48MHz = (1, 1) ⇒ 48MHz < Pixel rate < 96MHz (ii) 11K ohm: = (0, 0) ⇒ 6.5MHz < Pixel rate < 13MHz = (0, 1) ⇒ 13MHz < Pixel rate < 26MHz = (1, 0) ⇒ 26MHz < Pixel rate < 52MHz = (1, 1) ⇒ 52MHz < Pixel rate < 96MHz (iii)10K ohm: = (0, 0) ⇒ 7MHz < Pixel rate < 14MHz = (0, 1) ⇒ 14MHz < Pixel rate < 28MHz = (1, 0) ⇒ 28MHz < Pixel rate < 56MHz = (1, 1) ⇒ 56MHz < Pixel rate < 96MHz (iv)9.1K ohm: = (0, 0) ⇒ 7.5MHz < Pixel rate < 15MHz = (0, 1) ⇒ 15MHz < Pixel rate < 30MHz = (1, 0) ⇒ 30MHz < Pixel rate < 60MHz = (1, 1) ⇒ 60MHz < Pixel rate < 96MHz (v)8.2K ohm: = (0, 0) ⇒ 8MHz < Pixel rate < 16MHz = (0, 1) ⇒ 16MHz < Pixel rate < 32MHz

Column 18

B7 b6 b5 b4 b3 b2 b1 b0

TEST FBKGP PWMCK SELVCL HSP VSP VCO1 VCO0

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= (1, 0) ⇒ 32MHz < Pixel rate < 64MHz = (1, 1) ⇒ 64MHz < Pixel rate < 96MHz (vi)7.5K ohm: = (0, 0) ⇒ 8.5MHz < Pixel rate < 17MHz = (0, 1) ⇒ 17MHz < Pixel rate < 34MHz = (1, 0) ⇒ 34MHz < Pixel rate < 68MHz = (1, 1) ⇒ 68MHz < Pixel rate < 96MHz (vii)under or equal to 6.2K ohm: = (0, 0) ⇒ 9.5MHz < Pixel rate < 19MHz = (0, 1) ⇒ 19MHz < Pixel rate < 38MHz = (1, 0) ⇒ 38MHz < Pixel rate < 76MHz = (1, 1) ⇒ 76MHz < Pixel rate < 96MHz

where Pixel rate = VCLK Freq = HFLB Freq * HORR * 12 The initial value is (0, 0) after power up.

Notes :

1. That is, if HORR is specified, and RP resister = 12K ohm, then (VCO1, VCO0)

= (0, 0) if 6000/(HORR * 12) < HFLB Freq (KHz) < 12000/(HORR * 12) = (0, 1) if 12000/(HORR * 12) < HFLB Freq (KHZ) < 24000/(HORR * 12) = (1, 0) if 24000/(HORR * 12) < HFLB Freq (KHZ) < 48000/(HORR * 12) = (1, 1) if 48000/(HORR * 12) < HFLB Freq (KHZ) < 96000/(HORR * 12)

2. It is necessary to wait for the PLL to become stable while (i) the HORR register is changed; (ii) the (VCO1,

VCO0) bits is changed; (iii) the horizontal signal (HFLB) is changed.

3. When PLL is unstable, don't write data in any address except Column 15,17,18 of Row 15. If data is written

in any other address, a malfunction may occur.

3.11 PWM D/A converter

There are 8 open-drain PWM D/A outputs (PWM0 to PWM7). These PWM D/A converter outputs pulse width are programmable by writing data to Column 19 to 26 registers of Row 15 with 8-bit resolution to control the pulse width duration from 0/256 to 255/256. And the sampling rate is selected by (VCO1, VCO0) shown as table 4. In applications, all open-drain output pins should be pulled-up by external resistors to supply voltage (5V to 9V) for desired output range.

ROW 15

PWMDA0 - PWMDA7 - Define the output pulse width of pin PWM0 to PWM7.

TABLE 4. PWMCK Frequency and PWMDA sampling rate

(VCO1, VCO0) PWMCK Freq (6M ~ 12MHz) PWMDA sampling rate (23K ~ 47KHz)

( 0, 0 ) HFLB Freq * HORR * 12 HFLB Freq * HORR * 12 / 256 ( 0, 1 ) HFLB Freq * HORR * 6 HFLB Freq * HORR * 6 / 256 ( 1, 0 ) HFLB Freq * HORR * 3 HFLB Freq * HORR * 3 / 256 ( 1 ,1 ) HFLB Freq * HORR * 3 / 2 HFLB Freq * HORR * 3 / 512

Column 19

Column 26

b7 b6 b5 b4 b3 b2 b1 b0

PWMDA0

PWMDA7

MSB LSB

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TECHNOLOGY

3.12 Color encoder

The decoder generates the video output to ROUT, GOUT and BOUT by integrating window color, border blackedge, luminance output and color selection output (R, G, B) to form the desired video outputs.

4.0 ABSOLUTE MAXIMUM RATINGS

DC Supply Voltage(VDD,VDDA) -0.3 to +7 V Voltage with respect to Ground -0.3 to VDD+0.3 V

Storage Temperature -65 to +150 oC Ambient Operating Temperature 0 to +70 oC

5.0 OPERATING CONDITIONS

DC Supply Voltage(VDD,VDDA) +4.75 to +5.25 V Operating Temperature 0 to +70 oC

6.0 ELECTRICAL CHARACTERISTICS (Under Operating Conditions)

7.0 SWITCHING CHARACTERISTIC (Under Operating Conditions)

Symbol Parameter Conditions (Notes) Min. Max. Units

Input High Voltage - 0.7 * VDD VDD+0.3 V

Input Low Voltage - VSS-0.3

0.3 * VDD

(0.2 * VDD for SSB

pin)

Output High Voltage

≥ -5 mA

VDD-0.8 - V

Output Low Voltage

IOL ≤ 5 mA

- 0.5 V

ODH

Open Drain Output High

Voltage

(For all OD pins, and pulled

up by external 5 to 9V

power supply)

5 9 V

ODL

Open Drain Output Low

Voltage

5 mA ≥ I

DOL

( For all OD pins )

- 0.5 V

Standby Current

Vin = VDD,

load = 0uA

- 12 mA

Operating Current

Pixel rate=96MHz

load = 0uA

- 20 mA

Symbol Parameter Min. Typ. Max. Units

HFLB

HFLB input frequency 15 - 120 KHz

Output rise time - - 5 ns

Output fall time - - 5 ns

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TECHNOLOGY

8.0 TIMING DIAGRAMS

BCSU

SSB to SCK set up time 200 - - ns

BCH

SSB to SCK hold time 100 - - ns

DCSU

SDA to SCK set up time 200 - - ns

DCH

SDA to SCK hold time 100 - - ns

SCKH

SCK high time 500 - - ns

SCKL

SCK low time 500 - - ns

SU:STA

START condition setup time 500 - - ns

HD:STA

START condition hold time 500 - - ns

SU:STO

STOP condition setup time 500 - - ns

HD:STO

STOP condition hold time 500 - - ns

Symbol Parameter Min. Typ. Max. Units

SCK

SSB

SDA

SCKL

SCKH

BCSU

DCSU

DCH

BCH

FIGURE 7. Data interface timing(SPI)

FIGURE 8. Data interface timing(I2C)

SCK

SDA

SU:STA

SCKH

HD:STA

SCKL

DCSU

DCH

SU:STO

HD:STO

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TECHNOLOGY

9.0 PACKAGE DEMENSION

9.1 16 Pin 300mil

9.2 20 pin 300mil

75 +/-20

90 +/-20

250 +/-4

55 +/-20

90 +/-20

312 +/-12

65 +/-4

55 +/-4

310Max

350 +/-20

R10Max

(4X )

100Ty

18 +/-

2Typ

60 +/-

5Typ

115 Min

750 +/-10

15 Min

35 +/-5

7 Typ

R40

15 Max

75 +/-20

90 +/-20

250 +/-4

55 +/-20

90 +/-20

312 +/-12

65 +/-4

55 +/-4

310Max

350 +/-20

R10Max

(4X )

100Typ 18 +/-2Typ

60 +/-5Typ

115 Min

1020 +/-10

15 Min

35 +/-5

7 Typ

15 Max

R40

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TECHNOLOGY

9.3 24 Pin 300mil

10.0 CHARACTERS AND SYMBOLS PATTERN

Please see the attachment.

930+/-10

R40

55+/-20

312+/-12

R10Max (4X)

80+/-20

250+/-4

350+/-20

18+/2Typ

60+/5Typ

15Min.

15Max

115Min

100Ty

35+/-5

7Ty

1245+/-10

65+/-4

Myson Technology USA, Inc.

http://www.myson.com

20111 Stevens Creek Blvd. #138 Cupertino, Ca. 95014, U.S.A. Tel:408-252-8788 FAX: 408-252-8789 [email protected]

Myson Technology, Inc.

http://www.myson.com.tw

No. 2, Industry E. Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. Tel: 886-3-5784866 Fax: 886-3-5785002