Datasheet mtsf3n03hd Datasheet

Page 1

MTSF3N03HD

Preferred Device

Power MOSFET 3 Amps, 30 Volts

N–Channel Micro8

These Power MOSFET devices are capable of withstanding high energy in the avalanche and c ommutation modes a nd the d rain–to–source diode has a very low reverse recovery time. Micro8 devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc–dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients.

• Miniature Micro8 Surface Mount Package – Saves Board Space

• Extremely Low Profile (<1.1 mm) for thin applications such as

PCMCIA cards

• Ultra Low R

Life

• Logic Level Gate Drive – Can Be Driven by Logic ICs

• Diode Is Characterized for Use In Bridge Circuits

• Diode Exhibits High Speed, With Soft Recovery

• I

Specified at Elevated Temperature

DSS

• Avalanche Energy Specified

• Mounting Information for Micro8 Package Provided

Provides Higher Efficiency and Extends Battery

DS(on)

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3 AMPERES

30 VOLTS

DS(on)

= 40 m

N–Channel

Micro8

CASE 846A

STYLE 1

MARKING DIAGRAM

 Semiconductor Components Industries, LLC, 2000

November, 2000 – Rev. 4

WW = Date Code

PIN ASSIGNMENT

Source Source

Source

Gate

ORDERING INFORMATION

Device Package Shipping

MTSF3N03HDR2 Micro8 4000 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

1 Publication Order Number:

2 3

Top View

Drain

Drain Drain

Drain

MTSF3N03HD/D

Page 2

MTSF3N03HD

MAXIMUM RATINGS (T

Drain–to–Source Voltage V Drain–to–Gate Voltage (RGS = 1.0 MΩ) V Gate–to–Source Voltage – Continuous V 1″ SQ.

FR–4 or G–10 PCB Figure 1 below

Steady State Minimum

FR–4 or G–10 PCB Figure 2 below

Steady State Operating and Storage Temperature Range TJ, T Single Pulse Drain–to–Source Avalanche Energy – Starting TJ = 25°C

(VDD = 30 Vdc, VGS = 5.0 Vdc, Peak IL = 9.0 Apk, L = 5.0 mH, RG = 25 )

1. Repetitive rating; pulse width limited by maximum junction temperature.

= 25°C unless otherwise noted)

Rating Symbol Max Unit

Thermal Resistance – Junction to Ambient Total Power Dissipation @ TA = 25°C Linear Derating Factor Drain Current – Continuous @ TA = 25°C Continuous @ TA = 70°C Pulsed Drain Current (Note 1.)

DGR

THJA

DSS

± 20 V

1.79

14.29

0.78

6.25

– 55 to 150 °C

stg

30 V 30 V

Watts

mW/°C

5.7

4.5 45

160

Watts

mW/°C

3.8

3.0 30

200

°C/W

A A A

°C/W

A A A

Figure 1. 1 Square FR–4 or G–10 PCB Figure 2. Minimum FR–4 or G–10 PCB

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Page 3

MTSF3N03HD

)

f = 1.0 MHz)

Vdc, I

Adc

Vdc, I

Adc

Vdc, I

Adc

)

dIS/dt = 100 A/µs) (Note 2.)

ELECTRICAL CHARACTERISTICS (T

Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Drain–to–Source Breakdown Voltage (Cpk ≥ 2.0) (Notes 2. & 4.)

(VGS = 0 Vdc, ID = 250 µAdc) Temperature Coefficient (Positive)

Zero Gate Voltage Drain Current

(VDS = 24 Vdc, VGS = 0 Vdc) (VDS = 24 Vdc, VGS = 0 Vdc, TJ = 125°C)

Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) I

ON CHARACTERISTICS (Note 2.)

Gate Threshold Voltage (Cpk ≥ 2.0) (Note 4.)

(VDS = VGS, ID = 250 µAdc) Threshold Temperature Coefficient (Negative)

Static Drain–to–Source On–Resistance (Cpk ≥ 2.0) (Note 4.)

(VGS = 10 Vdc, ID = 3.8 Adc) (VGS = 4.5 Vdc, ID = 1.9 Adc)

Forward Transconductance (VDS = 10 Vdc, ID = 1.9 Adc) g

DYNAMIC CHARACTERISTICS

Input Capacitance Output Capacitance Transfer Capacitance

SWITCHING CHARACTERISTICS (Note 3.)

Turn–On Delay Time Rise Time Turn–Off Delay Time Fall Time t Turn–On Delay Time t Rise Time Turn–Off Delay Time Fall Time t Gate Charge

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage

Reverse Recovery Time

Reverse Recovery Storage Charge Q

2. Pulse Test: Pulse Width ≤300 µs, Duty Cycle ≤ 2%.

3. Switching characteristics are independent of operating junction temperature.

4. Reflects typical values. Cpk =

Max limit – Typ

= 25°C unless otherwise noted)

(VDS = 25 Vdc, VGS = 0 Vdc,

(VDS = 15 Vdc, ID = 3.7 Adc,

VGS = 10 Vdc, RG = 6 Ω) (Note 2.)

(VDD = 15 Vdc, ID = 1.9 Adc,

VGS = 4.5 Vdc, RG = 6 Ω) (Note 2.)

(VDS = 24 Vdc, ID = 3.7 Adc,

(IS = 3.7 Adc, VGS = 0 Vdc) (Note 2.)

3 x SIGMA

f = 1.0 MHz

VGS = 10 Vdc)

(IS = 3.7 Adc, VGS = 0 Vdc,

TJ = 125°C)

(IS = 3.7 Adc, VGS = 0 Vdc,

/dt = 100 A/µs) (Note 2.

3.7

1.9

3.7

(BR)DSS

DSS

GSS

GS(th)

DS(on)

iss

oss

rss

d(on)

d(off)

d(on)

d(off)

Q Q Q Q

–

– –

– – 100 nAdc

1.0 –

– –

2.0 – – Mhos

– 420 – pF – 190 – – 65 –

– 7.0 – ns – 19 – – 32 – – 36 – – 7.0 – ns – 11 – – 29 – – 23 –

T 1 2 3

– 18.5 26 nC – 1.4 – – 5.5 – – 7.1 –

– –

– 28 – – 14 – – 14 – – 0.028 – µC

–

– –

1.5

4.5

35 45

0.82

0.7

– –

1.0 25

– –

40 60

1.0

–

Vdc

mV/°C

µAdc

Vdc

mV/°C

mΩ

Vdc

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MTSF3N03HD

TYPICAL ELECTRICAL CHARACTERISTICS

, DRAIN CURRENT (AMPS)

0 0.5 1.5 2

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS = 10 V

4.5 V

3.3 V

3.1 V

= 25°C

2.9 V

2.7 V

2.5 V

2.3 V

2.1 V

Figure 3. On–Region Characteristics

0.6 ID = 3.8 A T

= 25°C

0.5

0.4

0.3

, DRAIN CURRENT (AMPS)

0.06

0.055

0.05

0.045

≥ 10 V

100°C

1.51

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

2 2.5 3 3.5 4

Figure 4. Transfer Characteristics

= 25°C

VGS = 4.5

25°C

= -55°C

0.2

0.1

, DRAIN-TO-SOURCE RESISTANCE (OHMS)

DS(on)

24 86

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. On–Resistance versus

Gate–to–Source Voltage

2.0 VGS = 10 V ID = 1.9 A

1.5

1.0

0.5

, DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

-50 0 50 100 150

DS(on)

, JUNCTION TEMPERATURE (°C)

Figure 7. On–Resistance Variation

with Temperature

0.04 10 V

0.035

, DRAIN-TO-SOURCE RESISTANCE (OHMS)

0.03

DS(on)

012 56

ID, DRAIN CURRENT (AMPS)

Figure 6. On–Resistance versus Drain Current

and Gate Voltage

1000

VGS = 0 V

= 125°C

100

100°C

, LEAKAGE (nA)

DSS

0.1

1257525-25

0 5 10 15 30

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

25°C

20 25

Figure 8. Drain–to–Source Leakage Current

versus V oltage

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MTSF3N03HD

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted

by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (I

) can be made from a

G(AV)

rudimentary analysis of the drive circuit so that t = Q/I

G(AV)

During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, V

. Therefore, rise and fall

SGP

times may be approximated by the following: tr = Q2 x RG/(VGG – V

tf = Q2 x RG/V

GSP

)

where VGG = the gate drive voltage, which varies from zero to V

RG = the gate drive resistance and Q2 and V

are read from the gate charge curve.

GSP

During the turn–on and turn–off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are:

d(on)

d(off)

= RG C

In [VGG/(VGG – V

iss

In (VGG/V

iss

GSP

)]

GSP

)

The capacitance (C

) is read from the capacitance curve at

iss

a voltage corresponding to the off–state condition when calculating t on–state when calculating t

and is read at a voltage corresponding to the

d(on)

d(off)

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified.

The resistive switching time variation versus gate resistance (Figure 11) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

1500

1200

C, CAPACITANCE (pF)

VDS = 0 V

iss

900

rss

600

300

10 0 10 15 25

VGS = 0 V

rss

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 9. Capacitance Variation

= 25°C

iss

oss

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MTSF3N03HD

, GATE-TO-SOURCE VOLTAGE (VOLTS)

03 659

Qg, TOTAL GATE CHARGE (nC)

12 15

ID = 3.7 A T

= 25°C

18 21

Figure 10. Gate–To–Source and

Drain–To–Source Voltage versus Total Charge

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI.

System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 13. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses.

The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by

1000

VDD = 15 V ID = 3.7 A VGS = 10 V T

= 25°C

100

t, TIME (ns)

, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

1 10010

d(off)

d(on)

RG, GATE RESISTANCE (OHMS)

Figure 11. Resistive Switching Time

Variation versus Gate Resistance

high di/dts. The diode’s negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy.

Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

VGS = 0 V T

= 25°C

, SOURCE CURRENT (AMPS)

0.5 0.6 0.7

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

0.8 0.9

Figure 12. Diode Forward Voltage versus Current

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Page 7

MTSF3N03HD

di/dt = 300 A/µs

, SOURCE CURRENT

Figure 13. Reverse Recovery Time (trr)

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curve (Figure

14) defines the maximum simultaneous drain–to–source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance – General Data and Its Use.”

Switching between the off–state and the on–state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (V

) is exceeded, and that the

DSS

transition time (tr, tf) does not exceed 10 µs. In addition the total power averaged over a complete switching cycle must not exceed (T

J(MAX)

– TC)/(R

θJC

A power MOSFET designated E–FET can be safely used in switching circuits with unclamped inductive loads. For

Standard Cell Density

High Cell Density

t, TIME

reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non–linearly with an increase of peak current in avalanche and peak junction temperature.

Although many E–FETs can withstand the stress of drain–to–source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 15). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

100

VGS = 20 V SINGLE PULSE

, DRAIN CURRENT (AMPS)

0.1

0.01

0.1

= 25°C

10 ms

LIMIT

DS(on)

THERMAL LIMIT PACKAGE LIMIT

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

100 µs

1 ms

Figure 14. Maximum Rated Forward Biased

Safe Operating Area

250

VDD = 30 V

200

150

100

AVALANCHE ENERGY (mJ)

, SINGLE PULSE DRAINTOSOURCE

100

25 50 75 100 125

, STARTING JUNCTION TEMPERATURE (°C)

VGS = 5 V

IL = 9 A

L = 5 mH

Figure 15. Maximum Avalanche Energy versus

Starting Junction Temperature

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Page 8

1000

MTSF3N03HD

TYPICAL ELECTRICAL CHARACTERISTICS

100

1.0

THERMAL RESISTANCE ( C/W)°

Rthja(t), EFFECTIVE TRANSIENT

0.1

1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01

D = 0.5

0.2

0.1

0.05

0.02

0.01

SINGLE PULSE

t, TIME (s)

(pk)

DUTY CYCLE, D = t1/t

Figure 16. Thermal Response

di/dt

0.25 I

TIME

(t) = r(t) R

θJC

D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t T

J(pk)

θJC

- TC = P

(pk)

1.0E+02 1.0E+03

(t)

θJC

Figure 17. Diode Reverse Recovery Waveform

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MTSF3N03HD

INFORMATION FOR USING THE Micro8 SURFACE MOUNT PACKAGE

MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a c ritical p ortion o f t he total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection

0.208

5.28

0.015

0.38

Micro8 POWER DISSIPATION

The power dissipation of the Micro8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by T temperature of the die, R

, the maximum rated junction

J(max)

, the thermal resistance from

θJA

the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the Micro8 package, PD can be calculated as follows:

PD =

J(max)

θJA

– T

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

interface between the board and the package. With the correct pad geometry, the packages will self–align when subjected to a solder reflow process.

0.041

1.04

0.126

3.20

0.0256

0.65

inches

into the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device which in this case is 0.78 Watts.

PD =

150°C – 25°C

160°C/W

= 0.78 Watts

The 160°C/W for the Micro8 package assumes the

recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 0.78 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS

The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected.

• Always preheat the device.

• The delta temperature between the preheat and

soldering should be 100°C or less.*

• When preheating and soldering, the temperature of the

leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C.

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• The soldering temperature and time shall not exceed 260°C for more than 10 seconds.

• When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less.

• After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress.

• Mechanical stress or shock should not be applied during cooling.

* Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

Page 10

MTSF3N03HD

TYPICAL SOLDER HEATING PROFILE

For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating “profile” for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows

200°C

150°C

100°C

STEP 1

PREHEAT

ZONE 1 “RAMP”

DESIRED CURVE FOR HIGH

STEP 2

VENT

“SOAK”

MASS ASSEMBLIES

150°C

100°C

HEATING

ZONES 2 & 5

STEP 3

“RAMP”

temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177–189°C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 4

HEATING

ZONES 3 & 6

“SOAK”

160°C

140°C

STEP 5

HEATING

ZONES 4 & 7

“SPIKE”

170°C

SOLDER IS LIQUID FOR

40 TO 80 SECONDS

(DEPENDING ON

MASS OF ASSEMBLY)

STEP 6

VENT

STEP 7

COOLING

205° TO 219°C

PEAK AT SOLDER

JOINT

5°C

DESIRED CURVE FOR LOW

MASS ASSEMBLIES

TIME (3 TO 7 MINUTES TOTAL) T

Figure 18. Typical Solder Heating Profile

MAX

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Page 11

Micro8

Dimensions are shown in millimeters (inches)

MTSF3N03HD

TAPE & REEL INFORMATION

2.05 (.080)

1.95 (.077)

4.10 (.161)

3.90 (.154)

12.30

11.70

(.484)

(.461)

PIN NUMBER 1

FEED DIRECTION

NOTES:

1. CONFORMS TO EIA–481–1.

2. CONTROLLING DIMENSION: MILLIMETER.

5.40 (.212)

5.20 (.205)

SECTION B–B

BBA

8.10 (.318)

7.90 (.312)

1.60 (.063)

1.50 (.059)

1.85 (.072)

1.65 (.065)

5.55 (.218)

5.45 (.215)

1.60 (.063)

1.50 (.059) TYP.

0.35 (.013)

0.25 (.010)

3.50 (.137)

3.30 (.130)

1.50 (.059)

1.30 (.052)

SECTION A–A

330.0

(13.20)

MAX.

NOTES:

1. CONFORMS TO EIA–481–1.

2. CONTROLLING DIMENSION: MILLIMETER.

3. INCLUDES FLANGE DISTORTION AT OUTER EDGE.

4. DIMENSION MEASURED AT INNER HUB.

18.4 (.724) MAX.

NOTE 3

13.2 (.52)

12.8 (.50)

50.0

(1.97)

MIN.

14.4 (.57)

12.4 (.49) NOTE 4

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Page 12

–T–

0.038 (0.0015)

PIN 1 ID

SEATING PLANE

MTSF3N03HD

PACKAGE DIMENSIONS

Micro8

CASE 846A–02

ISSUE E

NOTES:

–A–

–B–

8 PL

0.08 (0.003) A

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

DIM MIN MAX MIN MAX

A 2.90 3.10 0.114 0.122 B 2.90 3.10 0.114 0.122 C --- 1.10 --- 0.043 D 0.25 0.40 0.010 0.016 G 0.65 BSC 0.026 BSC H 0.05 0.15 0.002 0.006

J 0.13 0.23 0.005 0.009

K 4.75 5.05 0.187 0.199

L 0.40 0.70 0.016 0.028

STYLE 1:

PIN 1. SOURCE

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

INCHESMILLIMETERS

Micro8 is a trademark of International Rectifier. Thermal Clad is a registered trademark of the Bergquist Company.

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

NORTH AMERICA Literature Fulfillment:

Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: [email protected]

Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada

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