Datasheet MTP75N03HDL Datasheet (Motorola)

1

Motorola TMOS Power MOSFET Transistor Device Data

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 



   

N–Channel Enhancement–Mode Silicon Gate

This advanced high–cell density HDTMOS E–FET is designed to
withstand high energy in the avalanche and commutation modes.
This new energy efficient design also o ffers a drain–to–source
diode w ith a f ast r ecovery t ime. Designed for l ow–voltage,
high–speed switching applications in power supplies, converters
and PWM m otor controls, a nd inductive loads. The a valanche
energy capability is specified to eliminate the guesswork in designs
where inductive loads are switched, and to offer additional safety
margin against unexpected voltage transients.

• Ultra Low R

DS(on)

, High–Cell Density, HDTMOS

• SPICE Parameters Available

• Diode is Characterized for Use in Bridge Circuits

• I

DSS

and V

DS(on)

Specified at Elevated Temperature

• Avalanche Energy Specified

MAXIMUM RATINGS

(TC = 25°C unless otherwise noted)

Rating Symbol Value Unit

Drain–Source Voltage V

DSS

25 Vdc

Drain–Gate Voltage (RGS = 1.0 MΩ) V

DGR

25 Vdc

Gate–Source Voltage — Continuous

Gate–Source Voltage — Single Pulse (tp ≤ 10 ms)

V

GS

± 15
± 20

Vdc
Vpk

Drain Current — Continuous

— Continuous @ 100°C
— Single Pulse (tp ≤ 10 µs)

I

D

I

D

I

DM

75
59

225

Adc

Apk

Total Power Dissipation

Derate above 25°C

P

D

150

1.0

Watts

W/°C

Operating and Storage Temperature Range TJ, T

stg

–55 to 175 °C

Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C

(VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 75 Apk, L = 0.1 mH, RG = 25 Ω)

E

AS

280 mJ

Thermal Resistance — Junction to Case

— Junction to Ambient

R

θJC

R

θJA

1.0

62.5

°C/W

Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T

L

260 °C

This document contains information on a new product. Specifications and information herein are subject to change without notice.

E–FET and HDTMOS are trademarks of Motorola, Inc.
TMOS is a registered trademark of Motorola, Inc.

Preferred devices are Motorola recommended choices for future use and best overall value.

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by MTP75N03HDL/D

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SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995



TMOS POWER FET

LOGIC LEVEL

75 AMPERES

R

DS(on)

= 9.0 mOHM

25 VOLTS

Motorola Preferred Device



D

S

G

CASE 221A–06, Style 5

TO–220AB

MTP75N03HDL

2

Motorola TMOS Power MOSFET Transistor Device Data

ELECTRICAL CHARACTERISTICS

(TJ = 25°C unless otherwise noted)

Characteristic

Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Drain–Source Breakdown Voltage

(Cpk ≥ 2.0) (3)
(VGS = 0 Vdc, ID = 0.25 mA)
Temperature Coefficient (Positive)

V

(BR)DSS

25 — —

Vdc

mV/°C

Zero Gate Voltage Drain Current

(VDS = 25 Vdc, VGS = 0 Vdc)
(VDS = 25 Vdc, VGS = 0 Vdc, TJ = 125°C)

I

DSS

—
—

—
—

100
500

µAdc

Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 V) I

GSS

— — 100 nAdc

ON CHARACTERISTICS (1)

Gate Threshold Voltage (Cpk ≥ 3.0) (3)

(VDS = VGS, ID = 0.25 mA)
Temperature Coefficient (Negative)

V

GS(th)

1.0 1.5 2.0

Vdc

mV/°C

Static Drain–Source On–Resistance

(Cpk ≥ 2.0) (3)
(VGS = 5.0 Vdc, ID = 37.5 Adc)

R

DS(on)

— 6.0 9.0

mΩ

Drain–Source On–Voltage (VGS = 10 Vdc)

(ID = 75 Adc)
(ID = 37.5 Adc, TJ = 125°C)

V

DS(on)

—
—

—

0.68

0.6

Vdc

Forward Transconductance (VDS = 3.0 Vdc, ID = 20 Adc) g

FS

15 55 — mhos

DYNAMIC CHARACTERISTICS

Input Capacitance

C

iss

— 4025 5635 pF

Output Capacitance

(VDS = 25 Vdc, VGS = 0 Vdc,

f = 1.0 MHz)

C

oss

— 1353 1894

Reverse Transfer Capacitance

f = 1.0 MHz)

C

rss

— 307 430

SWITCHING CHARACTERISTICS (2)

Turn–On Delay Time

t

d(on)

— 24 48 ns

Rise Time

t

r

— 493 986

Turn–Off Delay Time

VGS = 5.0 Vdc,

Rg = 4.7 Ω)

t

d(off)

— 60 120

Fall Time

g

= 4.7 Ω)

t

f

— 149 300

Q

T

— 61 122 nC

DS

= 24 Vdc, ID = 75 Adc,

Q

1

— 14 28

(VDS = 24 Vdc, ID = 75 Adc,

VGS = 5.0 Vdc)

Q

2

— 33 66

Q

3

— 27 54

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage

(IS = 75 Adc, VGS = 0 Vdc)

(IS = 75 Adc, VGS = 0 Vdc, TJ = 125°C)

V

SD

—
—

0.97

0.87

1.1
—

Vdc

t

rr

— 58 —

S

= 75 Adc, VGS = 0 Vdc,

t

a

— 27 —

(IS = 75 Adc, VGS = 0 Vdc,

dIS/dt = 100 A/µs)

t

b

— 30 —

Reverse Recovery Stored Charge Q

RR

— 0.088 — µC

(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.

Cpk =

Max limit – Typ

3 x SIGMA

Gate Charge

Reverse Recovery Time

(VDS = 15 Vdc, ID = 75 Adc,

(V

(I

ns

MTP75N03HDL

3

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

R

DS(on)

, DRAIN–TO–SOURCE RESISTANCE (OHMS)

R

DS(on)

, DRAIN–TO–SOURCE RESISTANCE

(NORMALIZED)

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 1. On–Region Characteristics

I

D

, DRAIN CURRENT (AMPS)

I

D

, DRAIN CURRENT (AMPS)

VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

R

DS(on)

, DRAIN–TO–SOURCE RESISTANCE (OHMS)

ID, DRAIN CURRENT (AMPS)

Figure 3. On–Resistance versus Drain Current

and Temperature

ID, DRAIN CURRENT (AMPS)

Figure 4. On–Resistance versus Drain Current

and Gate Voltage

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On–Resistance Variation with

Temperature

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 6. Drain–To–Source Leakage

Current versus Voltage

I

DSS

, LEAKAGE (nA)

TJ = 25

°C

VDS ≥ 10 V

TJ = 100

°C

25

°C

–55

°C

TJ = 25

°C

VGS = 0 V

VGS = 10 V

VGS = 5 V

VGS = 5 V

VGS = 10 V
ID = 37.5 A

0.4 0.8 1.2 1.6 20 0.2 0.6 1 1.4 1.8

30

60

90

120

150

0

2 2.5 3.5 4 4.51.5

30

60

90

120

150

0

3

30 60 90 120 1500

0.01

0.002

0.008

0.006

0.004

25 50 100 125 1500

0.005

0.006

0.007

0.008

0.009

0.004
75

25 100 150–50 –25 0 50 75 125

0.4

0.8

1.2

1.6

2

0

10 20 300 5 15 25

10

100

1000

10000

1

10 V

100°C

25°C

TJ = 125°C

100°C

25°C

TJ = –55

°C

3.5 V

3 V

4 V

2.5 V

4.5 V

5 V

8 V

6 V

MTP75N03HDL

4

Motorola TMOS Power MOSFET Transistor Device Data

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter­mined by how fast the FET input capacitance can be charged
by current from the generator.

The published capacitance data is difficult to use for calculat­ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly , gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I

G(AV)

) can be made from a rudimentary analysis of

the drive circuit so that
t = Q/I

G(AV)

During the rise and fall time interval when switching a resis­tive load, VGS remains virtually constant at a level known as
the plateau voltage, V

SGP

. Therefore, rise and fall times may

be approximated by the following:
tr = Q2 x RG/(VGG – V

GSP

)

tf = Q2 x RG/V

GSP

where
VGG = the gate drive voltage, which varies from zero to V

GG

RG = the gate drive resistance
and Q2 and V

GSP

are read from the gate charge curve.

During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val­ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

t

d(on)

= RG C

iss

In [VGG/(VGG – V

GSP

)]

t

d(off)

= RG C

iss

In (VGG/V

GSP

)

The capacitance (C

iss

) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal­culating t

d(on)

and is read at a voltage corresponding to the

on–state when calculating t

d(off)

.

At high switching speeds, parasitic circuit elements com­plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func­tion of drain current, the mathematical solution is complex.
The M OSFET output capacitance also complicates t he
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea­sure and, consequently, is not specified.

The resistive switching time variation versus gate resis­tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op­erated into an inductive load; however, snubbing reduces
switching losses.

GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)

C, CAPACITANCE (pF)

Figure 7. Capacitance Variation

V

GS

V

DS

TJ = 25

°C

VDS = 0 V VGS = 0 V

15000

12000

9000

6000

3000

0

20 2510 150 510 5

C

rss

C

iss

C

oss

C

rss

C

iss

MTP75N03HDL

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Motorola TMOS Power MOSFET Transistor Device Data

V

DS

, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

V

GS

, GATE–TO–SOURCE VOLTAGE (VOLTS)

Figure 8. Gate–To–Source and Drain–To–Source

Voltage versus Total Charge

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

RG, GATE RESISTANCE (OHMS)

1 10 100

t, TIME (ns)

TJ = 25°C
ID = 75 A
VDD = 15 V
VGS = 5 V

t

r

t

f

t

d(off)

t

d(on)

0

QT, TOTAL GATE CHARGE (nC)

10 20 30 40 70

TJ = 25°C
ID = 75 A

10000

1000

100

10

6

4

2

0

7

5

3

1

28

24

20

16

12

8

4

50 60

0

QT

Q1

Q3

V

GS

V

DS

Q2

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse re­covery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.

System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier de­vice, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 12. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.

The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ring­ing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

di/dts. The diode’s negative di/dt during ta is directly con­trolled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode charac­teristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.

Compared to Motorola standard cell density low voltage
MOSFETs, high c ell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse re­covery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise gen­erated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)

I

S

, SOURCE CURRENT (AMPS)

TJ = 25°C
VGS = 0 V

Figure 10. Diode Forward Voltage versus Current

0.6 0.7 0.8 0.9 10.5

0

15

30

45

60

75

SAFE OPERATING AREA

MTP75N03HDL

6

Motorola TMOS Power MOSFET Transistor Device Data

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define
the maximum s imultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for­ward biased. Curves are based upon maximum peak junc­tion temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–Gen­eral Data and Its Use.”

Switching between the off–state and the on–state may tra­verse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 µs. In addition the total power
averaged over a complete switching cycle must not exceed
(T

J(MAX)

– TC)/(R

θJC

).

A power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-

able operation, the stored energy from circuit inductance dis­sipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction tem­perature.

Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur­rent (ID), in accordance with industry custom. The energy rat­ing m ust be d erated f or t emperature a s shown i n the
accompanying graph (Figure 13). Maximum energy at cur­rents below rated continuous ID can safely be assumed to
equal the values indicated.

0.1 100

R

DS(on)

LIMIT
THERMAL LIMIT
PACKAGE LIMIT

10

VGS = 20 V
SINGLE PULSE
TC = 25°C

1

10

100

1000

1

dc

100 µs

1 ms

10 ms

TJ, STARTING JUNCTION TEMPERATURE (°C)

E

AS

, SINGLE PULSE DRAIN–TO–SOURCE

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Avalanche Energy versus

Starting Junction Temperature

AVALANCHE ENERGY (mJ)

I

D

, DRAIN CURRENT (AMPS)

25 50 75 100 125

ID = 75 A

150

80

280

200

160

120

240

40

0

MTP75N03HDL

7

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

R

θ

JC

(t) = r(t) R

θ

JC

D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t

1

T

J(pk)

– TC = P

(pk)

R

θ

JC

(t)

P

(pk)

t

1

t

2

DUTY CYCLE, D = t1/t

2

t, TIME (s)

Figure 13. Thermal Response

r(t), NORMALIZED EFFECTIVE

TRANSIENT THERMAL RESISTANCE

Figure 14. Diode Reverse Recovery Waveform

di/dt

t

rr

t

a

t

p

I

S

0.25 I

S

TIME

I

S

t

b

1.0

0.1

0.01

0.2

D = 0.5

0.05

0.01

SINGLE PULSE

0.1

1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01

0.02

MTP75N03HDL

8

Motorola TMOS Power MOSFET Transistor Device Data

PACKAGE DIMENSIONS

CASE 221A–06

ISSUE Y

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.570 0.620 14.48 15.75
B 0.380 0.405 9.66 10.28
C 0.160 0.190 4.07 4.82
D 0.025 0.035 0.64 0.88
F 0.142 0.147 3.61 3.73
G 0.095 0.105 2.42 2.66
H 0.110 0.155 2.80 3.93
J 0.018 0.025 0.46 0.64
K 0.500 0.562 12.70 14.27
L 0.045 0.060 1.15 1.52
N 0.190 0.210 4.83 5.33
Q 0.100 0.120 2.54 3.04
R 0.080 0.110 2.04 2.79
S 0.045 0.055 1.15 1.39
T 0.235 0.255 5.97 6.47
U 0.000 0.050 0.00 1.27
V 0.045 ––– 1.15 –––
Z ––– 0.080 ––– 2.04

B

Q

H

Z

L

V

G

N

A

K

F

1 2 3

4

D

SEATING
PLANE

–T–

C

S

T

U

R
J

STYLE 5:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

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MTP75N03HDL/D

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◊