Datasheet MTP60N05HDL Datasheet (Motorola)

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SEMICONDUCTOR TECHNICAL DATA

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N–Channel Enhancement–Mode Silicon Gate

This advanced high–cell density HDTMOS power FET is
designed to withstand high energy in the avalanche and commuta­tion modes. The new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for low
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.

• Avalanche Energy Specified

• Source–to–Drain Diode Recovery Time Comparable to a Dis-

crete Fast Recovery Diode

• Diode is Characterized for Use in Bridge Circuits

• I

DSS

and V

Specified at Elevated Temperature

DS(on)

Order this document

by MTP60N05HDL/D



Motorola Preferred Device

TMOS POWER FET

60 AMPERES

50 VOLTS

R



D

DS(on)

= 0.014 OHM

G

S

MAXIMUM RATINGS

Drain–to–Source Voltage V
Drain–to–Gate Voltage (RGS = 1.0 MΩ) V
Gate–to–Source Voltage — Continuous

Drain Current — Continuous

— Continuous @ 100°C
— Single Pulse (tp ≤ 10 µs)

Total Power Dissipation
Derate above 25°C

Operating and Storage Temperature Range TJ, T
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C

(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 60 Apk, L = 0.3 mH, RG = 25 Ω)
Thermal Resistance — Junction to Case

Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 5 Seconds T

E–FET and HDTMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
Preferred devices are Motorola recommended choices for future use and best overall value.

(TC = 25°C unless otherwise noted)

Rating Symbol Value Unit

— Non–Repetitive (tp ≤ 10 ms)

— Junction to Ambient

V

V

I

E

R
R

DSS

DGR

GSM

I
I

DM
P

θJC
θJA

CASE 221A–06, Style 5

GS

D
D

D

stg

AS

L

–55 to 175 °C

TO–220AB

50 Vdc
50 Vdc

± 15
± 20

60
42

180
150

1.0

540 mJ

1.0

62.5
260 °C

Vdc
Vpk

Adc

Apk

Watts

W/°C

°C/W

Motorola TMOS Power MOSFET Transistor Device Data

 Motorola, Inc. 1997

1

MTP60N05HDL

)

f = 1.0 MHz)

(

DD

,

D

,

(

DD

,

D

,

(

S

,

GS

,

ELECTRICAL CHARACTERISTICS

OFF CHARACTERISTICS

Drain–to–Source Breakdown Voltage

(VGS = 0 Vdc, ID = 0.25 mAdc)
T emperature Coef ficient (Positive)

Zero Gate Voltage Drain Current

(VDS = 50 Vdc, VGS = 0 Vdc)
(VDS = 50 Vdc, VGS = 0 Vdc, TJ = –25°C)

Gate–Body Leakage Current

(VGS = ± 15 Vdc, VDS = 0 Vdc)

ON CHARACTERISTICS (1)

Gate Threshold Voltage

(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)

Static Drain–to–Source On–Resistance

(VGS = 5.0 Vdc, ID = 30 Adc)

Drain–to–Source On–Voltage (VGS = 5.0 Vdc)

(ID = 60 Adc)
(ID = 30 Adc, TJ = 125°C)

Forward Transconductance

(VDS = 4.0 Vdc, ID = 20 Adc)

DYNAMIC CHARACTERISTICS

Input Capacitance
Output Capacitance
Transfer Capacitance

SWITCHING CHARACTERISTICS (2)

Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time t
Gate Charge

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage

Reverse Recovery Time

Reverse Recovery Stored Charge Q

(1) Pulse Test: Pulse Width ≤300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.

(TJ = 25°C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit

(VDS = 25 Vdc, VGS = 0 Vdc,

f = 1.0 MHz

(VDD = 25 Vdc, ID = 60 Adc,

VGS = 5.0 Vdc, RG = 9.1 Ω)

(VDD = 25 Vdc, ID = 60 Adc,
VGS = 5.0 Vdc, RG = 9.1 W)

(IS = 60 Adc, VGS = 0 Vdc)

(IS = 60 Adc, VGS = 0 Vdc, TJ = 125°C)

(IS = 30 Adc, VGS = 0 Vdc,

dIS/dt = 100 A/µs)

V

(BR)DSS

I

DSS

I

GSS

V

GS(th)

R

DS(on)

V

DS(on)

g

FS

C

iss

C

oss

C

rss

t

d(on)

t

r

t

d(off)

f

Q
Q
Q
Q

V

SD

t

rr

t

a

t

b

RR

50

—

—
—

— — 100

1.0
—

— 0.010 0.014

—
—

15 48 —

— 2775 4000 pF
— 750 1070
— 150 300

— 21 40 ns
— 570 1150
— 86 170
— 200 400

T
1
2
3

— 42 62 nC
— 8.0 —
— 24 —
— 17 —

—
—

— 50 —
— 34 —
— 15 —
— 0.085 — µC

—
55

—
—

1.5

4.5

—
—

0.95

0.85

—
—

10

100

2.0
—

1.0

0.75

1.1
—

Vdc

mV/°C

µAdc

nAdc

Vdc

mV/°C

Ohms

Vdc

mhos

Vdc

ns

2

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

MTP60N05HDL

120

VGS = 10 V

100

80

60

40

, DRAIN CURRENT (AMPS)

D

I

20

0

0 1.0 2.0 3.0 4.0 5.00.5 1.5 2.5 3.5 4.5

VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS) VGS, GATE–T O–SOURCE VOL TAGE (VOLTS)

4.5 V

6.0 V

5.0 V

4.0 V

8.0 V

TJ = 25°C

3.5 V

3.0 V

2.5 V

120

VDS ≥ 10 V

100

80

60

40

, DRAIN CURRENT (AMPS)

D

I

20

0

1.5 2.0 2.5 4.03.0 3.5

TJ = 125°C

–55°C

Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics

0.018

0.016
TJ = 100°C

0.014

0.012

25°C

0.010

0.008

, DRAIN–TO–SOURCE RESIST ANCE (OHMS)

0.006

DS(on)

R

0 20 40 60 80 120100 0 20 40 60 80 120100

–55°C

11010 30 50 70 90

ID, DRAIN CURRENT (AMPS)

0.014

0.013

0.012

0.011

0.010

0.009

0.008

, DRAIN–TO–SOURCE RESIST ANCE (OHMS)

0.007

0.006

DS(on)

R

TJ = 25°C

VGS = 5.0 V

10 V

ID, DRAIN CURRENT (AMPS)

25°C

Figure 3. On–Resistance versus Drain Current

and T emperature

1.8

1.6

1.4

1.2

(NORMALIZED)

1.0

, DRAIN–TO–SOURCE RESIST ANCE

0.8

DS(on)

R

0.6

VGS = 10 V
ID = 5.0 A

– 50 – 25 0 25 50 75 100 125 150

TJ, JUNCTION TEMPERATURE (

°

C) VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

Figure 5. On–Resistance Variation with

Temperature

Figure 4. On–Resistance versus Drain Current

and Gate Voltage

10,000

VGS = 0 V

1000

100

, LEAKAGE (nA)

DSS

I

10

1.0

5.0 10 20 35 40 5030

TJ = 125°C

100°C

25°C

Figure 6. Drain–T o–Source Leakage

Current versus Voltage

4515 25

Motorola TMOS Power MOSFET Transistor Device Data

3

MTP60N05HDL

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter­mined by how fast the FET input capacitance can be charged
by current from the generator.

The published capacitance data is difficult to use for calculat­ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly , gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I

) can be made from a rudimentary analysis of

G(A V)

the drive circuit so that
t = Q/I

G(AV)

During the rise and fall time interval when switching a resis­tive load, VGS remains virtually constant at a level known as
the plateau voltage, V

. Therefore, rise and fall times may

SGP

be approximated by the following:
tr = Q2 x RG/(VGG – V
tf = Q2 x RG/V

GSP

GSP

)

where
VGG = the gate drive voltage, which varies from zero to V

GG

RG = the gate drive resistance
and Q2 and V

are read from the gate charge curve.

GSP

During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val­ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

t

d(on)

t

d(off)

= RG C
= RG C

In [VGG/(VGG – V

iss

In (VGG/V

iss

GSP

)]

GSP

)

The capacitance (C

) is read from the capacitance curve at

iss

a voltage corresponding to the off–state condition when cal­culating t
on–state when calculating t

and is read at a voltage corresponding to the

d(on)

d(off)

.

At high switching speeds, parasitic circuit elements com­plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func­tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea­sure and, consequently , is not specified.

The resistive switching time variation versus gate resis­tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op­erated into an inductive load; however, snubbing reduces
switching losses.

10,000

9000
8000
7000
6000
5000
4000
3000

C, CAPACITANCE (pF)

2000
1000

0

–10 0 10 15 20 25

VDS = 0 VGS = 0

C

iss

C

rss

C

C

C

rss

–5.0 5.0

V

GATE–T O–SOURCE OR DRAIN–TO–SOURCE VOL TAGE (VOLTS)

GS

V

DS

oss

Figure 7. Capacitance Variation

TJ = 25°C

iss

4

Motorola TMOS Power MOSFET Transistor Device Data

8.0

6.0

QT

MTP60N05HDL

60

GS

50

40

V

1000

VDD = 25 V
ID = 60 A
VGS = 5.0 V
TJ = 25

°

C

t

r

t

f

t

d(off)

4.0
Q2Q1

2.0

, GATE–T O–SOURCE VOL TAGE (VOLTS)

GS

V

0

Q3

010 405020 30

QG, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (OHMS)

TJ = 60°C
ID = 5.0 A

V

DS

30

20

10

0

Figure 8. Gate–T o–Source and Drain–To–Source

V oltage versus Total Charge

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse re­covery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.

System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier de­vice, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 11. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.

The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ring­ing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

100

t, TIME (ns)

, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

DS

V

10

1.0 10 100

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

di/dts. The diode’s negative di/dt during ta is directly con­trolled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode charac­teristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.

Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse re­covery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise gen­erated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

t

d(on)

60

VGS = 0 V
TJ = 25

°

50

40

30

20

, SOURCE CURRENT (AMPS)

S

I

10

0

0.5 0.6 0.7 0.8 0.9 1.0

C

VSD, SOURCE–TO–DRAIN VOL TAGE (VOLTS)

Figure 10. Diode Forward V oltage versus Current

Motorola TMOS Power MOSFET Transistor Device Data

5

MTP60N05HDL

, SOURCE CURRENT

S

I

Figure 11. Reverse Recovery T ime (trr)

SAFE OPERATING AREA

t, TIME

Standard Cell Density

t

rr

High Cell Density

t

rr

t

b

t

a

The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for­ward biased. Curves are based upon maximum peak junc­tion temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance –
General Data and Its Use.”

Switching between the off–state and the on–state may tra­verse any load line provided neither rated peak current (IDM)
nor rated voltage (V

) is exceeded, and that the transition

DSS

time (tr, tf) does not exceed 10 µs. In addition the total power
averaged over a complete switching cycle must not exceed
(T

J(MAX)

– TC)/(R

θJC

).

A power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-

1000

VGS = 5.0 V
SINGLE PULSE
TC = 25

100

°

C

1.0 ms

able operation, the stored energy from circuit inductance dis­sipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction tem­perature.

Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur­rent (ID), in accordance with industry custom. The energy rat­ing must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at cur­rents below rated continuous ID can safely be assumed to
equal the values indicated.

600

ID = 60 A

500

400

300

10

, DRAIN CURRENT (AMPS)

D

I

1.0

0.1 1.0 10 100
VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C)

R

LIMIT

DS(on)

THERMAL LIMIT
PACKAGE LIMIT

Figure 12. Maximum Rated Forward Biased

Safe Operating Area

6

10 ms

dc

200

AVALANCHE ENERGY (mJ)

, SINGLE PULSE DRAIN–TO–SOURCE

100

AS

E

0

25 17550 100 15075

125

Figure 13. Maximum Avalanche Energy versus

Starting Junction T emperature

Motorola TMOS Power MOSFET Transistor Device Data

1.0
D = 0.5

0.1

0.05

0.02

(NORMALIZED)

0.01

r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

0.00001 0.0001 0.010.001

0.2

0.1

SINGLE PULSE

0.01

t, TIME (s)

Figure 14. Thermal Response

di/dt

I

S

t

t

a

P

(pk)

t

1

DUTY CYCLE, D = t1/t

rr

t

b

MTP60N05HDL

R

(t) = r(t) R

θ

JC

D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN

2

READ TIME AT t
T

J(pk)

t

2

0.1 1.0 10

TIME

– TC = P

θ

(pk)

JC

1

R

θ

JC

(t)

t

p

0.25 I

S

I

S

Figure 15. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

7

MTP60N05HDL

P ACKAGE DIMENSIONS

SEATING

–T–

PLANE

B

4

Q

123

F

T

A

U

H

K

Z

L

V

C

S

STYLE 5:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

R
J

G

D

N

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.

DIM MIN MAX MIN MAX

A 0.570 0.620 14.48 15.75
B 0.380 0.405 9.66 10.28
C 0.160 0.190 4.07 4.82
D 0.025 0.035 0.64 0.88

F 0.142 0.147 3.61 3.73
G 0.095 0.105 2.42 2.66
H 0.110 0.155 2.80 3.93

J 0.018 0.025 0.46 0.64
K 0.500 0.562 12.70 14.27

L 0.045 0.060 1.15 1.52
N 0.190 0.210 4.83 5.33
Q 0.100 0.120 2.54 3.04
R 0.080 0.110 2.04 2.79
S 0.045 0.055 1.15 1.39

T 0.235 0.255 5.97 6.47
U 0.000 0.050 0.00 1.27
V 0.045 ––– 1.15 –––

Z ––– 0.080 ––– 2.04

MILLIMETERSINCHES

CASE 221A–06

ISSUE Y

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
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Opportunity/Affirmative Action Employer.

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Motorola TMOS Power MOSFET Transistor Device Data

Mfax is a trademark of Motorola, Inc.

MTP60N05HDL/D