Datasheet MTP5N40E Datasheet (Motorola)

1

Motorola TMOS Power MOSFET Transistor Device Data

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   

N–Channel Enhancement–Mode Silicon Gate

This a dvanced h igh voltage TMOS E–FET is designed to
withstand high energy in the avalanche mode and switch efficiently.
This new high energy device also offers a drain–to–source diode
with fast recovery time. Designed for high voltage, high s peed
switching applications such a s power supplies, P WM motor
controls and other inductive loads, the avalanche energy capability
is specified to eliminate the guesswork in designs where inductive
loads are switched and offer additional s afety margin against
unexpected voltage transients.

• Avalanche Energy Capability Specified at Elevated

Temperature

• Low Stored Gate Charge for Efficient Switching

• Internal Source–to–Drain Diode Designed to Replace External

Zener Transient Suppressor — Absorbs High Energy in the
Avalanche Mode

• Source–to–Drain Diode Recovery Time Comparable to Discrete

Fast Recovery Diode

MAXIMUM RATINGS

(TC = 25°C unless otherwise noted)

Rating

Symbol Value Unit

Drain–Source Voltage V

DSS

400 Vdc

Drain–Gate Voltage (RGS = 1.0 MΩ) V

DGR

400 Vdc

Gate–Source Voltage — Continuous

Gate–Source Voltage — Non–repetitive

V

GS

V

GSM

±20
±40

Vdc
Vpk

Drain Current — Continuous

Drain Current — Pulsed

I

D

I

DM

5.0
12

Adc

Total Power Dissipation @ TC = 25°C

Derate above 25°C

P

D

75

0.6

Watts

W/°C

Operating and Storage Temperature Range TJ, T

stg

–55 to 150 °C

UNCLAMPED DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS (T

J

< 150°C)

Single Pulse Drain–to–Source Avalanche Energy — TJ = 25°C

Single Pulse Drain–to–Source Avalanche Energy — TJ = 100°C

Repetitive Pulse Drain–to–Source Avalanche Energy

W

DSR

(1)

W

DSR

(2)

290

46

7.4

mJ

THERMAL CHARACTERISTICS

Thermal Resistance — Junction to Case

Thermal Resistance — Junction to Ambient°

R

θJC

R

θJA

1.67

62.5

°C/W

Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T

L

260 °C

(1) VDD = 50 V, ID = 5.0 A
(2) Pulse Width and frequency is limited by TJ(max) and thermal response

Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics— are given to facilitate “worst case” design.

E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

Preferred devices are Motorola recommended choices for future use and best overall value.

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SEMICONDUCTOR TECHNICAL DATA



TMOS POWER FET

5.0 AMPERES
400 VOLTS

R

DS(on)

= 1.0 OHM



D

S

G

CASE 221A–06, Style 5

TO–220AB

Motorola Preferred Device

 Motorola, Inc. 1996

MTP5N40E

2

Motorola TMOS Power MOSFET Transistor Device Data

ELECTRICAL CHARACTERISTICS

(T

J

= 25°C unless otherwise noted)

Characteristic

Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Drain–to–Source Breakdown Voltage

(VGS = 0, ID = 250 µAdc)

V

(BR)DSS

400 — — Vdc

Zero Gate Voltage Drain Current

(VDS = 400 V, VGS = 0)
(VDS = 320 V, VGS = 0, TJ = 125°C)

I

DSS

—
—

—
—

0.25

1.0

mAdc

Gate–Body Leakage Current, Forward (V

GSF

= 20 Vdc, VDS = 0) I

GSSF

— — 100 nAdc

Gate–Body Leakage Current, Reverse (V

GSR

= 20 Vdc, VDS = 0) I

GSSR

— — 100 nAdc

ON CHARACTERISTICS*

Gate Threshold Voltage

(VDS = VGS, ID = 250 µAdc)
(TJ = 125°C)

V

GS(th)

2.0

1.5

—
—

4.0

3.5

Vdc

Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 2.5 Adc) R

DS(on)

— 0.8 1.0 Ohm

Drain–Source On–Voltage (VGS = 10 Vdc)

(ID = 5.0 A)
(ID = 2.5 A, TJ = 100°C)

V

DS(on)

—
—

—
—

6.2

5.0

Vdc

Forward Transconductance (VDS = 15 Vdc, ID = 2.5 Adc) g

FS

2.0 — — mhos

DYNAMIC CHARACTERISTICS

Input Capacitance

C

iss

— 775 — pF

Output Capacitance

(VDS = 25 V, VGS = 0,

f = 1.0 MHz)

C

oss

— 96 —

Transfer Capacitance

f = 1.0 MHz)

C

rss

— 22 —

SWITCHING CHARACTERISTICS*

Turn–On Delay Time

t

d(on)

— 24 — ns

Rise Time

≈ 5.0 A,

t

r

— 34 —

Turn–Off Delay Time

RG = 12 Ω, RL = 50 Ω,

V

GS(on)

= 10 V)

t

d(off)

— 60 —

Fall Time

GS(on)

= 10 V)

t

f

— 36 —

Total Gate Charge

Q

g

— 27 32 nC

Gate–Source Charge

(VDS = 320 V, ID = 5.0 A,

V

= 10 V)

Q

gs

— 3.5 —

Gate–Drain Charge

VGS = 10 V)

Q

gd

— 14 —

SOURCE–DRAIN DIODE CHARACTERISTICS*

Forward On–Voltage

V

SD

— — 1.4 Vdc

Forward Turn–On Time

µs)

t

on

**

Reverse Recovery Time t

rr

— — 660

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance

(Measured from the contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)

L

d

—
—

3.5

4.5

—
—

Internal Source Inductance

(Measured from the source lead 0.25″ from package to source bond pad)

L

s

— 7.5 —

*Indicates Pulse Test: Pulse Width = 300 µs Max, Duty Cycle ≤ 2.0%.

**Limited by circuit inductance.

(IS = 5.0 A, di/dt = 100 A/

(VDD = 250 V, ID

ns

nH

MTP5N40E

3

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 1. On–Region Characteristics

TJ, JUNCTION TEMPERATURE (°C)

Figure 2. Gate–Threshold Voltage Variation

With Temperature

VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)

Figure 3. Transfer Characteristics

TJ, JUNCTION TEMPERATURE (°C)

Figure 4. Breakdown Voltage Variation

With Temperature

ID, DRAIN CURRENT (AMPS)

Figure 5. On–Resistance versus Drain Current

TJ, JUNCTION TEMPERATURE (°C)

Figure 6. On–Resistance Variation

With Temperature

R

DS(on)

, DRAIN–TO–SOURCE RESISTANCE (OHMS)

R

DS(on)

, DRAIN–TO–SOURCE RESISTANCE

(NORMALIZED)

I

D

, DRAIN CURRENT (AMPS)

V

GS(th)

, GATE THRESHOLD VOLTAGE (NORMALIZED)

V

BR(DSS)

, DRAIN–TO–SOURCE BREAKDOWN

VOLTAGE (NORMALIZED)

10

8

6

4

2

201612840

1.2

1.1

1

0.9

0.8

–50 –25 0 25 50 75 100 125 150

10

8

6

4

2

0

86420

1.2

1.1

1

0.9

0.8

–50 0 50 100 150

2

1.6

1.2

0

1086420

2.5

0

TJ = 25°C

7 V

6 V

5 V

VDS = V

GS

ID = 0.25 mA

TJ = 25°C

–55°C

125°C

VGS = 0
ID = 0.25 mA

TJ = 100°C

25°C

–55°C

VGS = 10 V

VGS = 10 V
ID = 2.5 A

I

D

, DRAIN CURRENT (AMPS)

VGS = 10 V

VDS ≥ 10 V

10

–50 0 50 100 200

4 V

0

200

0.8

0.4

2

1.5

1

0.5

150

MTP5N40E

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Motorola TMOS Power MOSFET Transistor Device Data

SAFE OPERATING AREA INFORMATION

I

D

, DRAIN CURRENT (AMPS)

I

D

, DRAIN CURRENT (AMPS)

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 7. Maximum Rated Forward Biased

Safe Operating Area

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 8. Maximum Rated Switching

Safe Operating Area

0 100 200 300 400

0

14

100

R

DS(on)

LIMIT
THERMAL LIMIT
PACKAGE LIMIT

10

VGS = 20 V
SINGLE PULSE
TC = 25°C

1

100

10 µs

1 ms

10 ms

500

10

1

0.1

0.1 ms

TJ ≤ 150°C

1000

12

10

8

6

4

2

dc

FORWARD BIASED SAFE OPERATING AREA

The FBSOA curves define the maximum drain–to–source
voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned on.
Because these curves include the limitations of simultaneous
high voltage and high current, up to the rating of the device,
they are especially useful to designers of linear systems. The
curves are based on a case temperature of 25°C and a maxi­mum junction temperature of 150°C. Limitations for repetitive
pulses at various case temperatures can be determined by
using the thermal response curves. M otorola Application
Note, AN569, “Transient Thermal Resistance–General Data
and Its Use” provides detailed instructions.

SWITCHING SAFE OPERATING AREA

The switching safe operating area (SOA) of Figure 8 is the
boundary that the load line may traverse without incurring
damage to the MOSFET. The fundamental l imits are the
peak current, IDM and the breakdown voltage, V

(BR)DSS

. The
switching SOA shown in Figure 8 is applicable for both turn–
on and turn–off of the devices for switching times less than
one microsecond.

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

t, TIME (ns)

RG, GATE RESISTANCE (OHMS)

VDD = 250 V
ID = 5 A
VGS = 10 V
TJ = 25

°

C

t

f

t

d(off)

t

d(on)

10001

10000

10

100

1000

10 100

t

r

Figure 10. Thermal Response

r(t), NORMALIZED EFFECTIVE

TRANSIENT THERMAL RESISTANCE

R

θ

JC

(t) = r(t) R

θ

JC

R

θ

JC

= 1.67

°

C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t

1

T

J(pk)

– TC = P

(pk)

R

θ

JC

(t)

P

(pk)

t

1

t

2

DUTY CYCLE, D = t1/t

2

t, TIME (ms)

1

0.01

0.2

D = 0.5

0.05

0.01

SINGLE PULSE

0.1

0.01

0.02

0.03

0.02

0.05

0.1

0.2

0.3

0.5

0.02 0.05 0.1 0.2 0.5 1 2 5 10 20 50 100 200 500 1000

MTP5N40E

5

Motorola TMOS Power MOSFET Transistor Device Data

GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 11. Capacitance Variation

C, CAPACITANCE (pF)

V

GS

V

DS

VDS = 0 V

0

C

iss

C

oss

C

rss

2000

1500

1000

252010

0

510

Figure 12. Gate Charge versus

Gate–To–Source Voltage

Qg, TOTAL GATE CHARGE (nC)

16

0

0 20

12

8

4

30 40 50

5

15

500

VDS = 100 V

V

GS

, GATE SOURCE VOLTAGE (VOLTS)

TJ = 25°C
ID = 5 A

320 V

200 V

TJ = 25°C
VGS = 0

10

COMMUTATING SAFE OPERATING AREA (CSOA)

The C ommutating S afe Operating Area ( CSOA) o f
Figure 14 defines the limits of safe operation for commutated
source–drain current versus re–applied drain voltage when
the source–drain diode has undergone forward bias. The
curve shows the limitations of IFM and peak VDS for a given
rate of change of source current. It is applicable when wave­forms similar to those of Figure 11 are present. Full or half–
bridge PWM DC motor controllers are common applications
requiring CSOA data.

Device stresses increase with increasing rate of change of
source current so dIs/dt is specified with a maximum value.
Higher values of dIs/dt require an appropriate derating of IFM,
peak VDS or both. Ultimately dIs/dt is limited primarily by de­vice, package, and circuit impedances. Maximum device
stress occurs during trr as the diode goes from conduction to
reverse blocking.

V

DS(pk)

is the peak drain–to–source voltage that the device
must sustain during commutation; IFM is the maximum for­ward source–drain diode current just prior to the onset of
commutation.

VR is specified at 80% of V

(BR)DSS

to ensure that the

CSOA stress is maximized as IS decays from IRM to zero.

RGS should be minimized during commutation. TJ has only

a second order effect on CSOA.

Stray inductances in Motorola’s test circuit are assumed to
be practical minimums. dVDS/dt in excess of 10 V/ns was at­tained with dIs/dt of 400 A/µs.

I

D

, DRAIN CURRENT (AMPS)

Figure 13. Commutating Safe Operating Area (CSOA)

0 100 200 300 400

6

4

2

0

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

+

+

–

Figure 14. Commutating Safe Operating Area

Test Circuit

V

R

V

GS

I

FM

20 V

R

GS

DUT

I

S

L

i

VR = 80% OF RATED V

DS

V

dsL

= Vf + Li

⋅

dls/dt

+

–

di/dt ≤ 90 A/µs

500

V

DS

Figure 15. Commutating Waveforms

15 V

V

GS

0

90%

I

FM

dls/dt

I

S

10%

t

rr

I

RM

t

on

V

DS

V

f

V

dsL

dVDS/dt

V

DS(pk)

MAX. CSOA
STRESS AREA

V

R

0.25 I

RM

MTP5N40E

6

Motorola TMOS Power MOSFET Transistor Device Data

Figure 16. Unclamped Inductive Switching

Test Circuit

Figure 17. Unclamped Inductive Switching

Waveforms

t

L

V

DS

I

D

V

DD

t

P

V

(BR)DSS

V

DD

I

D(t)

C

4700

µ

F

250 V

R

GS

50

Ω

I

O

V

ds(t)

t, (TIME)

W

DSR

+

ǒ

1
2

L I

O

2

Ǔ

ǒ

V

(BR)DSS

V

(BR)DSS

– V

DD

Ǔ

RESISTIVE SWITCHING

PULSE GENERATOR

V

DD

V

out

V

in

R

gen

50

Ω

z = 12

Ω

50

Ω

DUT

R

L

Figure 18. Switching Test Circuit

t

off

OUTPUT, V

out

INVERTED

t

on

t

r

t

d(off)

t

f

t

d(on)

90%90%

10%

INPUT, V

in

10%

50%

90%

50%

PULSE WIDTH

Figure 19. Switching Waveforms

*Note: The Mirror is shorted to the Kelvin terminal for this test.

Figure 20. Gate Charge Test Circuit

V

in

15 V

100 k

47 k

2N3904

2N3904

1 mA

+18 V V

DD

10 V

100 k

0.1

µ

F

100

FERRITE

BEAD

DUT

SAME
DEVICE TYPE
AS DUT

Vin = 15 Vpk; PULSE WIDTH

≤

100 µs, DUTY CYCLE ≤ 10%

47 k

MTP5N40E

7

Motorola TMOS Power MOSFET Transistor Device Data

PACKAGE DIMENSIONS

CASE 221A–06

ISSUE Y

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.

STYLE 5:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.570 0.620 14.48 15.75
B 0.380 0.405 9.66 10.28
C 0.160 0.190 4.07 4.82
D 0.025 0.035 0.64 0.88
F 0.142 0.147 3.61 3.73

G 0.095 0.105 2.42 2.66

H 0.110 0.155 2.80 3.93
J 0.018 0.025 0.46 0.64
K 0.500 0.562 12.70 14.27
L 0.045 0.060 1.15 1.52
N 0.190 0.210 4.83 5.33

Q 0.100 0.120 2.54 3.04

R 0.080 0.110 2.04 2.79
S 0.045 0.055 1.15 1.39
T 0.235 0.255 5.97 6.47
U 0.000 0.050 0.00 1.27
V 0.045 ––– 1.15 –––
Z ––– 0.080 ––– 2.04

B

Q

H

Z

L

V

G

N

A

K

F

1 2 3

4

D

SEATING
PLANE

–T–

C

S

T

U

R
J

MTP5N40E

8

Motorola TMOS Power MOSFET Transistor Device Data

How to reach us:
USA /EUROPE: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,

P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters can and do vary in different
applications. All operating parameters, including “T ypicals” must be validated for each customer application by customer’s technical experts. Motorola does
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MTP5N40E/D

*MTP5N40E/D*

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