Datasheet MTP50P03HDL Datasheet (Motorola)

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SEMICONDUCTOR TECHNICAL DATA

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Motorola Preferred Device

   

P–Channel Enhancement–Mode Silicon Gate

This advanced high–cell density HDTMOS power FET is
designed to withstand high energy in the avalanche and commuta­tion modes. The new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for low
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.

• Avalanche Energy Specified

• Source–to–Drain Diode Recovery Time Comparable to a Dis-

crete Fast Recovery Diode

• Diode is Characterized for Use in Bridge Circuits

• I

MAXIMUM RATINGS

Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit

curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.

Designer’s, E–FET and HDTMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

and V

DSS

Drain–Source Voltage V
Drain–Gate Voltage (RGS = 1.0 MΩ) V
Gate–Source Voltage — Continuous

— Non–Repetitive (tp ≤ 10 ms)
Drain Current — Continuous

Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)

Total Power Dissipation

Derate above 25°C
Operating and Storage Temperature Range TJ, T
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C

(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 50 Apk, L = 1.0 mH, RG = 25 Ω)
Thermal Resistance — Junction to Case

Thermal Resistance — Junction to Ambient, when mounted with the minimum recommended pad size

Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T

Specified at Elevated Temperature

DS(on)

(TC = 25°C unless otherwise noted)

D

G

S

Rating

TMOS POWER FET

LOGIC LEVEL

50 AMPERES

30 VOLTS

R

CASE 221A–06, Style 5

Symbol Value Unit

DSS

DGR

V

GS

V

GSM

I

D

I

D

I

DM
P

D

E

AS

R

θJC

R

θJA

L

= 0.025 OHM

DS(on)

TO–220AB

± 15
± 20

150
125

–55 to 150 °C

stg

1250 mJ

62.5
260 °C

30 Vdc
30 Vdc

Vdc
Vpk

50
31

1.0

1.0

Adc

Apk

Watts

W/°C

°C/W

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

Motorola TMOS Power MOSFET Transistor Device Data

 Motorola, Inc. 1997

1

MTP50P03HDL

)

f = 1.0 MHz)

V

RG 2.3 Ω)

(

DS

,

D

,

(

S

,

GS

,

ELECTRICAL CHARACTERISTICS

OFF CHARACTERISTICS

Drain–to–Source Breakdown Voltage (Cpk ≥ 2.0) (3)

(VGS = 0 Vdc, ID = 250 µAdc)
T emperature Coef ficient (Positive)

Zero Gate Voltage Drain Current

(VDS = 30 Vdc, VGS = 0 Vdc)
(VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125°C)

Gate–Body Leakage Current

(VGS = ± 15 Vdc, VDS = 0 Vdc)

ON CHARACTERISTICS (1)

Gate Threshold Voltage (Cpk ≥ 3.0) (3)

(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)

Static Drain–to–Source On–Resistance (Cpk ≥ 3.0) (3)

(VGS = 5.0 Vdc, ID = 25 Adc)

Drain–to–Source On–Voltage (VGS = 10 Vdc)

(ID = 50 Adc)
(ID = 25 Adc, TJ = 125°C)

Forward Transconductance

(VDS = 5.0 Vdc, ID = 25 Adc)

DYNAMIC CHARACTERISTICS

Input Capacitance
Output Capacitance
Transfer Capacitance

SWITCHING CHARACTERISTICS (2)

Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge

(See Figure 8)

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage

Reverse Recovery Time

(See Figure 15)

Reverse Recovery Stored Charge Q

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance

(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)

Internal Source Inductance

(Measured from the source lead 0.25″ from package to source bond pad)

(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.

Cpk =

(TJ = 25°C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit

(VDS = 25 Vdc, VGS = 0 Vdc,

(IS = 50 Adc, VGS = 0 Vdc, TJ = 125°C)

Max limit – Typ

3 x SIGMA

f = 1.0 MHz

(VDD = 15 Vdc, ID = 50 Adc,

(VDS = 24 Vdc, ID = 50 Adc,

(IS =50 Adc, VGS = 0 Vdc)

(IS = 50 Adc, VGS = 0 Vdc,

= 5.0 Vdc,

GS
RG = 2.3 Ω)

VGS = 5.0 Vdc)

dIS/dt = 100 A/µs)

V

(BR)DSS

I

DSS

I

GSS

V

GS(th)

R

DS(on)

V

DS(on)

g

FS

C

iss

C

oss

C

rss

t

d(on)

t

r

t

d(off)

t

f

Q
Q
Q
Q

V

SD

t

rr

t

a

t

b

RR

L

D

L

S

30
—

—
—

— — 100

1.0
—

— 0.020 0.025

—
—

15 20 —

— 3500 4900 pF
— 1550 2170
— 550 770

— 22 30 ns
— 340 466
— 90 117
— 218 300

T
1
2
3

— 74 100 nC
— 13.6 —
— 44.8 —
— 35 —

—
—

— 106 —
— 58 —
— 48 —
— 0.246 — µ C

—
—

— 7.5 —

—
26

—
—

1.5

4.0

0.83
—

2.39

1.84

3.5

4.5

—
—

1.0
10

2.0
—

1.5

1.3

3.0
—

—
—

Vdc

mV/°C

µAdc

nAdc

Vdc

mV/°C

Ohm

Vdc

mhos

Vdc

ns

nH

nH

2

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

MTP50P03HDL

100

TJ = 25°C

80

60

40

, DRAIN CURRENT (AMPS)

D

I

20

0

0 0.4 0.8 1.2 1.6 2.00.2 0.6 1.0 1.4 1.8

VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS) VGS, GATE–T O–SOURCE VOLT AGE (VOLTS)

VGS = 10 V

8 V

6 V

Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics

0.029
V

= 5.0 V

GS

0.027

0.025

0.023

0.021

TJ = 100°C

25°C

5 V

4.5 V

4 V

3.5 V

3 V

2.5 V

100

VDS ≥ 10 V

80

60

40

, DRAIN CURRENT (AMPS)

D

I

20

0

1.5 1.9 2.3 2.7 3.5 4.33.1 3.9

0.022
TJ = 25°C

0.021

0.020

0.019

0.018

VGS = 5 V

TJ = – 55°C

25°C

100°C

0.019

, DRAIN–TO–SOURCE RESIST ANCE (OHMS)

0.017

DS(on)

0.015

R

020406080100

ID, DRAIN CURRENT (AMPS)

–55°C

Figure 3. On–Resistance versus Drain Current

and T emperature

1.35
VGS = 5 V
ID = 25 A

1.25

1.15

1.05

(NORMALIZED)

, DRAIN–TO–SOURCE RESIST ANCE

0.95

DS(on)

R

0.85

– 50 – 25 0 25 50 75 100 125 150

TJ, JUNCTION TEMPERATURE (

°

C)

0.017

, DRAIN–TO–SOURCE RESIST ANCE (OHMS)

0.016

0.015

DS(on)

R

020406080100

ID, DRAIN CURRENT (AMPS)

10 V

Figure 4. On–Resistance versus Drain Current

and Gate Voltage

1000

VGS = 0 V

TJ = 125°C

100

, LEAKAGE (nA)

DSS

I

100°C

10

0 5 10 20 25 30

VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

15

Figure 5. On–Resistance Variation with

Temperature

Motorola TMOS Power MOSFET Transistor Device Data

Figure 6. Drain–T o–Source Leakage

Current versus Voltage

3

MTP50P03HDL

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter­mined by how fast the FET input capacitance can be charged
by current from the generator.

The published capacitance data is difficult to use for calculat­ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly , gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I

) can be made from a rudimentary analysis of

G(A V)

the drive circuit so that
t = Q/I

G(AV)

During the rise and fall time interval when switching a resis­tive load, VGS remains virtually constant at a level known as
the plateau voltage, V

. Therefore, rise and fall times may

SGP

be approximated by the following:
tr = Q2 x RG/(VGG – V
tf = Q2 x RG/V

GSP

GSP

)

where
VGG = the gate drive voltage, which varies from zero to V

GG

RG = the gate drive resistance
and Q2 and V

are read from the gate charge curve.

GSP

During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val­ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

t

d(on)

t

d(off)

= RG C

= RG C

In [VGG/(VGG – V

iss

In (VGG/V

iss

GSP

)]

GSP

)

The capacitance (C

) is read from the capacitance curve at

iss

a voltage corresponding to the off–state condition when cal­culating t
on–state when calculating t

and is read at a voltage corresponding to the

d(on)

d(off)

.

At high switching speeds, parasitic circuit elements com­plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func­tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea­sure and, consequently , is not specified.

The resistive switching time variation versus gate resis­tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op­erated into an inductive load; however, snubbing reduces
switching losses.

14000

VDS = 0 V

12000

C

10000

C, CAPACITANCE (pF)

iss

8000

6000

C

rss

4000

2000

0

10 0 10 15 20 25

55

GATE–T O–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)

VGS = 0 V

C

rss

V

GS

V

DS

T

C

iss

C

oss

Figure 7. Capacitance Variation

= 25°C

J

4

Motorola TMOS Power MOSFET Transistor Device Data

6 30

QT

5

Q1

4

3

Q2

V

GS

25

20

15

1000

VDD = 30 V ID = 50 A
VGS = 10 V TJ = 25

100

MTP50P03HDL

°

C

t

d(off)

t

r

t

f

2

, GATE–T O–SOURCE VOLT AGE (VOLTS)

1

GS

V

0

010 40 60708030 50

Q3

20

QT, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (Ohms)

ID = 50 A
TJ = 25

V

DS

10

°

C

5

0

Figure 8. Gate–T o–Source and Drain–To–Source

V oltage versus Total Charge

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse re­covery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.

System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier de­vice, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 12. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.

The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ring­ing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

t, TIME (ns)

t

, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

DS

V

10

110

d(on)

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

di/dts. The diode’s negative di/dt during ta is directly con­trolled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode charac­teristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.

Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse re­covery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise gen­erated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

50

VGS = 0 V
TJ = 25

°

C

40

30

20

, SOURCE CURRENT (AMPS)

S

I

10

0

0.4 0.8 1.2 1.6 2.0 2.4

0.6 1.0 1.4 1.8 2.2
VSD, SOURCE–TO–DRAIN VOL TAGE (VOLTS)

Figure 10. Diode Forward V oltage versus Current

Motorola TMOS Power MOSFET Transistor Device Data

5

MTP50P03HDL

di/dt = 300 A/µs

, SOURCE CURRENT

S

I

Figure 11. Reverse Recovery T ime (trr)

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for­ward biased. Curves are based upon maximum peak junc­tion temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance —
General Data and Its Use.”

Switching between the off–state and the on–state may tra­verse any load line provided neither rated peak current (IDM)
nor rated voltage (V
time (tr, tf) does not exceed 10 µs. In addition the total power
averaged over a complete switching cycle must not exceed
(T

J(MAX)

– TC)/(R

A power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-

) is exceeded, and that the transition

DSS

).

θJC

Standard Cell Density

t

rr

High Cell Density

t

rr

t

b

t

a

t, TIME

able operation, the stored energy from circuit inductance dis­sipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction tem­perature.

Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur­rent (ID), in accordance with industry custom. The energy rat­ing must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at cur­rents below rated continuous ID can safely be assumed to
equal the values indicated.

1000

VGS = 20 V
SINGLE PULSE

°

C

TC = 25

100

10

, DRAIN CURRENT (AMPS)

D

I

1

0.1 1.0 10 100
VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C)

R

LIMIT

DS(on)

THERMAL LIMIT
PACKAGE LIMIT

100 µs

1 ms
10 ms

dc

Figure 12. Maximum Rated Forward Biased

Safe Operating Area

6

1400

1200

1000

800

600

400

AVALANCHE ENERGY (mJ)

, SINGLE PULSE DRAIN–TO–SOURCE

200

AS

E

0

25 15050 100 12575

ID = 50 A

Figure 13. Maximum Avalanche Energy versus

Starting Junction T emperature

Motorola TMOS Power MOSFET Transistor Device Data

1.0

MTP50P03HDL

D = 0.5

0.2

0.1

0.1

0.05

0.02

(NORMALIZED)

0.01

SINGLE PULSE

0.01

1.0E–05 1.0E–04 1.0E–021.0E–03

r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

t, TIME (s)

Figure 14. Thermal Response

di/dt

I

S

t

a

t

p

P

(pk)

t

1

DUTY CYCLE, D = t1/t

t

rr

t

b

0.25 I

S

I

S

t

2

0.1

1.0E–01

TIME

R

(t) = r(t) R

θ

JC

D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
T

J(pk)

2

θ

JC

– TC = P

1

R

(pk)

1.0E+00 1.0E+01

(t)

θ

JC

Figure 15. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

7

MTP50P03HDL

P ACKAGE DIMENSIONS

SEATING

–T–

PLANE

B

4

Q

123

F

T

A

U

H

K

Z

L

V

C

S

STYLE 5:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

R
J

G

D

N

CASE 221A–06

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.

DIM MIN MAX MIN MAX

A 0.570 0.620 14.48 15.75
B 0.380 0.405 9.66 10.28
C 0.160 0.190 4.07 4.82
D 0.025 0.035 0.64 0.88
F 0.142 0.147 3.61 3.73
G 0.095 0.105 2.42 2.66
H 0.110 0.155 2.80 3.93
J 0.018 0.025 0.46 0.64
K 0.500 0.562 12.70 14.27
L 0.045 0.060 1.15 1.52
N 0.190 0.210 4.83 5.33
Q 0.100 0.120 2.54 3.04
R 0.080 0.110 2.04 2.79
S 0.045 0.055 1.15 1.39
T 0.235 0.255 5.97 6.47
U 0.000 0.050 0.00 1.27
V 0.045 ––– 1.15 –––
Z ––– 0.080 ––– 2.04

MILLIMETERSINCHES

ISSUE Y

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.

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Motorola TMOS Power MOSFET Transistor Device Data

Mfax is a trademark of Motorola, Inc.

MTP50P03HDL/D