Datasheet MTP4N40E Datasheet (Motorola)

1

Motorola TMOS Power MOSFET Transistor Device Data

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 

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   

N–Channel Enhancement–Mode Silicon Gate

This high voltage MOSFET uses an advanced t ermination
scheme to provide enhanced voltage–blocking capability without
degrading performance over time. In addition, this advanced TMOS
E–FET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.

• Robust High Voltage Termination

• Avalanche Energy Specified

• Source–to–Drain Diode Recovery Time Comparable to a Discrete

Fast Recovery Diode

• Diode is Characterized for Use in Bridge Circuits

• I

DSS

and V

DS(on)

Specified at Elevated Temperature

MAXIMUM RATINGS

(TC = 25°C unless otherwise noted)

Rating

Symbol Value Unit

Drain–to–Source Voltage V

DSS

400 Vdc

Drain–to–Gate Voltage (RGS = 1.0 MΩ) V

DGR

400 Vdc

Gate–to–Source Voltage — Continuous

— Non–Repetitive (tp ≤ 10 ms)

V

GS

V

GSM

±20
±40

Vdc
Vpk

Drain Current — Continuous

— Continuous @ 100°C
— Single Pulse (tp ≤ 10 µs)

I

D

I

D

I

DM

4.0

3.0
14

Adc

Apk

Total Power Dissipation

Derate above 25°C

P

D

74

0.59

Watts

W/°C

Operating and Storage Temperature Range TJ, T

stg

–55 to 150 °C

Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C

(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 4.0 Apk, L = 25 mH, RG = 25 Ω)

E

AS

200

mJ

Thermal Resistance — Junction to Case

— Junction to Ambient

R

θJC

R

θJA

1.7

62.5

°C/W

Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T

L

260 °C

Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.

E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

Preferred devices are Motorola recommended choices for future use and best overall value.

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SEMICONDUCTOR TECHNICAL DATA



TMOS POWER FET

4.0 AMPERES
400 VOLTS

R

DS(on)

= 1.8 OHM

Motorola Preferred Device



D

S

G

CASE 221A–06, Style 5

TO–220AB

 Motorola, Inc. 1996

MTP4N40E

2

Motorola TMOS Power MOSFET Transistor Device Data

ELECTRICAL CHARACTERISTICS

(T

J

= 25°C unless otherwise noted)

Characteristic

Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Drain–to–Source Breakdown Voltage

(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)

V

(BR)DSS

400

—

—

420

—
—

Vdc

mV/°C

Zero Gate Voltage Drain Current

(VDS = 400 Vdc, VGS = 0 Vdc)
(VDS = 400 Vdc, VGS = 0 Vdc, TJ = 125°C)

I

DSS

—
—

—
—

10

100

µAdc

Gate–Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) I

GSS

— — 100 nAdc

ON CHARACTERISTICS

(1)

Gate Threshold Voltage

(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)

V

GS(th)

2.0
—

3.0

6.0

4.0
—

Vdc

mV/°C

Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 2.0 Adc) R

DS(on)

— 1.3 1.8 Ohms

Drain–to–Source On–Voltage

(VGS = 10 Vdc, ID = 4.0 Adc)
(VGS = 10 Vdc, ID = 2.0 Adc, TJ = 125°C)

V

DS(on)

—
—

—
—

8.6

4.3

Vdc

Forward Transconductance (VDS = 15 Vdc, ID = 2.0 Adc) g

FS

1.8 2.5 — mhos

DYNAMIC CHARACTERISTICS

Input Capacitance

C

iss

— 440 616 pF

Output Capacitance

(VDS = 25 Vdc, VGS = 0 Vdc,

f = 1.0 MHz)

C

oss

— 72 100

Reverse Transfer Capacitance

f = 1.0 MHz)

C

rss

— 14 19.6

SWITCHING CHARACTERISTICS

(2)

Turn–On Delay Time

t

d(on)

— 9.0 20 ns

Rise Time

t

r

— 11 30

Turn–Off Delay Time

VGS = 10 Vdc,

RG = 9.1 Ω)

t

d(off)

— 18 30

Fall Time

G

= 9.1 Ω)

t

f

— 14 30

Q

T

— 13 21 nC

DS

= 320 Vdc, ID = 4.0 Adc,

Q

1

— 2.5 —

(VDS = 320 Vdc, ID = 4.0 Adc,

VGS = 10 Vdc)

Q

2

— 6.0 —

Q

3

— 7.0 —

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage

(IS = 4.0 Adc, VGS = 0 Vdc)

(IS = 4.0 Adc, VGS = 0 Vdc, TJ = 125°C)

V

SD

—
—

0.9

0.78

1.6
—

Vdc

t

rr

— 200 —

S

= 4.0 Adc, VGS = 0 Vdc,

t

a

— 99 —

(IS = 4.0 Adc, VGS = 0 Vdc,

dIS/dt = 100 A/µs)

t

b

— 101 —

Reverse Recovery Stored Charge Q

RR

— 1.03 — µC

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance

(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)

L

D

—
—

3.5

4.5

—
—

nH

Internal Source Inductance

(Measured from the source lead 0.25″ from package to source bond pad)

L

S

— 7.5 —

nH

(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.

Gate Charge

Reverse Recovery Time

(VDD = 200 Vdc, ID = 4.0 Adc,

(V

(I

ns

MTP4N40E

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Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

R

DS(on)

, DRAIN–TO–SOURCE RESISTANCE

(NORMALIZED)

R

DS(on)

, DRAIN–TO–SOURCE RESISTANCE (OHMS)

R

DS(on)

, DRAIN–TO–SOURCE RESISTANCE (OHMS)

0 4 8 12 16 20

0

3

5

6

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 1. On–Region Characteristics

I

D

, DRAIN CURRENT (AMPS)

I

D

, DRAIN CURRENT (AMPS)

VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

0 1 2 4

0

0.5

1.5

2.5

3.5

0 1 4 6

0.5

1

1.5

2

ID, DRAIN CURRENT (AMPS)

Figure 3. On–Resistance versus Drain Current

and Temperature

ID, DRAIN CURRENT (AMPS)

Figure 4. On–Resistance versus Drain Current

and Gate Voltage

–50

0

0.5

1.25

2.0

100 200 300 400

1

10

100

1000

TJ, JUNCTION TEMPERATURE (

°

C)

Figure 5. On–Resistance Variation with

Temperature

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 6. Drain–To–Source Leakage

Current versus Voltage

I

DSS

, LEAKAGE (nA)

–25 0 25 50 75 100 125 150

TJ = 25°C

VDS ≥ 10 V

TJ = –55°C

25°C

100°C

TJ = 100°C

25°C

–55°C

TJ = 25°C

VGS = 10 V

2

4

2 6 10 14 18

1

9 V

5 V

6 V

7 V

8 V

VGS = 10 V

0

3

5

6

2

4

1

2 3 4 5 6 7 8 9

3

2

1

3 5 6

2.25

1.75

1.25

0.75

2 3 5

0.75

2.5

150 250 350

VGS = 10 V

15 V

VGS = 10 V
ID = 2 A

0.25

1.5

2.25

1.0

1.75

500

VGS = 0 V

TJ = 125°C

100°C

7

8

7

8

2.5 3.5 4.5 5.5 6.5 7.5 8.5

4

7 8

70.5 1.5 4.5 6.52.5 3.5 5.5 7.5

MTP4N40E

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Motorola TMOS Power MOSFET Transistor Device Data

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter­mined by how fast the FET input capacitance can be charged
by current from the generator.

The published capacitance data is difficult to use for calculat­ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly , gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I

G(AV)

) can be made from a rudimentary analysis of

the drive circuit so that
t = Q/I

G(AV)

During the rise and fall time interval when switching a resis­tive load, VGS remains virtually constant at a level known as
the plateau voltage, V

SGP

. Therefore, rise and fall times may

be approximated by the following:
tr = Q2 x RG/(VGG – V

GSP

)

tf = Q2 x RG/V

GSP

where
VGG = the gate drive voltage, which varies from zero to V

GG

RG = the gate drive resistance
and Q2 and V

GSP

are read from the gate charge curve.

During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val­ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

t

d(on)

= RG C

iss

In [VGG/(VGG – V

GSP

)]

t

d(off)

= RG C

iss

In (VGG/V

GSP

)

The capacitance (C

iss

) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal­culating t

d(on)

and is read at a voltage corresponding to the

on–state when calculating t

d(off)

.

At high switching speeds, parasitic circuit elements com­plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func­tion of drain current, the mathematical solution is complex.
The M OSFET output c apacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea­sure and, consequently, is not specified.

The resistive switching time variation versus gate resis­tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op­erated into an inductive load; however, snubbing reduces
switching losses.

10 0 10 15 20 25

GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)

C, CAPACITANCE (pF)

Figure 7. Capacitance Variation

700

500

300

100

0

V

GS

V

DS

TJ = 25°C

VDS = 0 V

VGS = 0 V

600

400

200

5 5

C

iss

C

oss

C

iss

C

rss

C

rss

800

MTP4N40E

5

Motorola TMOS Power MOSFET Transistor Device Data

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

0.55 0.6 0.7

0.8

0.90.5

0

0.8

2

2.4

VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)

Figure 8. Gate–To–Source and Drain–To–Source

Voltage versus Total Charge

I

S

, SOURCE CURRENT (AMPS)

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

RG, GATE RESISTANCE (OHMS)

1 10 100

10

t, TIME (ns)

t

r

t

f

t

d(off)

t

d(on)

VGS = 0 V
TJ = 25

°

C

Figure 10. Diode Forward Voltage versus Current

500

V

GS

, GATE–TO–SOURCE VOLTAGE (VOLTS)

450
400
350
300
250
200

0

9

7

4

0

QG, TOTAL GATE CHARGE (nC)

V

DS

, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

10

8

2

1 2 3 4 9

TJ = 25°C
ID = 4 A

V

DS

V

GS

5

0

Q1 Q2

QT

Q3

100

0.4

1.2

0.65 0.75 0.85

VDD = 200 V
ID = 4 A
VGS = 10 V
TJ = 25

°

C

6 7 8

6
5

3

1

150
100
50

1

1.6

11

12

10 11 12 13 14 15

550

600

2.8

3.2

3.6

4

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for­ward biased. Curves are based upon maximum peak junc­tion temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–General
Data and Its Use.”

Switching between the off–state and the on–state may tra­verse any load line provided neither rated peak current (IDM)
nor rated voltage (V

DSS

) is exceeded and the transition time
(tr,tf) do not exceed 10 µs. In addition the total power aver­aged over a complete s witching cycle m ust not e xceed
(T

J(MAX)

– TC)/(R

θJC

).

A Power MOSFET designated E–FET can be safely used

in switching circuits with unclamped inductive loads. For reli-

able operation, the stored energy from circuit inductance dis­sipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a con­stant. The energy rating decreases non–linearly with an in­crease of peak current in a valanche and peak junction
temperature.

Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur­rent (ID), in accordance with industry custom. The energy rat­ing must be d erated f or temperature as s hown in the
accompanying graph (Figure 12). Maximum energy at cur­rents below rated continuous ID can safely be assumed to
equal the values indicated.

MTP4N40E

6

Motorola TMOS Power MOSFET Transistor Device Data

SAFE OPERATING AREA

TJ, STARTING JUNCTION TEMPERATURE (°C)

E

AS

, SINGLE PULSE DRAIN–TO–SOURCE

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

0.1 1.0 100
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Avalanche Energy versus

Starting Junction Temperature

0.1

10

AVALANCHE ENERGY (mJ)

I

D

, DRAIN CURRENT (AMPS)

R

DS(on)

LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0

25 50 75 100 125

40
20

ID = 4 A

100

1.0

10 150

t, TIME (s)

Figure 13. Thermal Response

r(t), NORMALIZED EFFECTIVE

TRANSIENT THERMAL RESISTANCE

R

θ

JC

(t) = r(t) R

θ

JC

D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t

1

T

J(pk)

– TC = P

(pk)

R

θ

JC

(t)

P

(pk)

t

1

t

2

DUTY CYCLE, D = t1/t

2

Figure 14. Diode Reverse Recovery Waveform

di/dt

t

rr

t

a

t

p

I

S

0.25 I

S

TIME

I

S

t

b

VGS = 20 V
SINGLE PULSE

TC = 25

°

C

0.2

0.1

0.05

0.02

0.01

SINGLE PULSE

D = 0.5

120

80
60

100

0.1

1.0

0.01

100µs

1 ms

10 ms

dc

1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01

10µs

0.01

200

160
140

180

MTP4N40E

7

Motorola TMOS Power MOSFET Transistor Device Data

PACKAGE DIMENSIONS

CASE 221A–06

(TO–220AB)

ISSUE Y

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.

STYLE 5:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.570 0.620 14.48 15.75
B 0.380 0.405 9.66 10.28
C 0.160 0.190 4.07 4.82
D 0.025 0.035 0.64 0.88
F 0.142 0.147 3.61 3.73
G 0.095 0.105 2.42 2.66
H 0.110 0.155 2.80 3.93
J 0.018 0.025 0.46 0.64
K 0.500 0.562 12.70 14.27
L 0.045 0.060 1.15 1.52
N 0.190 0.210 4.83 5.33
Q 0.100 0.120 2.54 3.04
R 0.080 0.110 2.04 2.79
S 0.045 0.055 1.15 1.39
T 0.235 0.255 5.97 6.47
U 0.000 0.050 0.00 1.27
V 0.045 ––– 1.15 –––
Z ––– 0.080 ––– 2.04

B

Q

H

Z

L

V

G

N

A

K

F

1 2 3

4

D

SEATING
PLANE

–T–

C

S

T

U

R
J

MTP4N40E

8

Motorola TMOS Power MOSFET Transistor Device Data

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability , including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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